Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #ifndef __AMDGPU_H__
29 : #define __AMDGPU_H__
30 :
31 : #ifdef pr_fmt
32 : #undef pr_fmt
33 : #endif
34 :
35 : #define pr_fmt(fmt) "amdgpu: " fmt
36 :
37 : #ifdef dev_fmt
38 : #undef dev_fmt
39 : #endif
40 :
41 : #define dev_fmt(fmt) "amdgpu: " fmt
42 :
43 : #include "amdgpu_ctx.h"
44 :
45 : #include <linux/atomic.h>
46 : #include <linux/wait.h>
47 : #include <linux/list.h>
48 : #include <linux/kref.h>
49 : #include <linux/rbtree.h>
50 : #include <linux/hashtable.h>
51 : #include <linux/dma-fence.h>
52 : #include <linux/pci.h>
53 : #include <linux/aer.h>
54 :
55 : #include <drm/ttm/ttm_bo_api.h>
56 : #include <drm/ttm/ttm_bo_driver.h>
57 : #include <drm/ttm/ttm_placement.h>
58 : #include <drm/ttm/ttm_execbuf_util.h>
59 :
60 : #include <drm/amdgpu_drm.h>
61 : #include <drm/drm_gem.h>
62 : #include <drm/drm_ioctl.h>
63 :
64 : #include <kgd_kfd_interface.h>
65 : #include "dm_pp_interface.h"
66 : #include "kgd_pp_interface.h"
67 :
68 : #include "amd_shared.h"
69 : #include "amdgpu_mode.h"
70 : #include "amdgpu_ih.h"
71 : #include "amdgpu_irq.h"
72 : #include "amdgpu_ucode.h"
73 : #include "amdgpu_ttm.h"
74 : #include "amdgpu_psp.h"
75 : #include "amdgpu_gds.h"
76 : #include "amdgpu_sync.h"
77 : #include "amdgpu_ring.h"
78 : #include "amdgpu_vm.h"
79 : #include "amdgpu_dpm.h"
80 : #include "amdgpu_acp.h"
81 : #include "amdgpu_uvd.h"
82 : #include "amdgpu_vce.h"
83 : #include "amdgpu_vcn.h"
84 : #include "amdgpu_jpeg.h"
85 : #include "amdgpu_mn.h"
86 : #include "amdgpu_gmc.h"
87 : #include "amdgpu_gfx.h"
88 : #include "amdgpu_sdma.h"
89 : #include "amdgpu_lsdma.h"
90 : #include "amdgpu_nbio.h"
91 : #include "amdgpu_hdp.h"
92 : #include "amdgpu_dm.h"
93 : #include "amdgpu_virt.h"
94 : #include "amdgpu_csa.h"
95 : #include "amdgpu_mes_ctx.h"
96 : #include "amdgpu_gart.h"
97 : #include "amdgpu_debugfs.h"
98 : #include "amdgpu_job.h"
99 : #include "amdgpu_bo_list.h"
100 : #include "amdgpu_gem.h"
101 : #include "amdgpu_doorbell.h"
102 : #include "amdgpu_amdkfd.h"
103 : #include "amdgpu_discovery.h"
104 : #include "amdgpu_mes.h"
105 : #include "amdgpu_umc.h"
106 : #include "amdgpu_mmhub.h"
107 : #include "amdgpu_gfxhub.h"
108 : #include "amdgpu_df.h"
109 : #include "amdgpu_smuio.h"
110 : #include "amdgpu_fdinfo.h"
111 : #include "amdgpu_mca.h"
112 : #include "amdgpu_ras.h"
113 :
114 : #define MAX_GPU_INSTANCE 16
115 :
116 : struct amdgpu_gpu_instance
117 : {
118 : struct amdgpu_device *adev;
119 : int mgpu_fan_enabled;
120 : };
121 :
122 : struct amdgpu_mgpu_info
123 : {
124 : struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
125 : struct mutex mutex;
126 : uint32_t num_gpu;
127 : uint32_t num_dgpu;
128 : uint32_t num_apu;
129 :
130 : /* delayed reset_func for XGMI configuration if necessary */
131 : struct delayed_work delayed_reset_work;
132 : bool pending_reset;
133 : };
134 :
135 : enum amdgpu_ss {
136 : AMDGPU_SS_DRV_LOAD,
137 : AMDGPU_SS_DEV_D0,
138 : AMDGPU_SS_DEV_D3,
139 : AMDGPU_SS_DRV_UNLOAD
140 : };
141 :
142 : struct amdgpu_watchdog_timer
143 : {
144 : bool timeout_fatal_disable;
145 : uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
146 : };
147 :
148 : #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
149 :
150 : /*
151 : * Modules parameters.
152 : */
153 : extern int amdgpu_modeset;
154 : extern int amdgpu_vram_limit;
155 : extern int amdgpu_vis_vram_limit;
156 : extern int amdgpu_gart_size;
157 : extern int amdgpu_gtt_size;
158 : extern int amdgpu_moverate;
159 : extern int amdgpu_audio;
160 : extern int amdgpu_disp_priority;
161 : extern int amdgpu_hw_i2c;
162 : extern int amdgpu_pcie_gen2;
163 : extern int amdgpu_msi;
164 : extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
165 : extern int amdgpu_dpm;
166 : extern int amdgpu_fw_load_type;
167 : extern int amdgpu_aspm;
168 : extern int amdgpu_runtime_pm;
169 : extern uint amdgpu_ip_block_mask;
170 : extern int amdgpu_bapm;
171 : extern int amdgpu_deep_color;
172 : extern int amdgpu_vm_size;
173 : extern int amdgpu_vm_block_size;
174 : extern int amdgpu_vm_fragment_size;
175 : extern int amdgpu_vm_fault_stop;
176 : extern int amdgpu_vm_debug;
177 : extern int amdgpu_vm_update_mode;
178 : extern int amdgpu_exp_hw_support;
179 : extern int amdgpu_dc;
180 : extern int amdgpu_sched_jobs;
181 : extern int amdgpu_sched_hw_submission;
182 : extern uint amdgpu_pcie_gen_cap;
183 : extern uint amdgpu_pcie_lane_cap;
184 : extern u64 amdgpu_cg_mask;
185 : extern uint amdgpu_pg_mask;
186 : extern uint amdgpu_sdma_phase_quantum;
187 : extern char *amdgpu_disable_cu;
188 : extern char *amdgpu_virtual_display;
189 : extern uint amdgpu_pp_feature_mask;
190 : extern uint amdgpu_force_long_training;
191 : extern int amdgpu_job_hang_limit;
192 : extern int amdgpu_lbpw;
193 : extern int amdgpu_compute_multipipe;
194 : extern int amdgpu_gpu_recovery;
195 : extern int amdgpu_emu_mode;
196 : extern uint amdgpu_smu_memory_pool_size;
197 : extern int amdgpu_smu_pptable_id;
198 : extern uint amdgpu_dc_feature_mask;
199 : extern uint amdgpu_dc_debug_mask;
200 : extern uint amdgpu_dc_visual_confirm;
201 : extern uint amdgpu_dm_abm_level;
202 : extern int amdgpu_backlight;
203 : extern struct amdgpu_mgpu_info mgpu_info;
204 : extern int amdgpu_ras_enable;
205 : extern uint amdgpu_ras_mask;
206 : extern int amdgpu_bad_page_threshold;
207 : extern bool amdgpu_ignore_bad_page_threshold;
208 : extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
209 : extern int amdgpu_async_gfx_ring;
210 : extern int amdgpu_mcbp;
211 : extern int amdgpu_discovery;
212 : extern int amdgpu_mes;
213 : extern int amdgpu_mes_kiq;
214 : extern int amdgpu_noretry;
215 : extern int amdgpu_force_asic_type;
216 : extern int amdgpu_smartshift_bias;
217 : extern int amdgpu_use_xgmi_p2p;
218 : #ifdef CONFIG_HSA_AMD
219 : extern int sched_policy;
220 : extern bool debug_evictions;
221 : extern bool no_system_mem_limit;
222 : #else
223 : static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
224 : static const bool __maybe_unused debug_evictions; /* = false */
225 : static const bool __maybe_unused no_system_mem_limit;
226 : #endif
227 : #ifdef CONFIG_HSA_AMD_P2P
228 : extern bool pcie_p2p;
229 : #endif
230 :
231 : extern int amdgpu_tmz;
232 : extern int amdgpu_reset_method;
233 :
234 : #ifdef CONFIG_DRM_AMDGPU_SI
235 : extern int amdgpu_si_support;
236 : #endif
237 : #ifdef CONFIG_DRM_AMDGPU_CIK
238 : extern int amdgpu_cik_support;
239 : #endif
240 : extern int amdgpu_num_kcq;
241 :
242 : #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
243 : extern int amdgpu_vcnfw_log;
244 :
245 : #define AMDGPU_VM_MAX_NUM_CTX 4096
246 : #define AMDGPU_SG_THRESHOLD (256*1024*1024)
247 : #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
248 : #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
249 : #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
250 : #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
251 : #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
252 : #define AMDGPUFB_CONN_LIMIT 4
253 : #define AMDGPU_BIOS_NUM_SCRATCH 16
254 :
255 : #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
256 :
257 : /* hard reset data */
258 : #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
259 :
260 : /* reset flags */
261 : #define AMDGPU_RESET_GFX (1 << 0)
262 : #define AMDGPU_RESET_COMPUTE (1 << 1)
263 : #define AMDGPU_RESET_DMA (1 << 2)
264 : #define AMDGPU_RESET_CP (1 << 3)
265 : #define AMDGPU_RESET_GRBM (1 << 4)
266 : #define AMDGPU_RESET_DMA1 (1 << 5)
267 : #define AMDGPU_RESET_RLC (1 << 6)
268 : #define AMDGPU_RESET_SEM (1 << 7)
269 : #define AMDGPU_RESET_IH (1 << 8)
270 : #define AMDGPU_RESET_VMC (1 << 9)
271 : #define AMDGPU_RESET_MC (1 << 10)
272 : #define AMDGPU_RESET_DISPLAY (1 << 11)
273 : #define AMDGPU_RESET_UVD (1 << 12)
274 : #define AMDGPU_RESET_VCE (1 << 13)
275 : #define AMDGPU_RESET_VCE1 (1 << 14)
276 :
277 : #define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
278 : #define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
279 :
280 : /* max cursor sizes (in pixels) */
281 : #define CIK_CURSOR_WIDTH 128
282 : #define CIK_CURSOR_HEIGHT 128
283 :
284 : /* smart shift bias level limits */
285 : #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
286 : #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
287 :
288 : struct amdgpu_device;
289 : struct amdgpu_irq_src;
290 : struct amdgpu_fpriv;
291 : struct amdgpu_bo_va_mapping;
292 : struct kfd_vm_fault_info;
293 : struct amdgpu_hive_info;
294 : struct amdgpu_reset_context;
295 : struct amdgpu_reset_control;
296 :
297 : enum amdgpu_cp_irq {
298 : AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
299 : AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
300 : AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
301 : AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
302 : AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
303 : AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
304 : AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
305 : AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
306 : AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
307 : AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
308 :
309 : AMDGPU_CP_IRQ_LAST
310 : };
311 :
312 : enum amdgpu_thermal_irq {
313 : AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
314 : AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
315 :
316 : AMDGPU_THERMAL_IRQ_LAST
317 : };
318 :
319 : enum amdgpu_kiq_irq {
320 : AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
321 : AMDGPU_CP_KIQ_IRQ_LAST
322 : };
323 : #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
324 : #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
325 : #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
326 : #define MAX_KIQ_REG_TRY 1000
327 :
328 : int amdgpu_device_ip_set_clockgating_state(void *dev,
329 : enum amd_ip_block_type block_type,
330 : enum amd_clockgating_state state);
331 : int amdgpu_device_ip_set_powergating_state(void *dev,
332 : enum amd_ip_block_type block_type,
333 : enum amd_powergating_state state);
334 : void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
335 : u64 *flags);
336 : int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
337 : enum amd_ip_block_type block_type);
338 : bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
339 : enum amd_ip_block_type block_type);
340 :
341 : #define AMDGPU_MAX_IP_NUM 16
342 :
343 : struct amdgpu_ip_block_status {
344 : bool valid;
345 : bool sw;
346 : bool hw;
347 : bool late_initialized;
348 : bool hang;
349 : };
350 :
351 : struct amdgpu_ip_block_version {
352 : const enum amd_ip_block_type type;
353 : const u32 major;
354 : const u32 minor;
355 : const u32 rev;
356 : const struct amd_ip_funcs *funcs;
357 : };
358 :
359 : #define HW_REV(_Major, _Minor, _Rev) \
360 : ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
361 :
362 : struct amdgpu_ip_block {
363 : struct amdgpu_ip_block_status status;
364 : const struct amdgpu_ip_block_version *version;
365 : };
366 :
367 : int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
368 : enum amd_ip_block_type type,
369 : u32 major, u32 minor);
370 :
371 : struct amdgpu_ip_block *
372 : amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
373 : enum amd_ip_block_type type);
374 :
375 : int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
376 : const struct amdgpu_ip_block_version *ip_block_version);
377 :
378 : /*
379 : * BIOS.
380 : */
381 : bool amdgpu_get_bios(struct amdgpu_device *adev);
382 : bool amdgpu_read_bios(struct amdgpu_device *adev);
383 : bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
384 : u8 *bios, u32 length_bytes);
385 : /*
386 : * Clocks
387 : */
388 :
389 : #define AMDGPU_MAX_PPLL 3
390 :
391 : struct amdgpu_clock {
392 : struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
393 : struct amdgpu_pll spll;
394 : struct amdgpu_pll mpll;
395 : /* 10 Khz units */
396 : uint32_t default_mclk;
397 : uint32_t default_sclk;
398 : uint32_t default_dispclk;
399 : uint32_t current_dispclk;
400 : uint32_t dp_extclk;
401 : uint32_t max_pixel_clock;
402 : };
403 :
404 : /* sub-allocation manager, it has to be protected by another lock.
405 : * By conception this is an helper for other part of the driver
406 : * like the indirect buffer or semaphore, which both have their
407 : * locking.
408 : *
409 : * Principe is simple, we keep a list of sub allocation in offset
410 : * order (first entry has offset == 0, last entry has the highest
411 : * offset).
412 : *
413 : * When allocating new object we first check if there is room at
414 : * the end total_size - (last_object_offset + last_object_size) >=
415 : * alloc_size. If so we allocate new object there.
416 : *
417 : * When there is not enough room at the end, we start waiting for
418 : * each sub object until we reach object_offset+object_size >=
419 : * alloc_size, this object then become the sub object we return.
420 : *
421 : * Alignment can't be bigger than page size.
422 : *
423 : * Hole are not considered for allocation to keep things simple.
424 : * Assumption is that there won't be hole (all object on same
425 : * alignment).
426 : */
427 :
428 : #define AMDGPU_SA_NUM_FENCE_LISTS 32
429 :
430 : struct amdgpu_sa_manager {
431 : wait_queue_head_t wq;
432 : struct amdgpu_bo *bo;
433 : struct list_head *hole;
434 : struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
435 : struct list_head olist;
436 : unsigned size;
437 : uint64_t gpu_addr;
438 : void *cpu_ptr;
439 : uint32_t domain;
440 : uint32_t align;
441 : };
442 :
443 : /* sub-allocation buffer */
444 : struct amdgpu_sa_bo {
445 : struct list_head olist;
446 : struct list_head flist;
447 : struct amdgpu_sa_manager *manager;
448 : unsigned soffset;
449 : unsigned eoffset;
450 : struct dma_fence *fence;
451 : };
452 :
453 : int amdgpu_fence_slab_init(void);
454 : void amdgpu_fence_slab_fini(void);
455 :
456 : /*
457 : * IRQS.
458 : */
459 :
460 : struct amdgpu_flip_work {
461 : struct delayed_work flip_work;
462 : struct work_struct unpin_work;
463 : struct amdgpu_device *adev;
464 : int crtc_id;
465 : u32 target_vblank;
466 : uint64_t base;
467 : struct drm_pending_vblank_event *event;
468 : struct amdgpu_bo *old_abo;
469 : unsigned shared_count;
470 : struct dma_fence **shared;
471 : struct dma_fence_cb cb;
472 : bool async;
473 : };
474 :
475 :
476 : /*
477 : * file private structure
478 : */
479 :
480 : struct amdgpu_fpriv {
481 : struct amdgpu_vm vm;
482 : struct amdgpu_bo_va *prt_va;
483 : struct amdgpu_bo_va *csa_va;
484 : struct mutex bo_list_lock;
485 : struct idr bo_list_handles;
486 : struct amdgpu_ctx_mgr ctx_mgr;
487 : };
488 :
489 : int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
490 :
491 : /*
492 : * Writeback
493 : */
494 : #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
495 :
496 : struct amdgpu_wb {
497 : struct amdgpu_bo *wb_obj;
498 : volatile uint32_t *wb;
499 : uint64_t gpu_addr;
500 : u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
501 : unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
502 : };
503 :
504 : int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
505 : void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
506 :
507 : /*
508 : * Benchmarking
509 : */
510 : int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
511 :
512 : /*
513 : * ASIC specific register table accessible by UMD
514 : */
515 : struct amdgpu_allowed_register_entry {
516 : uint32_t reg_offset;
517 : bool grbm_indexed;
518 : };
519 :
520 : enum amd_reset_method {
521 : AMD_RESET_METHOD_NONE = -1,
522 : AMD_RESET_METHOD_LEGACY = 0,
523 : AMD_RESET_METHOD_MODE0,
524 : AMD_RESET_METHOD_MODE1,
525 : AMD_RESET_METHOD_MODE2,
526 : AMD_RESET_METHOD_BACO,
527 : AMD_RESET_METHOD_PCI,
528 : };
529 :
530 : struct amdgpu_video_codec_info {
531 : u32 codec_type;
532 : u32 max_width;
533 : u32 max_height;
534 : u32 max_pixels_per_frame;
535 : u32 max_level;
536 : };
537 :
538 : #define codec_info_build(type, width, height, level) \
539 : .codec_type = type,\
540 : .max_width = width,\
541 : .max_height = height,\
542 : .max_pixels_per_frame = height * width,\
543 : .max_level = level,
544 :
545 : struct amdgpu_video_codecs {
546 : const u32 codec_count;
547 : const struct amdgpu_video_codec_info *codec_array;
548 : };
549 :
550 : /*
551 : * ASIC specific functions.
552 : */
553 : struct amdgpu_asic_funcs {
554 : bool (*read_disabled_bios)(struct amdgpu_device *adev);
555 : bool (*read_bios_from_rom)(struct amdgpu_device *adev,
556 : u8 *bios, u32 length_bytes);
557 : int (*read_register)(struct amdgpu_device *adev, u32 se_num,
558 : u32 sh_num, u32 reg_offset, u32 *value);
559 : void (*set_vga_state)(struct amdgpu_device *adev, bool state);
560 : int (*reset)(struct amdgpu_device *adev);
561 : enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
562 : /* get the reference clock */
563 : u32 (*get_xclk)(struct amdgpu_device *adev);
564 : /* MM block clocks */
565 : int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
566 : int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
567 : /* static power management */
568 : int (*get_pcie_lanes)(struct amdgpu_device *adev);
569 : void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
570 : /* get config memsize register */
571 : u32 (*get_config_memsize)(struct amdgpu_device *adev);
572 : /* flush hdp write queue */
573 : void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
574 : /* invalidate hdp read cache */
575 : void (*invalidate_hdp)(struct amdgpu_device *adev,
576 : struct amdgpu_ring *ring);
577 : /* check if the asic needs a full reset of if soft reset will work */
578 : bool (*need_full_reset)(struct amdgpu_device *adev);
579 : /* initialize doorbell layout for specific asic*/
580 : void (*init_doorbell_index)(struct amdgpu_device *adev);
581 : /* PCIe bandwidth usage */
582 : void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
583 : uint64_t *count1);
584 : /* do we need to reset the asic at init time (e.g., kexec) */
585 : bool (*need_reset_on_init)(struct amdgpu_device *adev);
586 : /* PCIe replay counter */
587 : uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
588 : /* device supports BACO */
589 : bool (*supports_baco)(struct amdgpu_device *adev);
590 : /* pre asic_init quirks */
591 : void (*pre_asic_init)(struct amdgpu_device *adev);
592 : /* enter/exit umd stable pstate */
593 : int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
594 : /* query video codecs */
595 : int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
596 : const struct amdgpu_video_codecs **codecs);
597 : };
598 :
599 : /*
600 : * IOCTL.
601 : */
602 : int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
603 : struct drm_file *filp);
604 :
605 : int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
606 : int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
607 : struct drm_file *filp);
608 : int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
609 : int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
610 : struct drm_file *filp);
611 :
612 : /* VRAM scratch page for HDP bug, default vram page */
613 : struct amdgpu_vram_scratch {
614 : struct amdgpu_bo *robj;
615 : volatile uint32_t *ptr;
616 : u64 gpu_addr;
617 : };
618 :
619 : /*
620 : * CGS
621 : */
622 : struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
623 : void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
624 :
625 : /*
626 : * Core structure, functions and helpers.
627 : */
628 : typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
629 : typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
630 :
631 : typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
632 : typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
633 :
634 : typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
635 : typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
636 :
637 : struct amdgpu_mmio_remap {
638 : u32 reg_offset;
639 : resource_size_t bus_addr;
640 : };
641 :
642 : /* Define the HW IP blocks will be used in driver , add more if necessary */
643 : enum amd_hw_ip_block_type {
644 : GC_HWIP = 1,
645 : HDP_HWIP,
646 : SDMA0_HWIP,
647 : SDMA1_HWIP,
648 : SDMA2_HWIP,
649 : SDMA3_HWIP,
650 : SDMA4_HWIP,
651 : SDMA5_HWIP,
652 : SDMA6_HWIP,
653 : SDMA7_HWIP,
654 : LSDMA_HWIP,
655 : MMHUB_HWIP,
656 : ATHUB_HWIP,
657 : NBIO_HWIP,
658 : MP0_HWIP,
659 : MP1_HWIP,
660 : UVD_HWIP,
661 : VCN_HWIP = UVD_HWIP,
662 : JPEG_HWIP = VCN_HWIP,
663 : VCN1_HWIP,
664 : VCE_HWIP,
665 : DF_HWIP,
666 : DCE_HWIP,
667 : OSSSYS_HWIP,
668 : SMUIO_HWIP,
669 : PWR_HWIP,
670 : NBIF_HWIP,
671 : THM_HWIP,
672 : CLK_HWIP,
673 : UMC_HWIP,
674 : RSMU_HWIP,
675 : XGMI_HWIP,
676 : DCI_HWIP,
677 : PCIE_HWIP,
678 : MAX_HWIP
679 : };
680 :
681 : #define HWIP_MAX_INSTANCE 11
682 :
683 : #define HW_ID_MAX 300
684 : #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
685 : #define IP_VERSION_MAJ(ver) ((ver) >> 16)
686 : #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
687 : #define IP_VERSION_REV(ver) ((ver) & 0xFF)
688 :
689 : struct amd_powerplay {
690 : void *pp_handle;
691 : const struct amd_pm_funcs *pp_funcs;
692 : };
693 :
694 : struct ip_discovery_top;
695 :
696 : /* polaris10 kickers */
697 : #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
698 : ((rid == 0xE3) || \
699 : (rid == 0xE4) || \
700 : (rid == 0xE5) || \
701 : (rid == 0xE7) || \
702 : (rid == 0xEF))) || \
703 : ((did == 0x6FDF) && \
704 : ((rid == 0xE7) || \
705 : (rid == 0xEF) || \
706 : (rid == 0xFF))))
707 :
708 : #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
709 : ((rid == 0xE1) || \
710 : (rid == 0xF7)))
711 :
712 : /* polaris11 kickers */
713 : #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
714 : ((rid == 0xE0) || \
715 : (rid == 0xE5))) || \
716 : ((did == 0x67FF) && \
717 : ((rid == 0xCF) || \
718 : (rid == 0xEF) || \
719 : (rid == 0xFF))))
720 :
721 : #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
722 : ((rid == 0xE2)))
723 :
724 : /* polaris12 kickers */
725 : #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
726 : ((rid == 0xC0) || \
727 : (rid == 0xC1) || \
728 : (rid == 0xC3) || \
729 : (rid == 0xC7))) || \
730 : ((did == 0x6981) && \
731 : ((rid == 0x00) || \
732 : (rid == 0x01) || \
733 : (rid == 0x10))))
734 :
735 : struct amdgpu_mqd_prop {
736 : uint64_t mqd_gpu_addr;
737 : uint64_t hqd_base_gpu_addr;
738 : uint64_t rptr_gpu_addr;
739 : uint64_t wptr_gpu_addr;
740 : uint32_t queue_size;
741 : bool use_doorbell;
742 : uint32_t doorbell_index;
743 : uint64_t eop_gpu_addr;
744 : uint32_t hqd_pipe_priority;
745 : uint32_t hqd_queue_priority;
746 : bool hqd_active;
747 : };
748 :
749 : struct amdgpu_mqd {
750 : unsigned mqd_size;
751 : int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
752 : struct amdgpu_mqd_prop *p);
753 : };
754 :
755 : #define AMDGPU_RESET_MAGIC_NUM 64
756 : #define AMDGPU_MAX_DF_PERFMONS 4
757 : #define AMDGPU_PRODUCT_NAME_LEN 64
758 : struct amdgpu_reset_domain;
759 :
760 : struct amdgpu_device {
761 : struct device *dev;
762 : struct pci_dev *pdev;
763 : struct drm_device ddev;
764 :
765 : #ifdef CONFIG_DRM_AMD_ACP
766 : struct amdgpu_acp acp;
767 : #endif
768 : struct amdgpu_hive_info *hive;
769 : /* ASIC */
770 : enum amd_asic_type asic_type;
771 : uint32_t family;
772 : uint32_t rev_id;
773 : uint32_t external_rev_id;
774 : unsigned long flags;
775 : unsigned long apu_flags;
776 : int usec_timeout;
777 : const struct amdgpu_asic_funcs *asic_funcs;
778 : bool shutdown;
779 : bool need_swiotlb;
780 : bool accel_working;
781 : struct notifier_block acpi_nb;
782 : struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
783 : struct debugfs_blob_wrapper debugfs_vbios_blob;
784 : struct debugfs_blob_wrapper debugfs_discovery_blob;
785 : struct mutex srbm_mutex;
786 : /* GRBM index mutex. Protects concurrent access to GRBM index */
787 : struct mutex grbm_idx_mutex;
788 : struct dev_pm_domain vga_pm_domain;
789 : bool have_disp_power_ref;
790 : bool have_atomics_support;
791 :
792 : /* BIOS */
793 : bool is_atom_fw;
794 : uint8_t *bios;
795 : uint32_t bios_size;
796 : uint32_t bios_scratch_reg_offset;
797 : uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
798 :
799 : /* Register/doorbell mmio */
800 : resource_size_t rmmio_base;
801 : resource_size_t rmmio_size;
802 : void __iomem *rmmio;
803 : /* protects concurrent MM_INDEX/DATA based register access */
804 : spinlock_t mmio_idx_lock;
805 : struct amdgpu_mmio_remap rmmio_remap;
806 : /* protects concurrent SMC based register access */
807 : spinlock_t smc_idx_lock;
808 : amdgpu_rreg_t smc_rreg;
809 : amdgpu_wreg_t smc_wreg;
810 : /* protects concurrent PCIE register access */
811 : spinlock_t pcie_idx_lock;
812 : amdgpu_rreg_t pcie_rreg;
813 : amdgpu_wreg_t pcie_wreg;
814 : amdgpu_rreg_t pciep_rreg;
815 : amdgpu_wreg_t pciep_wreg;
816 : amdgpu_rreg64_t pcie_rreg64;
817 : amdgpu_wreg64_t pcie_wreg64;
818 : /* protects concurrent UVD register access */
819 : spinlock_t uvd_ctx_idx_lock;
820 : amdgpu_rreg_t uvd_ctx_rreg;
821 : amdgpu_wreg_t uvd_ctx_wreg;
822 : /* protects concurrent DIDT register access */
823 : spinlock_t didt_idx_lock;
824 : amdgpu_rreg_t didt_rreg;
825 : amdgpu_wreg_t didt_wreg;
826 : /* protects concurrent gc_cac register access */
827 : spinlock_t gc_cac_idx_lock;
828 : amdgpu_rreg_t gc_cac_rreg;
829 : amdgpu_wreg_t gc_cac_wreg;
830 : /* protects concurrent se_cac register access */
831 : spinlock_t se_cac_idx_lock;
832 : amdgpu_rreg_t se_cac_rreg;
833 : amdgpu_wreg_t se_cac_wreg;
834 : /* protects concurrent ENDPOINT (audio) register access */
835 : spinlock_t audio_endpt_idx_lock;
836 : amdgpu_block_rreg_t audio_endpt_rreg;
837 : amdgpu_block_wreg_t audio_endpt_wreg;
838 : struct amdgpu_doorbell doorbell;
839 :
840 : /* clock/pll info */
841 : struct amdgpu_clock clock;
842 :
843 : /* MC */
844 : struct amdgpu_gmc gmc;
845 : struct amdgpu_gart gart;
846 : dma_addr_t dummy_page_addr;
847 : struct amdgpu_vm_manager vm_manager;
848 : struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
849 : unsigned num_vmhubs;
850 :
851 : /* memory management */
852 : struct amdgpu_mman mman;
853 : struct amdgpu_vram_scratch vram_scratch;
854 : struct amdgpu_wb wb;
855 : atomic64_t num_bytes_moved;
856 : atomic64_t num_evictions;
857 : atomic64_t num_vram_cpu_page_faults;
858 : atomic_t gpu_reset_counter;
859 : atomic_t vram_lost_counter;
860 :
861 : /* data for buffer migration throttling */
862 : struct {
863 : spinlock_t lock;
864 : s64 last_update_us;
865 : s64 accum_us; /* accumulated microseconds */
866 : s64 accum_us_vis; /* for visible VRAM */
867 : u32 log2_max_MBps;
868 : } mm_stats;
869 :
870 : /* display */
871 : bool enable_virtual_display;
872 : struct amdgpu_vkms_output *amdgpu_vkms_output;
873 : struct amdgpu_mode_info mode_info;
874 : /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
875 : struct work_struct hotplug_work;
876 : struct amdgpu_irq_src crtc_irq;
877 : struct amdgpu_irq_src vline0_irq;
878 : struct amdgpu_irq_src vupdate_irq;
879 : struct amdgpu_irq_src pageflip_irq;
880 : struct amdgpu_irq_src hpd_irq;
881 : struct amdgpu_irq_src dmub_trace_irq;
882 : struct amdgpu_irq_src dmub_outbox_irq;
883 :
884 : /* rings */
885 : u64 fence_context;
886 : unsigned num_rings;
887 : struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
888 : bool ib_pool_ready;
889 : struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
890 : struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
891 :
892 : /* interrupts */
893 : struct amdgpu_irq irq;
894 :
895 : /* powerplay */
896 : struct amd_powerplay powerplay;
897 : struct amdgpu_pm pm;
898 : u64 cg_flags;
899 : u32 pg_flags;
900 :
901 : /* nbio */
902 : struct amdgpu_nbio nbio;
903 :
904 : /* hdp */
905 : struct amdgpu_hdp hdp;
906 :
907 : /* smuio */
908 : struct amdgpu_smuio smuio;
909 :
910 : /* mmhub */
911 : struct amdgpu_mmhub mmhub;
912 :
913 : /* gfxhub */
914 : struct amdgpu_gfxhub gfxhub;
915 :
916 : /* gfx */
917 : struct amdgpu_gfx gfx;
918 :
919 : /* sdma */
920 : struct amdgpu_sdma sdma;
921 :
922 : /* lsdma */
923 : struct amdgpu_lsdma lsdma;
924 :
925 : /* uvd */
926 : struct amdgpu_uvd uvd;
927 :
928 : /* vce */
929 : struct amdgpu_vce vce;
930 :
931 : /* vcn */
932 : struct amdgpu_vcn vcn;
933 :
934 : /* jpeg */
935 : struct amdgpu_jpeg jpeg;
936 :
937 : /* firmwares */
938 : struct amdgpu_firmware firmware;
939 :
940 : /* PSP */
941 : struct psp_context psp;
942 :
943 : /* GDS */
944 : struct amdgpu_gds gds;
945 :
946 : /* KFD */
947 : struct amdgpu_kfd_dev kfd;
948 :
949 : /* UMC */
950 : struct amdgpu_umc umc;
951 :
952 : /* display related functionality */
953 : struct amdgpu_display_manager dm;
954 :
955 : /* mes */
956 : bool enable_mes;
957 : bool enable_mes_kiq;
958 : struct amdgpu_mes mes;
959 : struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
960 :
961 : /* df */
962 : struct amdgpu_df df;
963 :
964 : /* MCA */
965 : struct amdgpu_mca mca;
966 :
967 : struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
968 : uint32_t harvest_ip_mask;
969 : int num_ip_blocks;
970 : struct mutex mn_lock;
971 : DECLARE_HASHTABLE(mn_hash, 7);
972 :
973 : /* tracking pinned memory */
974 : atomic64_t vram_pin_size;
975 : atomic64_t visible_pin_size;
976 : atomic64_t gart_pin_size;
977 :
978 : /* soc15 register offset based on ip, instance and segment */
979 : uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
980 :
981 : /* delayed work_func for deferring clockgating during resume */
982 : struct delayed_work delayed_init_work;
983 :
984 : struct amdgpu_virt virt;
985 :
986 : /* link all shadow bo */
987 : struct list_head shadow_list;
988 : struct mutex shadow_list_lock;
989 :
990 : /* record hw reset is performed */
991 : bool has_hw_reset;
992 : u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
993 :
994 : /* s3/s4 mask */
995 : bool in_suspend;
996 : bool in_s3;
997 : bool in_s4;
998 : bool in_s0ix;
999 :
1000 : enum pp_mp1_state mp1_state;
1001 : struct amdgpu_doorbell_index doorbell_index;
1002 :
1003 : struct mutex notifier_lock;
1004 :
1005 : int asic_reset_res;
1006 : struct work_struct xgmi_reset_work;
1007 : struct list_head reset_list;
1008 :
1009 : long gfx_timeout;
1010 : long sdma_timeout;
1011 : long video_timeout;
1012 : long compute_timeout;
1013 :
1014 : uint64_t unique_id;
1015 : uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1016 :
1017 : /* enable runtime pm on the device */
1018 : bool in_runpm;
1019 : bool has_pr3;
1020 :
1021 : bool pm_sysfs_en;
1022 : bool ucode_sysfs_en;
1023 : bool psp_sysfs_en;
1024 :
1025 : /* Chip product information */
1026 : char product_number[20];
1027 : char product_name[AMDGPU_PRODUCT_NAME_LEN];
1028 : char serial[20];
1029 :
1030 : atomic_t throttling_logging_enabled;
1031 : struct ratelimit_state throttling_logging_rs;
1032 : uint32_t ras_hw_enabled;
1033 : uint32_t ras_enabled;
1034 :
1035 : bool no_hw_access;
1036 : struct pci_saved_state *pci_state;
1037 : pci_channel_state_t pci_channel_state;
1038 :
1039 : struct amdgpu_reset_control *reset_cntl;
1040 : uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1041 :
1042 : bool ram_is_direct_mapped;
1043 :
1044 : struct list_head ras_list;
1045 :
1046 : struct ip_discovery_top *ip_top;
1047 :
1048 : struct amdgpu_reset_domain *reset_domain;
1049 :
1050 : struct mutex benchmark_mutex;
1051 :
1052 : /* reset dump register */
1053 : uint32_t *reset_dump_reg_list;
1054 : uint32_t *reset_dump_reg_value;
1055 : int num_regs;
1056 : #ifdef CONFIG_DEV_COREDUMP
1057 : struct amdgpu_task_info reset_task_info;
1058 : bool reset_vram_lost;
1059 : struct timespec64 reset_time;
1060 : #endif
1061 :
1062 : bool scpm_enabled;
1063 : uint32_t scpm_status;
1064 :
1065 : struct work_struct reset_work;
1066 :
1067 : uint32_t amdgpu_reset_level_mask;
1068 : bool job_hang;
1069 : };
1070 :
1071 : static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1072 : {
1073 0 : return container_of(ddev, struct amdgpu_device, ddev);
1074 : }
1075 :
1076 : static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1077 : {
1078 0 : return &adev->ddev;
1079 : }
1080 :
1081 : static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1082 : {
1083 0 : return container_of(bdev, struct amdgpu_device, mman.bdev);
1084 : }
1085 :
1086 : int amdgpu_device_init(struct amdgpu_device *adev,
1087 : uint32_t flags);
1088 : void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1089 : void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1090 :
1091 : int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1092 :
1093 : void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1094 : void *buf, size_t size, bool write);
1095 : size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1096 : void *buf, size_t size, bool write);
1097 :
1098 : void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1099 : void *buf, size_t size, bool write);
1100 : uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1101 : uint32_t reg, uint32_t acc_flags);
1102 : void amdgpu_device_wreg(struct amdgpu_device *adev,
1103 : uint32_t reg, uint32_t v,
1104 : uint32_t acc_flags);
1105 : void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1106 : uint32_t reg, uint32_t v);
1107 : void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1108 : uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1109 :
1110 : u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1111 : u32 pcie_index, u32 pcie_data,
1112 : u32 reg_addr);
1113 : u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1114 : u32 pcie_index, u32 pcie_data,
1115 : u32 reg_addr);
1116 : void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1117 : u32 pcie_index, u32 pcie_data,
1118 : u32 reg_addr, u32 reg_data);
1119 : void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1120 : u32 pcie_index, u32 pcie_data,
1121 : u32 reg_addr, u64 reg_data);
1122 :
1123 : bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1124 : bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1125 :
1126 : int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1127 : struct amdgpu_reset_context *reset_context);
1128 :
1129 : int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1130 : struct amdgpu_reset_context *reset_context);
1131 :
1132 : int emu_soc_asic_init(struct amdgpu_device *adev);
1133 :
1134 : /*
1135 : * Registers read & write functions.
1136 : */
1137 : #define AMDGPU_REGS_NO_KIQ (1<<1)
1138 : #define AMDGPU_REGS_RLC (1<<2)
1139 :
1140 : #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1141 : #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1142 :
1143 : #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1144 : #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1145 :
1146 : #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1147 : #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1148 :
1149 : #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1150 : #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1151 : #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1152 : #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1153 : #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1154 : #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1155 : #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1156 : #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1157 : #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1158 : #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1159 : #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1160 : #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1161 : #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1162 : #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1163 : #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1164 : #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1165 : #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1166 : #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1167 : #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1168 : #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1169 : #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1170 : #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1171 : #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1172 : #define WREG32_P(reg, val, mask) \
1173 : do { \
1174 : uint32_t tmp_ = RREG32(reg); \
1175 : tmp_ &= (mask); \
1176 : tmp_ |= ((val) & ~(mask)); \
1177 : WREG32(reg, tmp_); \
1178 : } while (0)
1179 : #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1180 : #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1181 : #define WREG32_PLL_P(reg, val, mask) \
1182 : do { \
1183 : uint32_t tmp_ = RREG32_PLL(reg); \
1184 : tmp_ &= (mask); \
1185 : tmp_ |= ((val) & ~(mask)); \
1186 : WREG32_PLL(reg, tmp_); \
1187 : } while (0)
1188 :
1189 : #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1190 : do { \
1191 : u32 tmp = RREG32_SMC(_Reg); \
1192 : tmp &= (_Mask); \
1193 : tmp |= ((_Val) & ~(_Mask)); \
1194 : WREG32_SMC(_Reg, tmp); \
1195 : } while (0)
1196 :
1197 : #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1198 :
1199 : #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1200 : #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1201 :
1202 : #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1203 : (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1204 : (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1205 :
1206 : #define REG_GET_FIELD(value, reg, field) \
1207 : (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1208 :
1209 : #define WREG32_FIELD(reg, field, val) \
1210 : WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1211 :
1212 : #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1213 : WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1214 :
1215 : /*
1216 : * BIOS helpers.
1217 : */
1218 : #define RBIOS8(i) (adev->bios[i])
1219 : #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1220 : #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1221 :
1222 : /*
1223 : * ASICs macro.
1224 : */
1225 : #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1226 : #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1227 : #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1228 : #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1229 : #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1230 : #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1231 : #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1232 : #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1233 : #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1234 : #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1235 : #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1236 : #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1237 : #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1238 : #define amdgpu_asic_flush_hdp(adev, r) \
1239 : ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1240 : #define amdgpu_asic_invalidate_hdp(adev, r) \
1241 : ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1242 : ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1243 : #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1244 : #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1245 : #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1246 : #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1247 : #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1248 : #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1249 : #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1250 : #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1251 : ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1252 : #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1253 :
1254 : #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1255 :
1256 : #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1257 :
1258 : /* Common functions */
1259 : bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1260 : bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1261 : int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1262 : struct amdgpu_job *job,
1263 : struct amdgpu_reset_context *reset_context);
1264 : void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1265 : int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1266 : bool amdgpu_device_need_post(struct amdgpu_device *adev);
1267 : bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1268 :
1269 : void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1270 : u64 num_vis_bytes);
1271 : int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1272 : void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1273 : const u32 *registers,
1274 : const u32 array_size);
1275 :
1276 : int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1277 : bool amdgpu_device_supports_atpx(struct drm_device *dev);
1278 : bool amdgpu_device_supports_px(struct drm_device *dev);
1279 : bool amdgpu_device_supports_boco(struct drm_device *dev);
1280 : bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1281 : bool amdgpu_device_supports_baco(struct drm_device *dev);
1282 : bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1283 : struct amdgpu_device *peer_adev);
1284 : int amdgpu_device_baco_enter(struct drm_device *dev);
1285 : int amdgpu_device_baco_exit(struct drm_device *dev);
1286 :
1287 : void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1288 : struct amdgpu_ring *ring);
1289 : void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1290 : struct amdgpu_ring *ring);
1291 :
1292 : void amdgpu_device_halt(struct amdgpu_device *adev);
1293 : u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1294 : u32 reg);
1295 : void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1296 : u32 reg, u32 v);
1297 :
1298 : /* atpx handler */
1299 : #if defined(CONFIG_VGA_SWITCHEROO)
1300 : void amdgpu_register_atpx_handler(void);
1301 : void amdgpu_unregister_atpx_handler(void);
1302 : bool amdgpu_has_atpx_dgpu_power_cntl(void);
1303 : bool amdgpu_is_atpx_hybrid(void);
1304 : bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1305 : bool amdgpu_has_atpx(void);
1306 : #else
1307 : static inline void amdgpu_register_atpx_handler(void) {}
1308 : static inline void amdgpu_unregister_atpx_handler(void) {}
1309 : static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1310 : static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1311 : static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1312 : static inline bool amdgpu_has_atpx(void) { return false; }
1313 : #endif
1314 :
1315 : #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1316 : void *amdgpu_atpx_get_dhandle(void);
1317 : #else
1318 : static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1319 : #endif
1320 :
1321 : /*
1322 : * KMS
1323 : */
1324 : extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1325 : extern const int amdgpu_max_kms_ioctl;
1326 :
1327 : int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1328 : void amdgpu_driver_unload_kms(struct drm_device *dev);
1329 : void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1330 : int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1331 : void amdgpu_driver_postclose_kms(struct drm_device *dev,
1332 : struct drm_file *file_priv);
1333 : void amdgpu_driver_release_kms(struct drm_device *dev);
1334 :
1335 : int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1336 : int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1337 : int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1338 : u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1339 : int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1340 : void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1341 : int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1342 : struct drm_file *filp);
1343 :
1344 : /*
1345 : * functions used by amdgpu_encoder.c
1346 : */
1347 : struct amdgpu_afmt_acr {
1348 : u32 clock;
1349 :
1350 : int n_32khz;
1351 : int cts_32khz;
1352 :
1353 : int n_44_1khz;
1354 : int cts_44_1khz;
1355 :
1356 : int n_48khz;
1357 : int cts_48khz;
1358 :
1359 : };
1360 :
1361 : struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1362 :
1363 : /* amdgpu_acpi.c */
1364 :
1365 : /* ATCS Device/Driver State */
1366 : #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1367 : #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1368 : #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1369 : #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1370 :
1371 : #if defined(CONFIG_ACPI)
1372 : int amdgpu_acpi_init(struct amdgpu_device *adev);
1373 : void amdgpu_acpi_fini(struct amdgpu_device *adev);
1374 : bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1375 : bool amdgpu_acpi_is_power_shift_control_supported(void);
1376 : int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1377 : u8 perf_req, bool advertise);
1378 : int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1379 : u8 dev_state, bool drv_state);
1380 : int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1381 : int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1382 :
1383 : void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1384 : void amdgpu_acpi_detect(void);
1385 : #else
1386 : static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1387 : static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1388 : static inline void amdgpu_acpi_detect(void) { }
1389 : static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1390 : static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1391 : u8 dev_state, bool drv_state) { return 0; }
1392 : static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1393 : enum amdgpu_ss ss_state) { return 0; }
1394 : #endif
1395 :
1396 : #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1397 : bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1398 : bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1399 : bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1400 : #else
1401 : static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1402 : static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1403 : static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1404 : #endif
1405 :
1406 : #if defined(CONFIG_DRM_AMD_DC)
1407 : int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1408 : #else
1409 : static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1410 : #endif
1411 :
1412 :
1413 : void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1414 : void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1415 :
1416 : pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1417 : pci_channel_state_t state);
1418 : pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1419 : pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1420 : void amdgpu_pci_resume(struct pci_dev *pdev);
1421 :
1422 : bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1423 : bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1424 :
1425 : bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1426 :
1427 : int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1428 : enum amd_clockgating_state state);
1429 : int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1430 : enum amd_powergating_state state);
1431 :
1432 : static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1433 : {
1434 0 : return amdgpu_gpu_recovery != 0 &&
1435 0 : adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1436 0 : adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1437 0 : adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1438 0 : adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1439 : }
1440 :
1441 : #include "amdgpu_object.h"
1442 :
1443 : static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1444 : {
1445 : return adev->gmc.tmz_enabled;
1446 : }
1447 :
1448 : int amdgpu_in_reset(struct amdgpu_device *adev);
1449 :
1450 : #endif
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