Line data Source code
1 : /*
2 : * Copyright 2014 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : */
22 :
23 : #include "amdgpu_amdkfd.h"
24 : #include "amd_pcie.h"
25 : #include "amd_shared.h"
26 :
27 : #include "amdgpu.h"
28 : #include "amdgpu_gfx.h"
29 : #include "amdgpu_dma_buf.h"
30 : #include <linux/module.h>
31 : #include <linux/dma-buf.h>
32 : #include "amdgpu_xgmi.h"
33 : #include <uapi/linux/kfd_ioctl.h>
34 : #include "amdgpu_ras.h"
35 : #include "amdgpu_umc.h"
36 : #include "amdgpu_reset.h"
37 :
38 : /* Total memory size in system memory and all GPU VRAM. Used to
39 : * estimate worst case amount of memory to reserve for page tables
40 : */
41 : uint64_t amdgpu_amdkfd_total_mem_size;
42 :
43 : static bool kfd_initialized;
44 :
45 1 : int amdgpu_amdkfd_init(void)
46 : {
47 : struct sysinfo si;
48 : int ret;
49 :
50 1 : si_meminfo(&si);
51 1 : amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
52 1 : amdgpu_amdkfd_total_mem_size *= si.mem_unit;
53 :
54 1 : ret = kgd2kfd_init();
55 : amdgpu_amdkfd_gpuvm_init_mem_limits();
56 1 : kfd_initialized = !ret;
57 :
58 1 : return ret;
59 : }
60 :
61 0 : void amdgpu_amdkfd_fini(void)
62 : {
63 0 : if (kfd_initialized) {
64 : kgd2kfd_exit();
65 0 : kfd_initialized = false;
66 : }
67 0 : }
68 :
69 0 : void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
70 : {
71 0 : bool vf = amdgpu_sriov_vf(adev);
72 :
73 0 : if (!kfd_initialized)
74 : return;
75 :
76 0 : adev->kfd.dev = kgd2kfd_probe(adev, vf);
77 :
78 : if (adev->kfd.dev)
79 : amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
80 : }
81 :
82 : /**
83 : * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
84 : * setup amdkfd
85 : *
86 : * @adev: amdgpu_device pointer
87 : * @aperture_base: output returning doorbell aperture base physical address
88 : * @aperture_size: output returning doorbell aperture size in bytes
89 : * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
90 : *
91 : * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
92 : * takes doorbells required for its own rings and reports the setup to amdkfd.
93 : * amdgpu reserved doorbells are at the start of the doorbell aperture.
94 : */
95 : static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
96 : phys_addr_t *aperture_base,
97 : size_t *aperture_size,
98 : size_t *start_offset)
99 : {
100 : /*
101 : * The first num_doorbells are used by amdgpu.
102 : * amdkfd takes whatever's left in the aperture.
103 : */
104 : if (adev->enable_mes) {
105 : /*
106 : * With MES enabled, we only need to initialize
107 : * the base address. The size and offset are
108 : * not initialized as AMDGPU manages the whole
109 : * doorbell space.
110 : */
111 : *aperture_base = adev->doorbell.base;
112 : *aperture_size = 0;
113 : *start_offset = 0;
114 : } else if (adev->doorbell.size > adev->doorbell.num_doorbells *
115 : sizeof(u32)) {
116 : *aperture_base = adev->doorbell.base;
117 : *aperture_size = adev->doorbell.size;
118 : *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
119 : } else {
120 : *aperture_base = 0;
121 : *aperture_size = 0;
122 : *start_offset = 0;
123 : }
124 : }
125 :
126 :
127 0 : static void amdgpu_amdkfd_reset_work(struct work_struct *work)
128 : {
129 0 : struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
130 : kfd.reset_work);
131 :
132 : struct amdgpu_reset_context reset_context;
133 0 : memset(&reset_context, 0, sizeof(reset_context));
134 :
135 0 : reset_context.method = AMD_RESET_METHOD_NONE;
136 0 : reset_context.reset_req_dev = adev;
137 0 : clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
138 0 : clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
139 :
140 0 : amdgpu_device_gpu_recover(adev, NULL, &reset_context);
141 0 : }
142 :
143 0 : void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
144 : {
145 : int i;
146 : int last_valid_bit;
147 :
148 0 : if (adev->kfd.dev) {
149 0 : struct kgd2kfd_shared_resources gpu_resources = {
150 : .compute_vmid_bitmap =
151 0 : ((1 << AMDGPU_NUM_VMID) - 1) -
152 0 : ((1 << adev->vm_manager.first_kfd_vmid) - 1),
153 0 : .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
154 0 : .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
155 0 : .gpuvm_size = min(adev->vm_manager.max_pfn
156 : << AMDGPU_GPU_PAGE_SHIFT,
157 : AMDGPU_GMC_HOLE_START),
158 0 : .drm_render_minor = adev_to_drm(adev)->render->index,
159 0 : .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
160 0 : .enable_mes = adev->enable_mes,
161 : };
162 :
163 : /* this is going to have a few of the MSBs set that we need to
164 : * clear
165 : */
166 0 : bitmap_complement(gpu_resources.cp_queue_bitmap,
167 0 : adev->gfx.mec.queue_bitmap,
168 : KGD_MAX_QUEUES);
169 :
170 : /* According to linux/bitmap.h we shouldn't use bitmap_clear if
171 : * nbits is not compile time constant
172 : */
173 0 : last_valid_bit = 1 /* only first MEC can have compute queues */
174 0 : * adev->gfx.mec.num_pipe_per_mec
175 0 : * adev->gfx.mec.num_queue_per_pipe;
176 0 : for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
177 0 : clear_bit(i, gpu_resources.cp_queue_bitmap);
178 :
179 0 : amdgpu_doorbell_get_kfd_info(adev,
180 : &gpu_resources.doorbell_physical_address,
181 : &gpu_resources.doorbell_aperture_size,
182 : &gpu_resources.doorbell_start_offset);
183 :
184 : /* Since SOC15, BIF starts to statically use the
185 : * lower 12 bits of doorbell addresses for routing
186 : * based on settings in registers like
187 : * SDMA0_DOORBELL_RANGE etc..
188 : * In order to route a doorbell to CP engine, the lower
189 : * 12 bits of its address has to be outside the range
190 : * set for SDMA, VCN, and IH blocks.
191 : */
192 : if (adev->asic_type >= CHIP_VEGA10) {
193 : gpu_resources.non_cp_doorbells_start =
194 : adev->doorbell_index.first_non_cp;
195 : gpu_resources.non_cp_doorbells_end =
196 : adev->doorbell_index.last_non_cp;
197 : }
198 :
199 0 : adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
200 : adev_to_drm(adev), &gpu_resources);
201 :
202 0 : INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
203 : }
204 0 : }
205 :
206 0 : void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
207 : {
208 0 : if (adev->kfd.dev) {
209 0 : kgd2kfd_device_exit(adev->kfd.dev);
210 0 : adev->kfd.dev = NULL;
211 : }
212 0 : }
213 :
214 0 : void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
215 : const void *ih_ring_entry)
216 : {
217 : if (adev->kfd.dev)
218 : kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
219 0 : }
220 :
221 0 : void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
222 : {
223 0 : if (adev->kfd.dev)
224 : kgd2kfd_suspend(adev->kfd.dev, run_pm);
225 0 : }
226 :
227 0 : int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
228 : {
229 0 : int r = 0;
230 :
231 : if (adev->kfd.dev)
232 : r = kgd2kfd_resume_iommu(adev->kfd.dev);
233 :
234 0 : return r;
235 : }
236 :
237 0 : int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
238 : {
239 0 : int r = 0;
240 :
241 0 : if (adev->kfd.dev)
242 : r = kgd2kfd_resume(adev->kfd.dev, run_pm);
243 :
244 0 : return r;
245 : }
246 :
247 0 : int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
248 : {
249 0 : int r = 0;
250 :
251 : if (adev->kfd.dev)
252 : r = kgd2kfd_pre_reset(adev->kfd.dev);
253 :
254 0 : return r;
255 : }
256 :
257 0 : int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
258 : {
259 0 : int r = 0;
260 :
261 : if (adev->kfd.dev)
262 : r = kgd2kfd_post_reset(adev->kfd.dev);
263 :
264 0 : return r;
265 : }
266 :
267 0 : void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
268 : {
269 0 : if (amdgpu_device_should_recover_gpu(adev))
270 0 : amdgpu_reset_domain_schedule(adev->reset_domain,
271 : &adev->kfd.reset_work);
272 0 : }
273 :
274 0 : int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
275 : void **mem_obj, uint64_t *gpu_addr,
276 : void **cpu_ptr, bool cp_mqd_gfx9)
277 : {
278 0 : struct amdgpu_bo *bo = NULL;
279 : struct amdgpu_bo_param bp;
280 : int r;
281 0 : void *cpu_ptr_tmp = NULL;
282 :
283 0 : memset(&bp, 0, sizeof(bp));
284 0 : bp.size = size;
285 0 : bp.byte_align = PAGE_SIZE;
286 0 : bp.domain = AMDGPU_GEM_DOMAIN_GTT;
287 0 : bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
288 0 : bp.type = ttm_bo_type_kernel;
289 0 : bp.resv = NULL;
290 0 : bp.bo_ptr_size = sizeof(struct amdgpu_bo);
291 :
292 0 : if (cp_mqd_gfx9)
293 0 : bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
294 :
295 0 : r = amdgpu_bo_create(adev, &bp, &bo);
296 0 : if (r) {
297 0 : dev_err(adev->dev,
298 : "failed to allocate BO for amdkfd (%d)\n", r);
299 0 : return r;
300 : }
301 :
302 : /* map the buffer */
303 0 : r = amdgpu_bo_reserve(bo, true);
304 0 : if (r) {
305 0 : dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
306 0 : goto allocate_mem_reserve_bo_failed;
307 : }
308 :
309 0 : r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
310 0 : if (r) {
311 0 : dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
312 0 : goto allocate_mem_pin_bo_failed;
313 : }
314 :
315 0 : r = amdgpu_ttm_alloc_gart(&bo->tbo);
316 0 : if (r) {
317 0 : dev_err(adev->dev, "%p bind failed\n", bo);
318 0 : goto allocate_mem_kmap_bo_failed;
319 : }
320 :
321 0 : r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
322 0 : if (r) {
323 0 : dev_err(adev->dev,
324 : "(%d) failed to map bo to kernel for amdkfd\n", r);
325 0 : goto allocate_mem_kmap_bo_failed;
326 : }
327 :
328 0 : *mem_obj = bo;
329 0 : *gpu_addr = amdgpu_bo_gpu_offset(bo);
330 0 : *cpu_ptr = cpu_ptr_tmp;
331 :
332 0 : amdgpu_bo_unreserve(bo);
333 :
334 0 : return 0;
335 :
336 : allocate_mem_kmap_bo_failed:
337 0 : amdgpu_bo_unpin(bo);
338 : allocate_mem_pin_bo_failed:
339 0 : amdgpu_bo_unreserve(bo);
340 : allocate_mem_reserve_bo_failed:
341 0 : amdgpu_bo_unref(&bo);
342 :
343 0 : return r;
344 : }
345 :
346 0 : void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj)
347 : {
348 0 : struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
349 :
350 0 : amdgpu_bo_reserve(bo, true);
351 0 : amdgpu_bo_kunmap(bo);
352 0 : amdgpu_bo_unpin(bo);
353 0 : amdgpu_bo_unreserve(bo);
354 0 : amdgpu_bo_unref(&(bo));
355 0 : }
356 :
357 0 : int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
358 : void **mem_obj)
359 : {
360 0 : struct amdgpu_bo *bo = NULL;
361 : struct amdgpu_bo_user *ubo;
362 : struct amdgpu_bo_param bp;
363 : int r;
364 :
365 0 : memset(&bp, 0, sizeof(bp));
366 0 : bp.size = size;
367 0 : bp.byte_align = 1;
368 0 : bp.domain = AMDGPU_GEM_DOMAIN_GWS;
369 0 : bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
370 0 : bp.type = ttm_bo_type_device;
371 0 : bp.resv = NULL;
372 0 : bp.bo_ptr_size = sizeof(struct amdgpu_bo);
373 :
374 0 : r = amdgpu_bo_create_user(adev, &bp, &ubo);
375 0 : if (r) {
376 0 : dev_err(adev->dev,
377 : "failed to allocate gws BO for amdkfd (%d)\n", r);
378 0 : return r;
379 : }
380 :
381 0 : bo = &ubo->bo;
382 0 : *mem_obj = bo;
383 0 : return 0;
384 : }
385 :
386 0 : void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
387 : {
388 0 : struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
389 :
390 0 : amdgpu_bo_unref(&bo);
391 0 : }
392 :
393 0 : uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
394 : enum kgd_engine_type type)
395 : {
396 0 : switch (type) {
397 : case KGD_ENGINE_PFP:
398 0 : return adev->gfx.pfp_fw_version;
399 :
400 : case KGD_ENGINE_ME:
401 0 : return adev->gfx.me_fw_version;
402 :
403 : case KGD_ENGINE_CE:
404 0 : return adev->gfx.ce_fw_version;
405 :
406 : case KGD_ENGINE_MEC1:
407 0 : return adev->gfx.mec_fw_version;
408 :
409 : case KGD_ENGINE_MEC2:
410 0 : return adev->gfx.mec2_fw_version;
411 :
412 : case KGD_ENGINE_RLC:
413 0 : return adev->gfx.rlc_fw_version;
414 :
415 : case KGD_ENGINE_SDMA1:
416 0 : return adev->sdma.instance[0].fw_version;
417 :
418 : case KGD_ENGINE_SDMA2:
419 0 : return adev->sdma.instance[1].fw_version;
420 :
421 : default:
422 : return 0;
423 : }
424 :
425 : return 0;
426 : }
427 :
428 0 : void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
429 : struct kfd_local_mem_info *mem_info)
430 : {
431 0 : memset(mem_info, 0, sizeof(*mem_info));
432 :
433 0 : mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
434 0 : mem_info->local_mem_size_private = adev->gmc.real_vram_size -
435 0 : adev->gmc.visible_vram_size;
436 :
437 0 : mem_info->vram_width = adev->gmc.vram_width;
438 :
439 : pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
440 : &adev->gmc.aper_base,
441 : mem_info->local_mem_size_public,
442 : mem_info->local_mem_size_private);
443 :
444 0 : if (amdgpu_sriov_vf(adev))
445 0 : mem_info->mem_clk_max = adev->clock.default_mclk / 100;
446 0 : else if (adev->pm.dpm_enabled) {
447 0 : if (amdgpu_emu_mode == 1)
448 0 : mem_info->mem_clk_max = 0;
449 : else
450 0 : mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
451 : } else
452 0 : mem_info->mem_clk_max = 100;
453 0 : }
454 :
455 0 : uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
456 : {
457 0 : if (adev->gfx.funcs->get_gpu_clock_counter)
458 0 : return adev->gfx.funcs->get_gpu_clock_counter(adev);
459 : return 0;
460 : }
461 :
462 0 : uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
463 : {
464 : /* the sclk is in quantas of 10kHz */
465 0 : if (amdgpu_sriov_vf(adev))
466 0 : return adev->clock.default_sclk / 100;
467 0 : else if (adev->pm.dpm_enabled)
468 0 : return amdgpu_dpm_get_sclk(adev, false) / 100;
469 : else
470 : return 100;
471 : }
472 :
473 0 : void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info)
474 : {
475 0 : struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
476 :
477 0 : memset(cu_info, 0, sizeof(*cu_info));
478 : if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
479 : return;
480 :
481 0 : cu_info->cu_active_number = acu_info.number;
482 0 : cu_info->cu_ao_mask = acu_info.ao_cu_mask;
483 0 : memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
484 : sizeof(acu_info.bitmap));
485 0 : cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
486 0 : cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
487 0 : cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
488 0 : cu_info->simd_per_cu = acu_info.simd_per_cu;
489 0 : cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
490 0 : cu_info->wave_front_size = acu_info.wave_front_size;
491 0 : cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
492 0 : cu_info->lds_size = acu_info.lds_size;
493 : }
494 :
495 0 : int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
496 : struct amdgpu_device **dmabuf_adev,
497 : uint64_t *bo_size, void *metadata_buffer,
498 : size_t buffer_size, uint32_t *metadata_size,
499 : uint32_t *flags)
500 : {
501 : struct dma_buf *dma_buf;
502 : struct drm_gem_object *obj;
503 : struct amdgpu_bo *bo;
504 : uint64_t metadata_flags;
505 0 : int r = -EINVAL;
506 :
507 0 : dma_buf = dma_buf_get(dma_buf_fd);
508 0 : if (IS_ERR(dma_buf))
509 0 : return PTR_ERR(dma_buf);
510 :
511 0 : if (dma_buf->ops != &amdgpu_dmabuf_ops)
512 : /* Can't handle non-graphics buffers */
513 : goto out_put;
514 :
515 0 : obj = dma_buf->priv;
516 0 : if (obj->dev->driver != adev_to_drm(adev)->driver)
517 : /* Can't handle buffers from different drivers */
518 : goto out_put;
519 :
520 0 : adev = drm_to_adev(obj->dev);
521 0 : bo = gem_to_amdgpu_bo(obj);
522 0 : if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
523 : AMDGPU_GEM_DOMAIN_GTT)))
524 : /* Only VRAM and GTT BOs are supported */
525 : goto out_put;
526 :
527 0 : r = 0;
528 0 : if (dmabuf_adev)
529 0 : *dmabuf_adev = adev;
530 0 : if (bo_size)
531 0 : *bo_size = amdgpu_bo_size(bo);
532 0 : if (metadata_buffer)
533 0 : r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
534 : metadata_size, &metadata_flags);
535 0 : if (flags) {
536 0 : *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
537 : KFD_IOC_ALLOC_MEM_FLAGS_VRAM
538 0 : : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
539 :
540 0 : if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
541 0 : *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
542 : }
543 :
544 : out_put:
545 0 : dma_buf_put(dma_buf);
546 0 : return r;
547 : }
548 :
549 0 : uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
550 : struct amdgpu_device *src)
551 : {
552 0 : struct amdgpu_device *peer_adev = src;
553 0 : struct amdgpu_device *adev = dst;
554 0 : int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
555 :
556 0 : if (ret < 0) {
557 0 : DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
558 : adev->gmc.xgmi.physical_node_id,
559 : peer_adev->gmc.xgmi.physical_node_id, ret);
560 0 : ret = 0;
561 : }
562 0 : return (uint8_t)ret;
563 : }
564 :
565 0 : int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
566 : struct amdgpu_device *src,
567 : bool is_min)
568 : {
569 0 : struct amdgpu_device *adev = dst, *peer_adev;
570 : int num_links;
571 :
572 0 : if (adev->asic_type != CHIP_ALDEBARAN)
573 : return 0;
574 :
575 0 : if (src)
576 0 : peer_adev = src;
577 :
578 : /* num links returns 0 for indirect peers since indirect route is unknown. */
579 0 : num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
580 0 : if (num_links < 0) {
581 0 : DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
582 : adev->gmc.xgmi.physical_node_id,
583 : peer_adev->gmc.xgmi.physical_node_id, num_links);
584 0 : num_links = 0;
585 : }
586 :
587 : /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
588 0 : return (num_links * 16 * 25000)/BITS_PER_BYTE;
589 : }
590 :
591 0 : int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
592 : {
593 0 : int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
594 0 : fls(adev->pm.pcie_mlw_mask)) - 1;
595 0 : int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
596 : CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
597 0 : fls(adev->pm.pcie_gen_mask &
598 0 : CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
599 0 : uint32_t num_lanes_mask = 1 << num_lanes_shift;
600 0 : uint32_t gen_speed_mask = 1 << gen_speed_shift;
601 0 : int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
602 :
603 0 : switch (num_lanes_mask) {
604 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
605 0 : num_lanes_factor = 1;
606 0 : break;
607 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
608 0 : num_lanes_factor = 2;
609 0 : break;
610 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
611 0 : num_lanes_factor = 4;
612 0 : break;
613 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
614 0 : num_lanes_factor = 8;
615 0 : break;
616 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
617 0 : num_lanes_factor = 12;
618 0 : break;
619 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
620 0 : num_lanes_factor = 16;
621 0 : break;
622 : case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
623 0 : num_lanes_factor = 32;
624 0 : break;
625 : }
626 :
627 0 : switch (gen_speed_mask) {
628 : case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
629 0 : gen_speed_mbits_factor = 2500;
630 0 : break;
631 : case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
632 0 : gen_speed_mbits_factor = 5000;
633 0 : break;
634 : case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
635 0 : gen_speed_mbits_factor = 8000;
636 0 : break;
637 : case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
638 0 : gen_speed_mbits_factor = 16000;
639 0 : break;
640 : case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
641 0 : gen_speed_mbits_factor = 32000;
642 0 : break;
643 : }
644 :
645 0 : return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
646 : }
647 :
648 0 : int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
649 : enum kgd_engine_type engine,
650 : uint32_t vmid, uint64_t gpu_addr,
651 : uint32_t *ib_cmd, uint32_t ib_len)
652 : {
653 : struct amdgpu_job *job;
654 : struct amdgpu_ib *ib;
655 : struct amdgpu_ring *ring;
656 0 : struct dma_fence *f = NULL;
657 : int ret;
658 :
659 0 : switch (engine) {
660 : case KGD_ENGINE_MEC1:
661 0 : ring = &adev->gfx.compute_ring[0];
662 0 : break;
663 : case KGD_ENGINE_SDMA1:
664 0 : ring = &adev->sdma.instance[0].ring;
665 0 : break;
666 : case KGD_ENGINE_SDMA2:
667 0 : ring = &adev->sdma.instance[1].ring;
668 0 : break;
669 : default:
670 0 : pr_err("Invalid engine in IB submission: %d\n", engine);
671 0 : ret = -EINVAL;
672 0 : goto err;
673 : }
674 :
675 0 : ret = amdgpu_job_alloc(adev, 1, &job, NULL);
676 0 : if (ret)
677 : goto err;
678 :
679 0 : ib = &job->ibs[0];
680 0 : memset(ib, 0, sizeof(struct amdgpu_ib));
681 :
682 0 : ib->gpu_addr = gpu_addr;
683 0 : ib->ptr = ib_cmd;
684 0 : ib->length_dw = ib_len;
685 : /* This works for NO_HWS. TODO: need to handle without knowing VMID */
686 0 : job->vmid = vmid;
687 :
688 0 : ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
689 :
690 0 : if (ret) {
691 0 : DRM_ERROR("amdgpu: failed to schedule IB.\n");
692 0 : goto err_ib_sched;
693 : }
694 :
695 : /* Drop the initial kref_init count (see drm_sched_main as example) */
696 0 : dma_fence_put(f);
697 0 : ret = dma_fence_wait(f, false);
698 :
699 : err_ib_sched:
700 0 : amdgpu_job_free(job);
701 : err:
702 0 : return ret;
703 : }
704 :
705 0 : void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
706 : {
707 0 : amdgpu_dpm_switch_power_profile(adev,
708 : PP_SMC_POWER_PROFILE_COMPUTE,
709 0 : !idle);
710 0 : }
711 :
712 0 : bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
713 : {
714 0 : if (adev->kfd.dev)
715 0 : return vmid >= adev->vm_manager.first_kfd_vmid;
716 :
717 : return false;
718 : }
719 :
720 0 : int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
721 : uint16_t vmid)
722 : {
723 0 : if (adev->family == AMDGPU_FAMILY_AI) {
724 : int i;
725 :
726 0 : for (i = 0; i < adev->num_vmhubs; i++)
727 0 : amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
728 : } else {
729 0 : amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
730 : }
731 :
732 0 : return 0;
733 : }
734 :
735 0 : int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
736 : uint16_t pasid, enum TLB_FLUSH_TYPE flush_type)
737 : {
738 0 : bool all_hub = false;
739 :
740 0 : if (adev->family == AMDGPU_FAMILY_AI ||
741 : adev->family == AMDGPU_FAMILY_RV)
742 0 : all_hub = true;
743 :
744 0 : return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
745 : }
746 :
747 0 : bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
748 : {
749 0 : return adev->have_atomics_support;
750 : }
751 :
752 0 : void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
753 : {
754 0 : struct ras_err_data err_data = {0, 0, 0, NULL};
755 :
756 : /* CPU MCA will handle page retirement if connected_to_cpu is 1 */
757 0 : if (!adev->gmc.xgmi.connected_to_cpu)
758 0 : amdgpu_umc_poison_handler(adev, &err_data, reset);
759 0 : else if (reset)
760 0 : amdgpu_amdkfd_gpu_reset(adev);
761 0 : }
762 :
763 0 : bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
764 : {
765 0 : if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
766 0 : return adev->gfx.ras->query_utcl2_poison_status(adev);
767 : else
768 : return false;
769 : }
|
