Line data Source code
1 : /*
2 : * Copyright 2007-8 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: Dave Airlie
24 : * Alex Deucher
25 : */
26 :
27 : #include <drm/display/drm_dp_helper.h>
28 : #include <drm/drm_edid.h>
29 : #include <drm/drm_fb_helper.h>
30 : #include <drm/drm_probe_helper.h>
31 : #include <drm/amdgpu_drm.h>
32 : #include "amdgpu.h"
33 : #include "atom.h"
34 : #include "atombios_encoders.h"
35 : #include "atombios_dp.h"
36 : #include "amdgpu_connectors.h"
37 : #include "amdgpu_i2c.h"
38 : #include "amdgpu_display.h"
39 :
40 : #include <linux/pm_runtime.h>
41 :
42 0 : void amdgpu_connector_hotplug(struct drm_connector *connector)
43 : {
44 0 : struct drm_device *dev = connector->dev;
45 0 : struct amdgpu_device *adev = drm_to_adev(dev);
46 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
47 :
48 : /* bail if the connector does not have hpd pin, e.g.,
49 : * VGA, TV, etc.
50 : */
51 0 : if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
52 : return;
53 :
54 0 : amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
55 :
56 : /* if the connector is already off, don't turn it back on */
57 0 : if (connector->dpms != DRM_MODE_DPMS_ON)
58 : return;
59 :
60 : /* just deal with DP (not eDP) here. */
61 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
62 0 : struct amdgpu_connector_atom_dig *dig_connector =
63 : amdgpu_connector->con_priv;
64 :
65 : /* if existing sink type was not DP no need to retrain */
66 0 : if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
67 : return;
68 :
69 : /* first get sink type as it may be reset after (un)plug */
70 0 : dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
71 : /* don't do anything if sink is not display port, i.e.,
72 : * passive dp->(dvi|hdmi) adaptor
73 : */
74 0 : if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
75 0 : amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
76 0 : amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
77 : /* Don't start link training before we have the DPCD */
78 0 : if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
79 : return;
80 :
81 : /* Turn the connector off and back on immediately, which
82 : * will trigger link training
83 : */
84 0 : drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
85 0 : drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
86 : }
87 : }
88 : }
89 :
90 0 : static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
91 : {
92 0 : struct drm_crtc *crtc = encoder->crtc;
93 :
94 0 : if (crtc && crtc->enabled) {
95 0 : drm_crtc_helper_set_mode(crtc, &crtc->mode,
96 0 : crtc->x, crtc->y, crtc->primary->fb);
97 : }
98 0 : }
99 :
100 0 : int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
101 : {
102 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
103 : struct amdgpu_connector_atom_dig *dig_connector;
104 0 : int bpc = 8;
105 : unsigned mode_clock, max_tmds_clock;
106 :
107 0 : switch (connector->connector_type) {
108 : case DRM_MODE_CONNECTOR_DVII:
109 : case DRM_MODE_CONNECTOR_HDMIB:
110 0 : if (amdgpu_connector->use_digital) {
111 0 : if (connector->display_info.is_hdmi) {
112 0 : if (connector->display_info.bpc)
113 0 : bpc = connector->display_info.bpc;
114 : }
115 : }
116 : break;
117 : case DRM_MODE_CONNECTOR_DVID:
118 : case DRM_MODE_CONNECTOR_HDMIA:
119 0 : if (connector->display_info.is_hdmi) {
120 0 : if (connector->display_info.bpc)
121 0 : bpc = connector->display_info.bpc;
122 : }
123 : break;
124 : case DRM_MODE_CONNECTOR_DisplayPort:
125 0 : dig_connector = amdgpu_connector->con_priv;
126 0 : if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
127 0 : (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
128 0 : connector->display_info.is_hdmi) {
129 0 : if (connector->display_info.bpc)
130 0 : bpc = connector->display_info.bpc;
131 : }
132 : break;
133 : case DRM_MODE_CONNECTOR_eDP:
134 : case DRM_MODE_CONNECTOR_LVDS:
135 0 : if (connector->display_info.bpc)
136 0 : bpc = connector->display_info.bpc;
137 : else {
138 0 : const struct drm_connector_helper_funcs *connector_funcs =
139 : connector->helper_private;
140 0 : struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
141 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
142 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
143 :
144 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
145 : bpc = 6;
146 : else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
147 : bpc = 8;
148 : }
149 : break;
150 : }
151 :
152 0 : if (connector->display_info.is_hdmi) {
153 : /*
154 : * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
155 : * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
156 : * 12 bpc is always supported on hdmi deep color sinks, as this is
157 : * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
158 : */
159 0 : if (bpc > 12) {
160 0 : DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
161 : connector->name, bpc);
162 0 : bpc = 12;
163 : }
164 :
165 : /* Any defined maximum tmds clock limit we must not exceed? */
166 0 : if (connector->display_info.max_tmds_clock > 0) {
167 : /* mode_clock is clock in kHz for mode to be modeset on this connector */
168 0 : mode_clock = amdgpu_connector->pixelclock_for_modeset;
169 :
170 : /* Maximum allowable input clock in kHz */
171 0 : max_tmds_clock = connector->display_info.max_tmds_clock;
172 :
173 0 : DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
174 : connector->name, mode_clock, max_tmds_clock);
175 :
176 : /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
177 0 : if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
178 0 : if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
179 0 : (mode_clock * 5/4 <= max_tmds_clock))
180 : bpc = 10;
181 : else
182 0 : bpc = 8;
183 :
184 0 : DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
185 : connector->name, bpc);
186 : }
187 :
188 0 : if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
189 0 : bpc = 8;
190 0 : DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
191 : connector->name, bpc);
192 : }
193 0 : } else if (bpc > 8) {
194 : /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
195 0 : DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
196 : connector->name);
197 0 : bpc = 8;
198 : }
199 : }
200 :
201 0 : if ((amdgpu_deep_color == 0) && (bpc > 8)) {
202 0 : DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
203 : connector->name);
204 0 : bpc = 8;
205 : }
206 :
207 0 : DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
208 : connector->name, connector->display_info.bpc, bpc);
209 :
210 0 : return bpc;
211 : }
212 :
213 : static void
214 0 : amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
215 : enum drm_connector_status status)
216 : {
217 : struct drm_encoder *best_encoder;
218 : struct drm_encoder *encoder;
219 0 : const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
220 : bool connected;
221 :
222 0 : best_encoder = connector_funcs->best_encoder(connector);
223 :
224 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
225 0 : if ((encoder == best_encoder) && (status == connector_status_connected))
226 : connected = true;
227 : else
228 0 : connected = false;
229 :
230 0 : amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
231 : }
232 0 : }
233 :
234 : static struct drm_encoder *
235 : amdgpu_connector_find_encoder(struct drm_connector *connector,
236 : int encoder_type)
237 : {
238 : struct drm_encoder *encoder;
239 :
240 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
241 0 : if (encoder->encoder_type == encoder_type)
242 : return encoder;
243 : }
244 :
245 : return NULL;
246 : }
247 :
248 0 : struct edid *amdgpu_connector_edid(struct drm_connector *connector)
249 : {
250 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
251 0 : struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
252 :
253 0 : if (amdgpu_connector->edid) {
254 : return amdgpu_connector->edid;
255 0 : } else if (edid_blob) {
256 0 : struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
257 0 : if (edid)
258 0 : amdgpu_connector->edid = edid;
259 : }
260 0 : return amdgpu_connector->edid;
261 : }
262 :
263 : static struct edid *
264 0 : amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
265 : {
266 : struct edid *edid;
267 :
268 0 : if (adev->mode_info.bios_hardcoded_edid) {
269 0 : edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
270 0 : if (edid) {
271 0 : memcpy((unsigned char *)edid,
272 0 : (unsigned char *)adev->mode_info.bios_hardcoded_edid,
273 0 : adev->mode_info.bios_hardcoded_edid_size);
274 : return edid;
275 : }
276 : }
277 : return NULL;
278 : }
279 :
280 0 : static void amdgpu_connector_get_edid(struct drm_connector *connector)
281 : {
282 0 : struct drm_device *dev = connector->dev;
283 0 : struct amdgpu_device *adev = drm_to_adev(dev);
284 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
285 :
286 0 : if (amdgpu_connector->edid)
287 : return;
288 :
289 : /* on hw with routers, select right port */
290 0 : if (amdgpu_connector->router.ddc_valid)
291 0 : amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
292 :
293 0 : if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
294 0 : ENCODER_OBJECT_ID_NONE) &&
295 0 : amdgpu_connector->ddc_bus->has_aux) {
296 0 : amdgpu_connector->edid = drm_get_edid(connector,
297 : &amdgpu_connector->ddc_bus->aux.ddc);
298 0 : } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
299 : (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
300 0 : struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
301 :
302 0 : if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
303 0 : dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
304 0 : amdgpu_connector->ddc_bus->has_aux)
305 0 : amdgpu_connector->edid = drm_get_edid(connector,
306 : &amdgpu_connector->ddc_bus->aux.ddc);
307 0 : else if (amdgpu_connector->ddc_bus)
308 0 : amdgpu_connector->edid = drm_get_edid(connector,
309 : &amdgpu_connector->ddc_bus->adapter);
310 0 : } else if (amdgpu_connector->ddc_bus) {
311 0 : amdgpu_connector->edid = drm_get_edid(connector,
312 : &amdgpu_connector->ddc_bus->adapter);
313 : }
314 :
315 0 : if (!amdgpu_connector->edid) {
316 : /* some laptops provide a hardcoded edid in rom for LCDs */
317 0 : if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
318 : (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
319 0 : amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
320 0 : drm_connector_update_edid_property(connector, amdgpu_connector->edid);
321 : }
322 : }
323 : }
324 :
325 : static void amdgpu_connector_free_edid(struct drm_connector *connector)
326 : {
327 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
328 :
329 0 : kfree(amdgpu_connector->edid);
330 0 : amdgpu_connector->edid = NULL;
331 0 : drm_connector_update_edid_property(connector, NULL);
332 : }
333 :
334 0 : static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
335 : {
336 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
337 : int ret;
338 :
339 0 : if (amdgpu_connector->edid) {
340 0 : drm_connector_update_edid_property(connector, amdgpu_connector->edid);
341 0 : ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
342 0 : return ret;
343 : }
344 0 : drm_connector_update_edid_property(connector, NULL);
345 0 : return 0;
346 : }
347 :
348 : static struct drm_encoder *
349 0 : amdgpu_connector_best_single_encoder(struct drm_connector *connector)
350 : {
351 : struct drm_encoder *encoder;
352 :
353 : /* pick the first one */
354 0 : drm_connector_for_each_possible_encoder(connector, encoder)
355 : return encoder;
356 :
357 : return NULL;
358 : }
359 :
360 0 : static void amdgpu_get_native_mode(struct drm_connector *connector)
361 : {
362 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
363 : struct amdgpu_encoder *amdgpu_encoder;
364 :
365 0 : if (encoder == NULL)
366 : return;
367 :
368 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
369 :
370 0 : if (!list_empty(&connector->probed_modes)) {
371 0 : struct drm_display_mode *preferred_mode =
372 0 : list_first_entry(&connector->probed_modes,
373 : struct drm_display_mode, head);
374 :
375 0 : amdgpu_encoder->native_mode = *preferred_mode;
376 : } else {
377 0 : amdgpu_encoder->native_mode.clock = 0;
378 : }
379 : }
380 :
381 : static struct drm_display_mode *
382 0 : amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
383 : {
384 0 : struct drm_device *dev = encoder->dev;
385 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
386 0 : struct drm_display_mode *mode = NULL;
387 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
388 :
389 0 : if (native_mode->hdisplay != 0 &&
390 0 : native_mode->vdisplay != 0 &&
391 0 : native_mode->clock != 0) {
392 0 : mode = drm_mode_duplicate(dev, native_mode);
393 0 : if (!mode)
394 : return NULL;
395 :
396 0 : mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
397 0 : drm_mode_set_name(mode);
398 :
399 0 : DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
400 0 : } else if (native_mode->hdisplay != 0 &&
401 0 : native_mode->vdisplay != 0) {
402 : /* mac laptops without an edid */
403 : /* Note that this is not necessarily the exact panel mode,
404 : * but an approximation based on the cvt formula. For these
405 : * systems we should ideally read the mode info out of the
406 : * registers or add a mode table, but this works and is much
407 : * simpler.
408 : */
409 0 : mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
410 0 : if (!mode)
411 : return NULL;
412 :
413 0 : mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
414 0 : DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
415 : }
416 : return mode;
417 : }
418 :
419 0 : static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
420 : struct drm_connector *connector)
421 : {
422 0 : struct drm_device *dev = encoder->dev;
423 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
424 0 : struct drm_display_mode *mode = NULL;
425 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
426 : int i;
427 : static const struct mode_size {
428 : int w;
429 : int h;
430 : } common_modes[17] = {
431 : { 640, 480},
432 : { 720, 480},
433 : { 800, 600},
434 : { 848, 480},
435 : {1024, 768},
436 : {1152, 768},
437 : {1280, 720},
438 : {1280, 800},
439 : {1280, 854},
440 : {1280, 960},
441 : {1280, 1024},
442 : {1440, 900},
443 : {1400, 1050},
444 : {1680, 1050},
445 : {1600, 1200},
446 : {1920, 1080},
447 : {1920, 1200}
448 : };
449 :
450 0 : for (i = 0; i < 17; i++) {
451 0 : if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
452 0 : if (common_modes[i].w > 1024 ||
453 0 : common_modes[i].h > 768)
454 0 : continue;
455 : }
456 0 : if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
457 0 : if (common_modes[i].w > native_mode->hdisplay ||
458 0 : common_modes[i].h > native_mode->vdisplay ||
459 0 : (common_modes[i].w == native_mode->hdisplay &&
460 : common_modes[i].h == native_mode->vdisplay))
461 0 : continue;
462 : }
463 0 : if (common_modes[i].w < 320 || common_modes[i].h < 200)
464 0 : continue;
465 :
466 0 : mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
467 0 : drm_mode_probed_add(connector, mode);
468 : }
469 0 : }
470 :
471 0 : static int amdgpu_connector_set_property(struct drm_connector *connector,
472 : struct drm_property *property,
473 : uint64_t val)
474 : {
475 0 : struct drm_device *dev = connector->dev;
476 0 : struct amdgpu_device *adev = drm_to_adev(dev);
477 : struct drm_encoder *encoder;
478 : struct amdgpu_encoder *amdgpu_encoder;
479 :
480 0 : if (property == adev->mode_info.coherent_mode_property) {
481 : struct amdgpu_encoder_atom_dig *dig;
482 : bool new_coherent_mode;
483 :
484 : /* need to find digital encoder on connector */
485 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
486 0 : if (!encoder)
487 : return 0;
488 :
489 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
490 :
491 0 : if (!amdgpu_encoder->enc_priv)
492 : return 0;
493 :
494 0 : dig = amdgpu_encoder->enc_priv;
495 0 : new_coherent_mode = val ? true : false;
496 0 : if (dig->coherent_mode != new_coherent_mode) {
497 0 : dig->coherent_mode = new_coherent_mode;
498 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
499 : }
500 : }
501 :
502 0 : if (property == adev->mode_info.audio_property) {
503 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
504 : /* need to find digital encoder on connector */
505 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
506 0 : if (!encoder)
507 : return 0;
508 :
509 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
510 :
511 0 : if (amdgpu_connector->audio != val) {
512 0 : amdgpu_connector->audio = val;
513 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
514 : }
515 : }
516 :
517 0 : if (property == adev->mode_info.dither_property) {
518 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
519 : /* need to find digital encoder on connector */
520 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
521 0 : if (!encoder)
522 : return 0;
523 :
524 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
525 :
526 0 : if (amdgpu_connector->dither != val) {
527 0 : amdgpu_connector->dither = val;
528 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
529 : }
530 : }
531 :
532 0 : if (property == adev->mode_info.underscan_property) {
533 : /* need to find digital encoder on connector */
534 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
535 0 : if (!encoder)
536 : return 0;
537 :
538 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
539 :
540 0 : if (amdgpu_encoder->underscan_type != val) {
541 0 : amdgpu_encoder->underscan_type = val;
542 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
543 : }
544 : }
545 :
546 0 : if (property == adev->mode_info.underscan_hborder_property) {
547 : /* need to find digital encoder on connector */
548 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
549 0 : if (!encoder)
550 : return 0;
551 :
552 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
553 :
554 0 : if (amdgpu_encoder->underscan_hborder != val) {
555 0 : amdgpu_encoder->underscan_hborder = val;
556 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
557 : }
558 : }
559 :
560 0 : if (property == adev->mode_info.underscan_vborder_property) {
561 : /* need to find digital encoder on connector */
562 0 : encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
563 0 : if (!encoder)
564 : return 0;
565 :
566 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
567 :
568 0 : if (amdgpu_encoder->underscan_vborder != val) {
569 0 : amdgpu_encoder->underscan_vborder = val;
570 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
571 : }
572 : }
573 :
574 0 : if (property == adev->mode_info.load_detect_property) {
575 0 : struct amdgpu_connector *amdgpu_connector =
576 0 : to_amdgpu_connector(connector);
577 :
578 0 : if (val == 0)
579 0 : amdgpu_connector->dac_load_detect = false;
580 : else
581 0 : amdgpu_connector->dac_load_detect = true;
582 : }
583 :
584 0 : if (property == dev->mode_config.scaling_mode_property) {
585 : enum amdgpu_rmx_type rmx_type;
586 :
587 0 : if (connector->encoder) {
588 : amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
589 : } else {
590 0 : const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
591 0 : amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
592 : }
593 :
594 : switch (val) {
595 : default:
596 : case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
597 : case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
598 : case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
599 : case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
600 : }
601 0 : if (amdgpu_encoder->rmx_type == rmx_type)
602 : return 0;
603 :
604 0 : if ((rmx_type != DRM_MODE_SCALE_NONE) &&
605 0 : (amdgpu_encoder->native_mode.clock == 0))
606 : return 0;
607 :
608 0 : amdgpu_encoder->rmx_type = rmx_type;
609 :
610 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
611 : }
612 :
613 : return 0;
614 : }
615 :
616 : static void
617 0 : amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
618 : struct drm_connector *connector)
619 : {
620 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
621 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
622 : struct drm_display_mode *t, *mode;
623 :
624 : /* If the EDID preferred mode doesn't match the native mode, use it */
625 0 : list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
626 0 : if (mode->type & DRM_MODE_TYPE_PREFERRED) {
627 0 : if (mode->hdisplay != native_mode->hdisplay ||
628 0 : mode->vdisplay != native_mode->vdisplay)
629 0 : drm_mode_copy(native_mode, mode);
630 : }
631 : }
632 :
633 : /* Try to get native mode details from EDID if necessary */
634 0 : if (!native_mode->clock) {
635 0 : list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
636 0 : if (mode->hdisplay == native_mode->hdisplay &&
637 0 : mode->vdisplay == native_mode->vdisplay) {
638 0 : drm_mode_copy(native_mode, mode);
639 0 : drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
640 0 : DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
641 0 : break;
642 : }
643 : }
644 : }
645 :
646 0 : if (!native_mode->clock) {
647 0 : DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
648 0 : amdgpu_encoder->rmx_type = RMX_OFF;
649 : }
650 0 : }
651 :
652 0 : static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
653 : {
654 : struct drm_encoder *encoder;
655 0 : int ret = 0;
656 : struct drm_display_mode *mode;
657 :
658 0 : amdgpu_connector_get_edid(connector);
659 0 : ret = amdgpu_connector_ddc_get_modes(connector);
660 0 : if (ret > 0) {
661 0 : encoder = amdgpu_connector_best_single_encoder(connector);
662 0 : if (encoder) {
663 0 : amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
664 : /* add scaled modes */
665 0 : amdgpu_connector_add_common_modes(encoder, connector);
666 : }
667 : return ret;
668 : }
669 :
670 0 : encoder = amdgpu_connector_best_single_encoder(connector);
671 0 : if (!encoder)
672 : return 0;
673 :
674 : /* we have no EDID modes */
675 0 : mode = amdgpu_connector_lcd_native_mode(encoder);
676 0 : if (mode) {
677 0 : ret = 1;
678 0 : drm_mode_probed_add(connector, mode);
679 : /* add the width/height from vbios tables if available */
680 0 : connector->display_info.width_mm = mode->width_mm;
681 0 : connector->display_info.height_mm = mode->height_mm;
682 : /* add scaled modes */
683 0 : amdgpu_connector_add_common_modes(encoder, connector);
684 : }
685 :
686 : return ret;
687 : }
688 :
689 0 : static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
690 : struct drm_display_mode *mode)
691 : {
692 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
693 :
694 0 : if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
695 : return MODE_PANEL;
696 :
697 0 : if (encoder) {
698 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
699 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
700 :
701 : /* AVIVO hardware supports downscaling modes larger than the panel
702 : * to the panel size, but I'm not sure this is desirable.
703 : */
704 0 : if ((mode->hdisplay > native_mode->hdisplay) ||
705 0 : (mode->vdisplay > native_mode->vdisplay))
706 : return MODE_PANEL;
707 :
708 : /* if scaling is disabled, block non-native modes */
709 0 : if (amdgpu_encoder->rmx_type == RMX_OFF) {
710 0 : if ((mode->hdisplay != native_mode->hdisplay) ||
711 : (mode->vdisplay != native_mode->vdisplay))
712 : return MODE_PANEL;
713 : }
714 : }
715 :
716 0 : return MODE_OK;
717 : }
718 :
719 : static enum drm_connector_status
720 0 : amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
721 : {
722 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
723 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
724 0 : enum drm_connector_status ret = connector_status_disconnected;
725 : int r;
726 :
727 0 : if (!drm_kms_helper_is_poll_worker()) {
728 0 : r = pm_runtime_get_sync(connector->dev->dev);
729 0 : if (r < 0) {
730 0 : pm_runtime_put_autosuspend(connector->dev->dev);
731 0 : return connector_status_disconnected;
732 : }
733 : }
734 :
735 0 : if (encoder) {
736 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
737 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
738 :
739 : /* check if panel is valid */
740 0 : if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
741 0 : ret = connector_status_connected;
742 :
743 : }
744 :
745 : /* check for edid as well */
746 0 : amdgpu_connector_get_edid(connector);
747 0 : if (amdgpu_connector->edid)
748 0 : ret = connector_status_connected;
749 : /* check acpi lid status ??? */
750 :
751 0 : amdgpu_connector_update_scratch_regs(connector, ret);
752 :
753 0 : if (!drm_kms_helper_is_poll_worker()) {
754 0 : pm_runtime_mark_last_busy(connector->dev->dev);
755 0 : pm_runtime_put_autosuspend(connector->dev->dev);
756 : }
757 :
758 : return ret;
759 : }
760 :
761 0 : static void amdgpu_connector_unregister(struct drm_connector *connector)
762 : {
763 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
764 :
765 0 : if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
766 0 : drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
767 0 : amdgpu_connector->ddc_bus->has_aux = false;
768 : }
769 0 : }
770 :
771 0 : static void amdgpu_connector_destroy(struct drm_connector *connector)
772 : {
773 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
774 :
775 0 : amdgpu_connector_free_edid(connector);
776 0 : kfree(amdgpu_connector->con_priv);
777 0 : drm_connector_unregister(connector);
778 0 : drm_connector_cleanup(connector);
779 0 : kfree(connector);
780 0 : }
781 :
782 0 : static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
783 : struct drm_property *property,
784 : uint64_t value)
785 : {
786 0 : struct drm_device *dev = connector->dev;
787 : struct amdgpu_encoder *amdgpu_encoder;
788 : enum amdgpu_rmx_type rmx_type;
789 :
790 0 : DRM_DEBUG_KMS("\n");
791 0 : if (property != dev->mode_config.scaling_mode_property)
792 : return 0;
793 :
794 0 : if (connector->encoder)
795 : amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
796 : else {
797 0 : const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
798 0 : amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
799 : }
800 :
801 : switch (value) {
802 : case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
803 : case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
804 : case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
805 : default:
806 : case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
807 : }
808 0 : if (amdgpu_encoder->rmx_type == rmx_type)
809 : return 0;
810 :
811 0 : amdgpu_encoder->rmx_type = rmx_type;
812 :
813 0 : amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
814 0 : return 0;
815 : }
816 :
817 :
818 : static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
819 : .get_modes = amdgpu_connector_lvds_get_modes,
820 : .mode_valid = amdgpu_connector_lvds_mode_valid,
821 : .best_encoder = amdgpu_connector_best_single_encoder,
822 : };
823 :
824 : static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
825 : .dpms = drm_helper_connector_dpms,
826 : .detect = amdgpu_connector_lvds_detect,
827 : .fill_modes = drm_helper_probe_single_connector_modes,
828 : .early_unregister = amdgpu_connector_unregister,
829 : .destroy = amdgpu_connector_destroy,
830 : .set_property = amdgpu_connector_set_lcd_property,
831 : };
832 :
833 0 : static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
834 : {
835 : int ret;
836 :
837 0 : amdgpu_connector_get_edid(connector);
838 0 : ret = amdgpu_connector_ddc_get_modes(connector);
839 0 : amdgpu_get_native_mode(connector);
840 :
841 0 : return ret;
842 : }
843 :
844 0 : static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
845 : struct drm_display_mode *mode)
846 : {
847 0 : struct drm_device *dev = connector->dev;
848 0 : struct amdgpu_device *adev = drm_to_adev(dev);
849 :
850 : /* XXX check mode bandwidth */
851 :
852 0 : if ((mode->clock / 10) > adev->clock.max_pixel_clock)
853 : return MODE_CLOCK_HIGH;
854 :
855 0 : return MODE_OK;
856 : }
857 :
858 : static enum drm_connector_status
859 0 : amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
860 : {
861 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
862 : struct drm_encoder *encoder;
863 : const struct drm_encoder_helper_funcs *encoder_funcs;
864 0 : bool dret = false;
865 0 : enum drm_connector_status ret = connector_status_disconnected;
866 : int r;
867 :
868 0 : if (!drm_kms_helper_is_poll_worker()) {
869 0 : r = pm_runtime_get_sync(connector->dev->dev);
870 0 : if (r < 0) {
871 0 : pm_runtime_put_autosuspend(connector->dev->dev);
872 0 : return connector_status_disconnected;
873 : }
874 : }
875 :
876 0 : encoder = amdgpu_connector_best_single_encoder(connector);
877 : if (!encoder)
878 : ret = connector_status_disconnected;
879 :
880 0 : if (amdgpu_connector->ddc_bus)
881 0 : dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
882 0 : if (dret) {
883 0 : amdgpu_connector->detected_by_load = false;
884 0 : amdgpu_connector_free_edid(connector);
885 0 : amdgpu_connector_get_edid(connector);
886 :
887 0 : if (!amdgpu_connector->edid) {
888 0 : DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
889 : connector->name);
890 0 : ret = connector_status_connected;
891 : } else {
892 0 : amdgpu_connector->use_digital =
893 0 : !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
894 :
895 : /* some oems have boards with separate digital and analog connectors
896 : * with a shared ddc line (often vga + hdmi)
897 : */
898 0 : if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
899 0 : amdgpu_connector_free_edid(connector);
900 0 : ret = connector_status_disconnected;
901 : } else {
902 : ret = connector_status_connected;
903 : }
904 : }
905 : } else {
906 :
907 : /* if we aren't forcing don't do destructive polling */
908 0 : if (!force) {
909 : /* only return the previous status if we last
910 : * detected a monitor via load.
911 : */
912 0 : if (amdgpu_connector->detected_by_load)
913 0 : ret = connector->status;
914 : goto out;
915 : }
916 :
917 0 : if (amdgpu_connector->dac_load_detect && encoder) {
918 0 : encoder_funcs = encoder->helper_private;
919 0 : ret = encoder_funcs->detect(encoder, connector);
920 0 : if (ret != connector_status_disconnected)
921 0 : amdgpu_connector->detected_by_load = true;
922 : }
923 : }
924 :
925 0 : amdgpu_connector_update_scratch_regs(connector, ret);
926 :
927 : out:
928 0 : if (!drm_kms_helper_is_poll_worker()) {
929 0 : pm_runtime_mark_last_busy(connector->dev->dev);
930 0 : pm_runtime_put_autosuspend(connector->dev->dev);
931 : }
932 :
933 : return ret;
934 : }
935 :
936 : static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
937 : .get_modes = amdgpu_connector_vga_get_modes,
938 : .mode_valid = amdgpu_connector_vga_mode_valid,
939 : .best_encoder = amdgpu_connector_best_single_encoder,
940 : };
941 :
942 : static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
943 : .dpms = drm_helper_connector_dpms,
944 : .detect = amdgpu_connector_vga_detect,
945 : .fill_modes = drm_helper_probe_single_connector_modes,
946 : .early_unregister = amdgpu_connector_unregister,
947 : .destroy = amdgpu_connector_destroy,
948 : .set_property = amdgpu_connector_set_property,
949 : };
950 :
951 : static bool
952 : amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
953 : {
954 0 : struct drm_device *dev = connector->dev;
955 0 : struct amdgpu_device *adev = drm_to_adev(dev);
956 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
957 : enum drm_connector_status status;
958 :
959 0 : if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
960 0 : if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
961 : status = connector_status_connected;
962 : else
963 0 : status = connector_status_disconnected;
964 0 : if (connector->status == status)
965 : return true;
966 : }
967 :
968 : return false;
969 : }
970 :
971 : /*
972 : * DVI is complicated
973 : * Do a DDC probe, if DDC probe passes, get the full EDID so
974 : * we can do analog/digital monitor detection at this point.
975 : * If the monitor is an analog monitor or we got no DDC,
976 : * we need to find the DAC encoder object for this connector.
977 : * If we got no DDC, we do load detection on the DAC encoder object.
978 : * If we got analog DDC or load detection passes on the DAC encoder
979 : * we have to check if this analog encoder is shared with anyone else (TV)
980 : * if its shared we have to set the other connector to disconnected.
981 : */
982 : static enum drm_connector_status
983 0 : amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
984 : {
985 0 : struct drm_device *dev = connector->dev;
986 0 : struct amdgpu_device *adev = drm_to_adev(dev);
987 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
988 : const struct drm_encoder_helper_funcs *encoder_funcs;
989 : int r;
990 0 : enum drm_connector_status ret = connector_status_disconnected;
991 0 : bool dret = false, broken_edid = false;
992 :
993 0 : if (!drm_kms_helper_is_poll_worker()) {
994 0 : r = pm_runtime_get_sync(connector->dev->dev);
995 0 : if (r < 0) {
996 0 : pm_runtime_put_autosuspend(connector->dev->dev);
997 0 : return connector_status_disconnected;
998 : }
999 : }
1000 :
1001 0 : if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1002 0 : ret = connector->status;
1003 0 : goto exit;
1004 : }
1005 :
1006 0 : if (amdgpu_connector->ddc_bus)
1007 0 : dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1008 0 : if (dret) {
1009 0 : amdgpu_connector->detected_by_load = false;
1010 0 : amdgpu_connector_free_edid(connector);
1011 0 : amdgpu_connector_get_edid(connector);
1012 :
1013 0 : if (!amdgpu_connector->edid) {
1014 0 : DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1015 : connector->name);
1016 0 : ret = connector_status_connected;
1017 0 : broken_edid = true; /* defer use_digital to later */
1018 : } else {
1019 0 : amdgpu_connector->use_digital =
1020 0 : !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1021 :
1022 : /* some oems have boards with separate digital and analog connectors
1023 : * with a shared ddc line (often vga + hdmi)
1024 : */
1025 0 : if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1026 0 : amdgpu_connector_free_edid(connector);
1027 0 : ret = connector_status_disconnected;
1028 : } else {
1029 : ret = connector_status_connected;
1030 : }
1031 :
1032 : /* This gets complicated. We have boards with VGA + HDMI with a
1033 : * shared DDC line and we have boards with DVI-D + HDMI with a shared
1034 : * DDC line. The latter is more complex because with DVI<->HDMI adapters
1035 : * you don't really know what's connected to which port as both are digital.
1036 : */
1037 0 : if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1038 : struct drm_connector *list_connector;
1039 : struct drm_connector_list_iter iter;
1040 : struct amdgpu_connector *list_amdgpu_connector;
1041 :
1042 0 : drm_connector_list_iter_begin(dev, &iter);
1043 0 : drm_for_each_connector_iter(list_connector,
1044 : &iter) {
1045 0 : if (connector == list_connector)
1046 0 : continue;
1047 0 : list_amdgpu_connector = to_amdgpu_connector(list_connector);
1048 0 : if (list_amdgpu_connector->shared_ddc &&
1049 0 : (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1050 0 : amdgpu_connector->ddc_bus->rec.i2c_id)) {
1051 : /* cases where both connectors are digital */
1052 0 : if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1053 : /* hpd is our only option in this case */
1054 0 : if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1055 0 : amdgpu_connector_free_edid(connector);
1056 0 : ret = connector_status_disconnected;
1057 : }
1058 : }
1059 : }
1060 : }
1061 0 : drm_connector_list_iter_end(&iter);
1062 : }
1063 : }
1064 : }
1065 :
1066 0 : if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1067 : goto out;
1068 :
1069 : /* DVI-D and HDMI-A are digital only */
1070 0 : if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1071 : (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1072 : goto out;
1073 :
1074 : /* if we aren't forcing don't do destructive polling */
1075 0 : if (!force) {
1076 : /* only return the previous status if we last
1077 : * detected a monitor via load.
1078 : */
1079 0 : if (amdgpu_connector->detected_by_load)
1080 0 : ret = connector->status;
1081 : goto out;
1082 : }
1083 :
1084 : /* find analog encoder */
1085 0 : if (amdgpu_connector->dac_load_detect) {
1086 : struct drm_encoder *encoder;
1087 :
1088 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
1089 0 : if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1090 : encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1091 0 : continue;
1092 :
1093 0 : encoder_funcs = encoder->helper_private;
1094 0 : if (encoder_funcs->detect) {
1095 0 : if (!broken_edid) {
1096 0 : if (ret != connector_status_connected) {
1097 : /* deal with analog monitors without DDC */
1098 0 : ret = encoder_funcs->detect(encoder, connector);
1099 0 : if (ret == connector_status_connected) {
1100 0 : amdgpu_connector->use_digital = false;
1101 : }
1102 0 : if (ret != connector_status_disconnected)
1103 0 : amdgpu_connector->detected_by_load = true;
1104 : }
1105 : } else {
1106 : enum drm_connector_status lret;
1107 : /* assume digital unless load detected otherwise */
1108 0 : amdgpu_connector->use_digital = true;
1109 0 : lret = encoder_funcs->detect(encoder, connector);
1110 0 : DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1111 0 : if (lret == connector_status_connected)
1112 0 : amdgpu_connector->use_digital = false;
1113 : }
1114 : break;
1115 : }
1116 : }
1117 : }
1118 :
1119 : out:
1120 : /* updated in get modes as well since we need to know if it's analog or digital */
1121 0 : amdgpu_connector_update_scratch_regs(connector, ret);
1122 :
1123 : exit:
1124 0 : if (!drm_kms_helper_is_poll_worker()) {
1125 0 : pm_runtime_mark_last_busy(connector->dev->dev);
1126 0 : pm_runtime_put_autosuspend(connector->dev->dev);
1127 : }
1128 :
1129 : return ret;
1130 : }
1131 :
1132 : /* okay need to be smart in here about which encoder to pick */
1133 : static struct drm_encoder *
1134 0 : amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1135 : {
1136 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1137 : struct drm_encoder *encoder;
1138 :
1139 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
1140 0 : if (amdgpu_connector->use_digital == true) {
1141 0 : if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1142 : return encoder;
1143 : } else {
1144 0 : if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1145 : encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1146 : return encoder;
1147 : }
1148 : }
1149 :
1150 : /* see if we have a default encoder TODO */
1151 :
1152 : /* then check use digitial */
1153 : /* pick the first one */
1154 0 : drm_connector_for_each_possible_encoder(connector, encoder)
1155 : return encoder;
1156 :
1157 : return NULL;
1158 : }
1159 :
1160 0 : static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1161 : {
1162 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1163 0 : if (connector->force == DRM_FORCE_ON)
1164 0 : amdgpu_connector->use_digital = false;
1165 0 : if (connector->force == DRM_FORCE_ON_DIGITAL)
1166 0 : amdgpu_connector->use_digital = true;
1167 0 : }
1168 :
1169 0 : static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1170 : struct drm_display_mode *mode)
1171 : {
1172 0 : struct drm_device *dev = connector->dev;
1173 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1174 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1175 :
1176 : /* XXX check mode bandwidth */
1177 :
1178 0 : if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1179 0 : if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1180 0 : (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1181 : (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1182 : return MODE_OK;
1183 0 : } else if (connector->display_info.is_hdmi) {
1184 : /* HDMI 1.3+ supports max clock of 340 Mhz */
1185 0 : if (mode->clock > 340000)
1186 : return MODE_CLOCK_HIGH;
1187 : else
1188 0 : return MODE_OK;
1189 : } else {
1190 : return MODE_CLOCK_HIGH;
1191 : }
1192 : }
1193 :
1194 : /* check against the max pixel clock */
1195 0 : if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1196 : return MODE_CLOCK_HIGH;
1197 :
1198 0 : return MODE_OK;
1199 : }
1200 :
1201 : static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1202 : .get_modes = amdgpu_connector_vga_get_modes,
1203 : .mode_valid = amdgpu_connector_dvi_mode_valid,
1204 : .best_encoder = amdgpu_connector_dvi_encoder,
1205 : };
1206 :
1207 : static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1208 : .dpms = drm_helper_connector_dpms,
1209 : .detect = amdgpu_connector_dvi_detect,
1210 : .fill_modes = drm_helper_probe_single_connector_modes,
1211 : .set_property = amdgpu_connector_set_property,
1212 : .early_unregister = amdgpu_connector_unregister,
1213 : .destroy = amdgpu_connector_destroy,
1214 : .force = amdgpu_connector_dvi_force,
1215 : };
1216 :
1217 0 : static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1218 : {
1219 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1220 0 : struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1221 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1222 : int ret;
1223 :
1224 0 : if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1225 : (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1226 : struct drm_display_mode *mode;
1227 :
1228 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1229 0 : if (!amdgpu_dig_connector->edp_on)
1230 0 : amdgpu_atombios_encoder_set_edp_panel_power(connector,
1231 : ATOM_TRANSMITTER_ACTION_POWER_ON);
1232 0 : amdgpu_connector_get_edid(connector);
1233 0 : ret = amdgpu_connector_ddc_get_modes(connector);
1234 0 : if (!amdgpu_dig_connector->edp_on)
1235 0 : amdgpu_atombios_encoder_set_edp_panel_power(connector,
1236 : ATOM_TRANSMITTER_ACTION_POWER_OFF);
1237 : } else {
1238 : /* need to setup ddc on the bridge */
1239 0 : if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1240 : ENCODER_OBJECT_ID_NONE) {
1241 0 : if (encoder)
1242 0 : amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1243 : }
1244 0 : amdgpu_connector_get_edid(connector);
1245 0 : ret = amdgpu_connector_ddc_get_modes(connector);
1246 : }
1247 :
1248 0 : if (ret > 0) {
1249 0 : if (encoder) {
1250 0 : amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1251 : /* add scaled modes */
1252 0 : amdgpu_connector_add_common_modes(encoder, connector);
1253 : }
1254 : return ret;
1255 : }
1256 :
1257 0 : if (!encoder)
1258 : return 0;
1259 :
1260 : /* we have no EDID modes */
1261 0 : mode = amdgpu_connector_lcd_native_mode(encoder);
1262 0 : if (mode) {
1263 0 : ret = 1;
1264 0 : drm_mode_probed_add(connector, mode);
1265 : /* add the width/height from vbios tables if available */
1266 0 : connector->display_info.width_mm = mode->width_mm;
1267 0 : connector->display_info.height_mm = mode->height_mm;
1268 : /* add scaled modes */
1269 0 : amdgpu_connector_add_common_modes(encoder, connector);
1270 : }
1271 : } else {
1272 : /* need to setup ddc on the bridge */
1273 0 : if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1274 : ENCODER_OBJECT_ID_NONE) {
1275 0 : if (encoder)
1276 0 : amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1277 : }
1278 0 : amdgpu_connector_get_edid(connector);
1279 0 : ret = amdgpu_connector_ddc_get_modes(connector);
1280 :
1281 0 : amdgpu_get_native_mode(connector);
1282 : }
1283 :
1284 : return ret;
1285 : }
1286 :
1287 0 : u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1288 : {
1289 : struct drm_encoder *encoder;
1290 : struct amdgpu_encoder *amdgpu_encoder;
1291 :
1292 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
1293 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
1294 :
1295 0 : switch (amdgpu_encoder->encoder_id) {
1296 : case ENCODER_OBJECT_ID_TRAVIS:
1297 : case ENCODER_OBJECT_ID_NUTMEG:
1298 0 : return amdgpu_encoder->encoder_id;
1299 : default:
1300 : break;
1301 : }
1302 : }
1303 :
1304 : return ENCODER_OBJECT_ID_NONE;
1305 : }
1306 :
1307 : static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1308 : {
1309 : struct drm_encoder *encoder;
1310 : struct amdgpu_encoder *amdgpu_encoder;
1311 0 : bool found = false;
1312 :
1313 0 : drm_connector_for_each_possible_encoder(connector, encoder) {
1314 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
1315 0 : if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1316 0 : found = true;
1317 : }
1318 :
1319 : return found;
1320 : }
1321 :
1322 0 : bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1323 : {
1324 0 : struct drm_device *dev = connector->dev;
1325 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1326 :
1327 0 : if ((adev->clock.default_dispclk >= 53900) &&
1328 0 : amdgpu_connector_encoder_is_hbr2(connector)) {
1329 : return true;
1330 : }
1331 :
1332 : return false;
1333 : }
1334 :
1335 : static enum drm_connector_status
1336 0 : amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1337 : {
1338 0 : struct drm_device *dev = connector->dev;
1339 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1340 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1341 0 : enum drm_connector_status ret = connector_status_disconnected;
1342 0 : struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1343 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1344 : int r;
1345 :
1346 0 : if (!drm_kms_helper_is_poll_worker()) {
1347 0 : r = pm_runtime_get_sync(connector->dev->dev);
1348 0 : if (r < 0) {
1349 0 : pm_runtime_put_autosuspend(connector->dev->dev);
1350 0 : return connector_status_disconnected;
1351 : }
1352 : }
1353 :
1354 0 : if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1355 0 : ret = connector->status;
1356 0 : goto out;
1357 : }
1358 :
1359 0 : amdgpu_connector_free_edid(connector);
1360 :
1361 0 : if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1362 : (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1363 0 : if (encoder) {
1364 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1365 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1366 :
1367 : /* check if panel is valid */
1368 0 : if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1369 0 : ret = connector_status_connected;
1370 : }
1371 : /* eDP is always DP */
1372 0 : amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1373 0 : if (!amdgpu_dig_connector->edp_on)
1374 0 : amdgpu_atombios_encoder_set_edp_panel_power(connector,
1375 : ATOM_TRANSMITTER_ACTION_POWER_ON);
1376 0 : if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1377 0 : ret = connector_status_connected;
1378 0 : if (!amdgpu_dig_connector->edp_on)
1379 0 : amdgpu_atombios_encoder_set_edp_panel_power(connector,
1380 : ATOM_TRANSMITTER_ACTION_POWER_OFF);
1381 0 : } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1382 : ENCODER_OBJECT_ID_NONE) {
1383 : /* DP bridges are always DP */
1384 0 : amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1385 : /* get the DPCD from the bridge */
1386 0 : amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1387 :
1388 0 : if (encoder) {
1389 : /* setup ddc on the bridge */
1390 0 : amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1391 : /* bridge chips are always aux */
1392 : /* try DDC */
1393 0 : if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1394 : ret = connector_status_connected;
1395 0 : else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1396 0 : const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1397 0 : ret = encoder_funcs->detect(encoder, connector);
1398 : }
1399 : }
1400 : } else {
1401 0 : amdgpu_dig_connector->dp_sink_type =
1402 0 : amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1403 0 : if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1404 0 : ret = connector_status_connected;
1405 0 : if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1406 0 : amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1407 : } else {
1408 0 : if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1409 0 : if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1410 0 : ret = connector_status_connected;
1411 : } else {
1412 : /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1413 0 : if (amdgpu_display_ddc_probe(amdgpu_connector,
1414 : false))
1415 0 : ret = connector_status_connected;
1416 : }
1417 : }
1418 : }
1419 :
1420 0 : amdgpu_connector_update_scratch_regs(connector, ret);
1421 : out:
1422 0 : if (!drm_kms_helper_is_poll_worker()) {
1423 0 : pm_runtime_mark_last_busy(connector->dev->dev);
1424 0 : pm_runtime_put_autosuspend(connector->dev->dev);
1425 : }
1426 :
1427 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1428 : connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1429 0 : drm_dp_set_subconnector_property(&amdgpu_connector->base,
1430 : ret,
1431 0 : amdgpu_dig_connector->dpcd,
1432 0 : amdgpu_dig_connector->downstream_ports);
1433 : return ret;
1434 : }
1435 :
1436 0 : static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1437 : struct drm_display_mode *mode)
1438 : {
1439 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1440 0 : struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1441 :
1442 : /* XXX check mode bandwidth */
1443 :
1444 0 : if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1445 : (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1446 0 : struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1447 :
1448 0 : if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1449 : return MODE_PANEL;
1450 :
1451 0 : if (encoder) {
1452 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1453 0 : struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1454 :
1455 : /* AVIVO hardware supports downscaling modes larger than the panel
1456 : * to the panel size, but I'm not sure this is desirable.
1457 : */
1458 0 : if ((mode->hdisplay > native_mode->hdisplay) ||
1459 0 : (mode->vdisplay > native_mode->vdisplay))
1460 : return MODE_PANEL;
1461 :
1462 : /* if scaling is disabled, block non-native modes */
1463 0 : if (amdgpu_encoder->rmx_type == RMX_OFF) {
1464 0 : if ((mode->hdisplay != native_mode->hdisplay) ||
1465 : (mode->vdisplay != native_mode->vdisplay))
1466 : return MODE_PANEL;
1467 : }
1468 : }
1469 0 : return MODE_OK;
1470 : } else {
1471 0 : if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1472 : (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1473 0 : return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1474 : } else {
1475 0 : if (connector->display_info.is_hdmi) {
1476 : /* HDMI 1.3+ supports max clock of 340 Mhz */
1477 0 : if (mode->clock > 340000)
1478 : return MODE_CLOCK_HIGH;
1479 : } else {
1480 0 : if (mode->clock > 165000)
1481 : return MODE_CLOCK_HIGH;
1482 : }
1483 : }
1484 : }
1485 :
1486 0 : return MODE_OK;
1487 : }
1488 :
1489 : static int
1490 0 : amdgpu_connector_late_register(struct drm_connector *connector)
1491 : {
1492 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1493 0 : int r = 0;
1494 :
1495 0 : if (amdgpu_connector->ddc_bus->has_aux) {
1496 0 : amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1497 0 : r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1498 : }
1499 :
1500 0 : return r;
1501 : }
1502 :
1503 : static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1504 : .get_modes = amdgpu_connector_dp_get_modes,
1505 : .mode_valid = amdgpu_connector_dp_mode_valid,
1506 : .best_encoder = amdgpu_connector_dvi_encoder,
1507 : };
1508 :
1509 : static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1510 : .dpms = drm_helper_connector_dpms,
1511 : .detect = amdgpu_connector_dp_detect,
1512 : .fill_modes = drm_helper_probe_single_connector_modes,
1513 : .set_property = amdgpu_connector_set_property,
1514 : .early_unregister = amdgpu_connector_unregister,
1515 : .destroy = amdgpu_connector_destroy,
1516 : .force = amdgpu_connector_dvi_force,
1517 : .late_register = amdgpu_connector_late_register,
1518 : };
1519 :
1520 : static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1521 : .dpms = drm_helper_connector_dpms,
1522 : .detect = amdgpu_connector_dp_detect,
1523 : .fill_modes = drm_helper_probe_single_connector_modes,
1524 : .set_property = amdgpu_connector_set_lcd_property,
1525 : .early_unregister = amdgpu_connector_unregister,
1526 : .destroy = amdgpu_connector_destroy,
1527 : .force = amdgpu_connector_dvi_force,
1528 : .late_register = amdgpu_connector_late_register,
1529 : };
1530 :
1531 : void
1532 0 : amdgpu_connector_add(struct amdgpu_device *adev,
1533 : uint32_t connector_id,
1534 : uint32_t supported_device,
1535 : int connector_type,
1536 : struct amdgpu_i2c_bus_rec *i2c_bus,
1537 : uint16_t connector_object_id,
1538 : struct amdgpu_hpd *hpd,
1539 : struct amdgpu_router *router)
1540 : {
1541 0 : struct drm_device *dev = adev_to_drm(adev);
1542 : struct drm_connector *connector;
1543 : struct drm_connector_list_iter iter;
1544 : struct amdgpu_connector *amdgpu_connector;
1545 : struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1546 : struct drm_encoder *encoder;
1547 : struct amdgpu_encoder *amdgpu_encoder;
1548 0 : struct i2c_adapter *ddc = NULL;
1549 0 : uint32_t subpixel_order = SubPixelNone;
1550 0 : bool shared_ddc = false;
1551 0 : bool is_dp_bridge = false;
1552 0 : bool has_aux = false;
1553 :
1554 0 : if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1555 0 : return;
1556 :
1557 : /* see if we already added it */
1558 0 : drm_connector_list_iter_begin(dev, &iter);
1559 0 : drm_for_each_connector_iter(connector, &iter) {
1560 0 : amdgpu_connector = to_amdgpu_connector(connector);
1561 0 : if (amdgpu_connector->connector_id == connector_id) {
1562 0 : amdgpu_connector->devices |= supported_device;
1563 0 : drm_connector_list_iter_end(&iter);
1564 0 : return;
1565 : }
1566 0 : if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1567 0 : if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1568 0 : amdgpu_connector->shared_ddc = true;
1569 0 : shared_ddc = true;
1570 : }
1571 0 : if (amdgpu_connector->router_bus && router->ddc_valid &&
1572 0 : (amdgpu_connector->router.router_id == router->router_id)) {
1573 0 : amdgpu_connector->shared_ddc = false;
1574 0 : shared_ddc = false;
1575 : }
1576 : }
1577 : }
1578 0 : drm_connector_list_iter_end(&iter);
1579 :
1580 : /* check if it's a dp bridge */
1581 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1582 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
1583 0 : if (amdgpu_encoder->devices & supported_device) {
1584 0 : switch (amdgpu_encoder->encoder_id) {
1585 : case ENCODER_OBJECT_ID_TRAVIS:
1586 : case ENCODER_OBJECT_ID_NUTMEG:
1587 0 : is_dp_bridge = true;
1588 0 : break;
1589 : default:
1590 : break;
1591 : }
1592 : }
1593 : }
1594 :
1595 0 : amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1596 0 : if (!amdgpu_connector)
1597 : return;
1598 :
1599 0 : connector = &amdgpu_connector->base;
1600 :
1601 0 : amdgpu_connector->connector_id = connector_id;
1602 0 : amdgpu_connector->devices = supported_device;
1603 0 : amdgpu_connector->shared_ddc = shared_ddc;
1604 0 : amdgpu_connector->connector_object_id = connector_object_id;
1605 0 : amdgpu_connector->hpd = *hpd;
1606 :
1607 0 : amdgpu_connector->router = *router;
1608 0 : if (router->ddc_valid || router->cd_valid) {
1609 0 : amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1610 0 : if (!amdgpu_connector->router_bus)
1611 0 : DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1612 : }
1613 :
1614 0 : if (is_dp_bridge) {
1615 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1616 0 : if (!amdgpu_dig_connector)
1617 : goto failed;
1618 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1619 0 : if (i2c_bus->valid) {
1620 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1621 0 : if (amdgpu_connector->ddc_bus) {
1622 0 : has_aux = true;
1623 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1624 : } else {
1625 0 : DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1626 : }
1627 : }
1628 : switch (connector_type) {
1629 : case DRM_MODE_CONNECTOR_VGA:
1630 : case DRM_MODE_CONNECTOR_DVIA:
1631 : default:
1632 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1633 : &amdgpu_connector_dp_funcs,
1634 : connector_type,
1635 : ddc);
1636 0 : drm_connector_helper_add(&amdgpu_connector->base,
1637 : &amdgpu_connector_dp_helper_funcs);
1638 0 : connector->interlace_allowed = true;
1639 0 : connector->doublescan_allowed = true;
1640 0 : amdgpu_connector->dac_load_detect = true;
1641 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1642 : adev->mode_info.load_detect_property,
1643 : 1);
1644 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1645 : dev->mode_config.scaling_mode_property,
1646 : DRM_MODE_SCALE_NONE);
1647 0 : break;
1648 : case DRM_MODE_CONNECTOR_DVII:
1649 : case DRM_MODE_CONNECTOR_DVID:
1650 : case DRM_MODE_CONNECTOR_HDMIA:
1651 : case DRM_MODE_CONNECTOR_HDMIB:
1652 : case DRM_MODE_CONNECTOR_DisplayPort:
1653 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1654 : &amdgpu_connector_dp_funcs,
1655 : connector_type,
1656 : ddc);
1657 0 : drm_connector_helper_add(&amdgpu_connector->base,
1658 : &amdgpu_connector_dp_helper_funcs);
1659 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1660 : adev->mode_info.underscan_property,
1661 : UNDERSCAN_OFF);
1662 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1663 : adev->mode_info.underscan_hborder_property,
1664 : 0);
1665 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1666 : adev->mode_info.underscan_vborder_property,
1667 : 0);
1668 :
1669 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1670 : dev->mode_config.scaling_mode_property,
1671 : DRM_MODE_SCALE_NONE);
1672 :
1673 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1674 : adev->mode_info.dither_property,
1675 : AMDGPU_FMT_DITHER_DISABLE);
1676 :
1677 0 : if (amdgpu_audio != 0)
1678 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1679 : adev->mode_info.audio_property,
1680 : AMDGPU_AUDIO_AUTO);
1681 :
1682 0 : subpixel_order = SubPixelHorizontalRGB;
1683 0 : connector->interlace_allowed = true;
1684 0 : if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1685 0 : connector->doublescan_allowed = true;
1686 : else
1687 0 : connector->doublescan_allowed = false;
1688 0 : if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1689 0 : amdgpu_connector->dac_load_detect = true;
1690 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1691 : adev->mode_info.load_detect_property,
1692 : 1);
1693 : }
1694 : break;
1695 : case DRM_MODE_CONNECTOR_LVDS:
1696 : case DRM_MODE_CONNECTOR_eDP:
1697 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1698 : &amdgpu_connector_edp_funcs,
1699 : connector_type,
1700 : ddc);
1701 0 : drm_connector_helper_add(&amdgpu_connector->base,
1702 : &amdgpu_connector_dp_helper_funcs);
1703 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1704 : dev->mode_config.scaling_mode_property,
1705 : DRM_MODE_SCALE_FULLSCREEN);
1706 0 : subpixel_order = SubPixelHorizontalRGB;
1707 0 : connector->interlace_allowed = false;
1708 0 : connector->doublescan_allowed = false;
1709 0 : break;
1710 : }
1711 : } else {
1712 0 : switch (connector_type) {
1713 : case DRM_MODE_CONNECTOR_VGA:
1714 0 : if (i2c_bus->valid) {
1715 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1716 0 : if (!amdgpu_connector->ddc_bus)
1717 0 : DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1718 : else
1719 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1720 : }
1721 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1722 : &amdgpu_connector_vga_funcs,
1723 : connector_type,
1724 : ddc);
1725 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1726 0 : amdgpu_connector->dac_load_detect = true;
1727 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1728 : adev->mode_info.load_detect_property,
1729 : 1);
1730 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1731 : dev->mode_config.scaling_mode_property,
1732 : DRM_MODE_SCALE_NONE);
1733 : /* no HPD on analog connectors */
1734 0 : amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1735 0 : connector->interlace_allowed = true;
1736 0 : connector->doublescan_allowed = true;
1737 0 : break;
1738 : case DRM_MODE_CONNECTOR_DVIA:
1739 0 : if (i2c_bus->valid) {
1740 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1741 0 : if (!amdgpu_connector->ddc_bus)
1742 0 : DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1743 : else
1744 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1745 : }
1746 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1747 : &amdgpu_connector_vga_funcs,
1748 : connector_type,
1749 : ddc);
1750 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1751 0 : amdgpu_connector->dac_load_detect = true;
1752 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1753 : adev->mode_info.load_detect_property,
1754 : 1);
1755 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1756 : dev->mode_config.scaling_mode_property,
1757 : DRM_MODE_SCALE_NONE);
1758 : /* no HPD on analog connectors */
1759 0 : amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1760 0 : connector->interlace_allowed = true;
1761 0 : connector->doublescan_allowed = true;
1762 0 : break;
1763 : case DRM_MODE_CONNECTOR_DVII:
1764 : case DRM_MODE_CONNECTOR_DVID:
1765 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1766 0 : if (!amdgpu_dig_connector)
1767 : goto failed;
1768 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1769 0 : if (i2c_bus->valid) {
1770 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1771 0 : if (!amdgpu_connector->ddc_bus)
1772 0 : DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1773 : else
1774 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1775 : }
1776 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1777 : &amdgpu_connector_dvi_funcs,
1778 : connector_type,
1779 : ddc);
1780 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1781 0 : subpixel_order = SubPixelHorizontalRGB;
1782 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1783 : adev->mode_info.coherent_mode_property,
1784 : 1);
1785 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1786 : adev->mode_info.underscan_property,
1787 : UNDERSCAN_OFF);
1788 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1789 : adev->mode_info.underscan_hborder_property,
1790 : 0);
1791 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1792 : adev->mode_info.underscan_vborder_property,
1793 : 0);
1794 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1795 : dev->mode_config.scaling_mode_property,
1796 : DRM_MODE_SCALE_NONE);
1797 :
1798 0 : if (amdgpu_audio != 0) {
1799 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1800 : adev->mode_info.audio_property,
1801 : AMDGPU_AUDIO_AUTO);
1802 : }
1803 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1804 : adev->mode_info.dither_property,
1805 : AMDGPU_FMT_DITHER_DISABLE);
1806 0 : if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1807 0 : amdgpu_connector->dac_load_detect = true;
1808 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1809 : adev->mode_info.load_detect_property,
1810 : 1);
1811 : }
1812 0 : connector->interlace_allowed = true;
1813 0 : if (connector_type == DRM_MODE_CONNECTOR_DVII)
1814 0 : connector->doublescan_allowed = true;
1815 : else
1816 0 : connector->doublescan_allowed = false;
1817 : break;
1818 : case DRM_MODE_CONNECTOR_HDMIA:
1819 : case DRM_MODE_CONNECTOR_HDMIB:
1820 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1821 0 : if (!amdgpu_dig_connector)
1822 : goto failed;
1823 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1824 0 : if (i2c_bus->valid) {
1825 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1826 0 : if (!amdgpu_connector->ddc_bus)
1827 0 : DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1828 : else
1829 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1830 : }
1831 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1832 : &amdgpu_connector_dvi_funcs,
1833 : connector_type,
1834 : ddc);
1835 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1836 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1837 : adev->mode_info.coherent_mode_property,
1838 : 1);
1839 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1840 : adev->mode_info.underscan_property,
1841 : UNDERSCAN_OFF);
1842 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1843 : adev->mode_info.underscan_hborder_property,
1844 : 0);
1845 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1846 : adev->mode_info.underscan_vborder_property,
1847 : 0);
1848 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1849 : dev->mode_config.scaling_mode_property,
1850 : DRM_MODE_SCALE_NONE);
1851 0 : if (amdgpu_audio != 0) {
1852 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1853 : adev->mode_info.audio_property,
1854 : AMDGPU_AUDIO_AUTO);
1855 : }
1856 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1857 : adev->mode_info.dither_property,
1858 : AMDGPU_FMT_DITHER_DISABLE);
1859 0 : subpixel_order = SubPixelHorizontalRGB;
1860 0 : connector->interlace_allowed = true;
1861 0 : if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1862 0 : connector->doublescan_allowed = true;
1863 : else
1864 0 : connector->doublescan_allowed = false;
1865 : break;
1866 : case DRM_MODE_CONNECTOR_DisplayPort:
1867 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1868 0 : if (!amdgpu_dig_connector)
1869 : goto failed;
1870 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1871 0 : if (i2c_bus->valid) {
1872 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1873 0 : if (amdgpu_connector->ddc_bus) {
1874 0 : has_aux = true;
1875 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1876 : } else {
1877 0 : DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1878 : }
1879 : }
1880 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1881 : &amdgpu_connector_dp_funcs,
1882 : connector_type,
1883 : ddc);
1884 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1885 0 : subpixel_order = SubPixelHorizontalRGB;
1886 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1887 : adev->mode_info.coherent_mode_property,
1888 : 1);
1889 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1890 : adev->mode_info.underscan_property,
1891 : UNDERSCAN_OFF);
1892 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1893 : adev->mode_info.underscan_hborder_property,
1894 : 0);
1895 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1896 : adev->mode_info.underscan_vborder_property,
1897 : 0);
1898 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1899 : dev->mode_config.scaling_mode_property,
1900 : DRM_MODE_SCALE_NONE);
1901 0 : if (amdgpu_audio != 0) {
1902 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1903 : adev->mode_info.audio_property,
1904 : AMDGPU_AUDIO_AUTO);
1905 : }
1906 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1907 : adev->mode_info.dither_property,
1908 : AMDGPU_FMT_DITHER_DISABLE);
1909 0 : connector->interlace_allowed = true;
1910 : /* in theory with a DP to VGA converter... */
1911 0 : connector->doublescan_allowed = false;
1912 0 : break;
1913 : case DRM_MODE_CONNECTOR_eDP:
1914 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1915 0 : if (!amdgpu_dig_connector)
1916 : goto failed;
1917 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1918 0 : if (i2c_bus->valid) {
1919 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1920 0 : if (amdgpu_connector->ddc_bus) {
1921 0 : has_aux = true;
1922 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1923 : } else {
1924 0 : DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1925 : }
1926 : }
1927 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1928 : &amdgpu_connector_edp_funcs,
1929 : connector_type,
1930 : ddc);
1931 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1932 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1933 : dev->mode_config.scaling_mode_property,
1934 : DRM_MODE_SCALE_FULLSCREEN);
1935 0 : subpixel_order = SubPixelHorizontalRGB;
1936 0 : connector->interlace_allowed = false;
1937 0 : connector->doublescan_allowed = false;
1938 0 : break;
1939 : case DRM_MODE_CONNECTOR_LVDS:
1940 0 : amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1941 0 : if (!amdgpu_dig_connector)
1942 : goto failed;
1943 0 : amdgpu_connector->con_priv = amdgpu_dig_connector;
1944 0 : if (i2c_bus->valid) {
1945 0 : amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1946 0 : if (!amdgpu_connector->ddc_bus)
1947 0 : DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1948 : else
1949 0 : ddc = &amdgpu_connector->ddc_bus->adapter;
1950 : }
1951 0 : drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1952 : &amdgpu_connector_lvds_funcs,
1953 : connector_type,
1954 : ddc);
1955 0 : drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1956 0 : drm_object_attach_property(&amdgpu_connector->base.base,
1957 : dev->mode_config.scaling_mode_property,
1958 : DRM_MODE_SCALE_FULLSCREEN);
1959 0 : subpixel_order = SubPixelHorizontalRGB;
1960 0 : connector->interlace_allowed = false;
1961 0 : connector->doublescan_allowed = false;
1962 0 : break;
1963 : }
1964 : }
1965 :
1966 0 : if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1967 0 : if (i2c_bus->valid) {
1968 0 : connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1969 : DRM_CONNECTOR_POLL_DISCONNECT;
1970 : }
1971 : } else
1972 0 : connector->polled = DRM_CONNECTOR_POLL_HPD;
1973 :
1974 0 : connector->display_info.subpixel_order = subpixel_order;
1975 :
1976 0 : if (has_aux)
1977 0 : amdgpu_atombios_dp_aux_init(amdgpu_connector);
1978 :
1979 0 : if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1980 0 : connector_type == DRM_MODE_CONNECTOR_eDP) {
1981 0 : drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
1982 : }
1983 :
1984 : return;
1985 :
1986 : failed:
1987 0 : drm_connector_cleanup(connector);
1988 0 : kfree(connector);
1989 : }
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