Line data Source code
1 : /*
2 : * Copyright 2007-8 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: Dave Airlie
24 : * Alex Deucher
25 : */
26 :
27 : #include <drm/amdgpu_drm.h>
28 : #include "amdgpu.h"
29 : #include "amdgpu_i2c.h"
30 : #include "atom.h"
31 : #include "amdgpu_connectors.h"
32 : #include "amdgpu_display.h"
33 : #include "soc15_common.h"
34 : #include "gc/gc_11_0_0_offset.h"
35 : #include "gc/gc_11_0_0_sh_mask.h"
36 : #include <asm/div64.h>
37 :
38 : #include <linux/pci.h>
39 : #include <linux/pm_runtime.h>
40 : #include <drm/drm_crtc_helper.h>
41 : #include <drm/drm_damage_helper.h>
42 : #include <drm/drm_edid.h>
43 : #include <drm/drm_gem_framebuffer_helper.h>
44 : #include <drm/drm_fb_helper.h>
45 : #include <drm/drm_fourcc.h>
46 : #include <drm/drm_vblank.h>
47 :
48 : static int amdgpu_display_framebuffer_init(struct drm_device *dev,
49 : struct amdgpu_framebuffer *rfb,
50 : const struct drm_mode_fb_cmd2 *mode_cmd,
51 : struct drm_gem_object *obj);
52 :
53 0 : static void amdgpu_display_flip_callback(struct dma_fence *f,
54 : struct dma_fence_cb *cb)
55 : {
56 0 : struct amdgpu_flip_work *work =
57 0 : container_of(cb, struct amdgpu_flip_work, cb);
58 :
59 0 : dma_fence_put(f);
60 0 : schedule_work(&work->flip_work.work);
61 0 : }
62 :
63 0 : static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
64 : struct dma_fence **f)
65 : {
66 0 : struct dma_fence *fence= *f;
67 :
68 0 : if (fence == NULL)
69 : return false;
70 :
71 0 : *f = NULL;
72 :
73 0 : if (!dma_fence_add_callback(fence, &work->cb,
74 : amdgpu_display_flip_callback))
75 : return true;
76 :
77 0 : dma_fence_put(fence);
78 0 : return false;
79 : }
80 :
81 0 : static void amdgpu_display_flip_work_func(struct work_struct *__work)
82 : {
83 0 : struct delayed_work *delayed_work =
84 0 : container_of(__work, struct delayed_work, work);
85 0 : struct amdgpu_flip_work *work =
86 0 : container_of(delayed_work, struct amdgpu_flip_work, flip_work);
87 0 : struct amdgpu_device *adev = work->adev;
88 0 : struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
89 :
90 0 : struct drm_crtc *crtc = &amdgpu_crtc->base;
91 : unsigned long flags;
92 : unsigned i;
93 : int vpos, hpos;
94 :
95 0 : for (i = 0; i < work->shared_count; ++i)
96 0 : if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
97 0 : return;
98 :
99 : /* Wait until we're out of the vertical blank period before the one
100 : * targeted by the flip
101 : */
102 0 : if (amdgpu_crtc->enabled &&
103 0 : (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
104 : &vpos, &hpos, NULL, NULL,
105 0 : &crtc->hwmode)
106 0 : & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
107 0 : (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
108 0 : (int)(work->target_vblank -
109 0 : amdgpu_get_vblank_counter_kms(crtc)) > 0) {
110 0 : schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
111 : return;
112 : }
113 :
114 : /* We borrow the event spin lock for protecting flip_status */
115 0 : spin_lock_irqsave(&crtc->dev->event_lock, flags);
116 :
117 : /* Do the flip (mmio) */
118 0 : adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
119 :
120 : /* Set the flip status */
121 0 : amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
122 0 : spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
123 :
124 :
125 0 : drm_dbg_vbl(adev_to_drm(adev),
126 : "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
127 : amdgpu_crtc->crtc_id, amdgpu_crtc, work);
128 :
129 : }
130 :
131 : /*
132 : * Handle unpin events outside the interrupt handler proper.
133 : */
134 0 : static void amdgpu_display_unpin_work_func(struct work_struct *__work)
135 : {
136 0 : struct amdgpu_flip_work *work =
137 0 : container_of(__work, struct amdgpu_flip_work, unpin_work);
138 : int r;
139 :
140 : /* unpin of the old buffer */
141 0 : r = amdgpu_bo_reserve(work->old_abo, true);
142 0 : if (likely(r == 0)) {
143 0 : amdgpu_bo_unpin(work->old_abo);
144 0 : amdgpu_bo_unreserve(work->old_abo);
145 : } else
146 0 : DRM_ERROR("failed to reserve buffer after flip\n");
147 :
148 0 : amdgpu_bo_unref(&work->old_abo);
149 0 : kfree(work->shared);
150 0 : kfree(work);
151 0 : }
152 :
153 0 : int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
154 : struct drm_framebuffer *fb,
155 : struct drm_pending_vblank_event *event,
156 : uint32_t page_flip_flags, uint32_t target,
157 : struct drm_modeset_acquire_ctx *ctx)
158 : {
159 0 : struct drm_device *dev = crtc->dev;
160 0 : struct amdgpu_device *adev = drm_to_adev(dev);
161 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
162 : struct drm_gem_object *obj;
163 : struct amdgpu_flip_work *work;
164 : struct amdgpu_bo *new_abo;
165 : unsigned long flags;
166 : u64 tiling_flags;
167 : int i, r;
168 :
169 0 : work = kzalloc(sizeof *work, GFP_KERNEL);
170 0 : if (work == NULL)
171 : return -ENOMEM;
172 :
173 0 : INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
174 0 : INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
175 :
176 0 : work->event = event;
177 0 : work->adev = adev;
178 0 : work->crtc_id = amdgpu_crtc->crtc_id;
179 0 : work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
180 :
181 : /* schedule unpin of the old buffer */
182 0 : obj = crtc->primary->fb->obj[0];
183 :
184 : /* take a reference to the old object */
185 0 : work->old_abo = gem_to_amdgpu_bo(obj);
186 0 : amdgpu_bo_ref(work->old_abo);
187 :
188 0 : obj = fb->obj[0];
189 0 : new_abo = gem_to_amdgpu_bo(obj);
190 :
191 : /* pin the new buffer */
192 0 : r = amdgpu_bo_reserve(new_abo, false);
193 0 : if (unlikely(r != 0)) {
194 0 : DRM_ERROR("failed to reserve new abo buffer before flip\n");
195 0 : goto cleanup;
196 : }
197 :
198 0 : if (!adev->enable_virtual_display) {
199 0 : r = amdgpu_bo_pin(new_abo,
200 : amdgpu_display_supported_domains(adev, new_abo->flags));
201 0 : if (unlikely(r != 0)) {
202 0 : DRM_ERROR("failed to pin new abo buffer before flip\n");
203 0 : goto unreserve;
204 : }
205 : }
206 :
207 0 : r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
208 0 : if (unlikely(r != 0)) {
209 0 : DRM_ERROR("%p bind failed\n", new_abo);
210 0 : goto unpin;
211 : }
212 :
213 0 : r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
214 : &work->shared_count,
215 : &work->shared);
216 0 : if (unlikely(r != 0)) {
217 0 : DRM_ERROR("failed to get fences for buffer\n");
218 0 : goto unpin;
219 : }
220 :
221 0 : amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
222 0 : amdgpu_bo_unreserve(new_abo);
223 :
224 0 : if (!adev->enable_virtual_display)
225 0 : work->base = amdgpu_bo_gpu_offset(new_abo);
226 0 : work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
227 0 : amdgpu_get_vblank_counter_kms(crtc);
228 :
229 : /* we borrow the event spin lock for protecting flip_wrok */
230 0 : spin_lock_irqsave(&crtc->dev->event_lock, flags);
231 0 : if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
232 0 : DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
233 0 : spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
234 0 : r = -EBUSY;
235 : goto pflip_cleanup;
236 : }
237 :
238 0 : amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
239 0 : amdgpu_crtc->pflip_works = work;
240 :
241 :
242 0 : DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
243 : amdgpu_crtc->crtc_id, amdgpu_crtc, work);
244 : /* update crtc fb */
245 0 : crtc->primary->fb = fb;
246 0 : spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
247 0 : amdgpu_display_flip_work_func(&work->flip_work.work);
248 0 : return 0;
249 :
250 : pflip_cleanup:
251 0 : if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
252 0 : DRM_ERROR("failed to reserve new abo in error path\n");
253 0 : goto cleanup;
254 : }
255 : unpin:
256 0 : if (!adev->enable_virtual_display)
257 0 : amdgpu_bo_unpin(new_abo);
258 :
259 : unreserve:
260 : amdgpu_bo_unreserve(new_abo);
261 :
262 : cleanup:
263 0 : amdgpu_bo_unref(&work->old_abo);
264 0 : for (i = 0; i < work->shared_count; ++i)
265 0 : dma_fence_put(work->shared[i]);
266 0 : kfree(work->shared);
267 0 : kfree(work);
268 :
269 0 : return r;
270 : }
271 :
272 0 : int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
273 : struct drm_modeset_acquire_ctx *ctx)
274 : {
275 : struct drm_device *dev;
276 : struct amdgpu_device *adev;
277 : struct drm_crtc *crtc;
278 0 : bool active = false;
279 : int ret;
280 :
281 0 : if (!set || !set->crtc)
282 : return -EINVAL;
283 :
284 0 : dev = set->crtc->dev;
285 :
286 0 : ret = pm_runtime_get_sync(dev->dev);
287 0 : if (ret < 0)
288 : goto out;
289 :
290 0 : ret = drm_crtc_helper_set_config(set, ctx);
291 :
292 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
293 0 : if (crtc->enabled)
294 0 : active = true;
295 :
296 0 : pm_runtime_mark_last_busy(dev->dev);
297 :
298 0 : adev = drm_to_adev(dev);
299 : /* if we have active crtcs and we don't have a power ref,
300 : take the current one */
301 0 : if (active && !adev->have_disp_power_ref) {
302 0 : adev->have_disp_power_ref = true;
303 0 : return ret;
304 : }
305 : /* if we have no active crtcs, then drop the power ref
306 : we got before */
307 0 : if (!active && adev->have_disp_power_ref) {
308 0 : pm_runtime_put_autosuspend(dev->dev);
309 0 : adev->have_disp_power_ref = false;
310 : }
311 :
312 : out:
313 : /* drop the power reference we got coming in here */
314 0 : pm_runtime_put_autosuspend(dev->dev);
315 0 : return ret;
316 : }
317 :
318 : static const char *encoder_names[41] = {
319 : "NONE",
320 : "INTERNAL_LVDS",
321 : "INTERNAL_TMDS1",
322 : "INTERNAL_TMDS2",
323 : "INTERNAL_DAC1",
324 : "INTERNAL_DAC2",
325 : "INTERNAL_SDVOA",
326 : "INTERNAL_SDVOB",
327 : "SI170B",
328 : "CH7303",
329 : "CH7301",
330 : "INTERNAL_DVO1",
331 : "EXTERNAL_SDVOA",
332 : "EXTERNAL_SDVOB",
333 : "TITFP513",
334 : "INTERNAL_LVTM1",
335 : "VT1623",
336 : "HDMI_SI1930",
337 : "HDMI_INTERNAL",
338 : "INTERNAL_KLDSCP_TMDS1",
339 : "INTERNAL_KLDSCP_DVO1",
340 : "INTERNAL_KLDSCP_DAC1",
341 : "INTERNAL_KLDSCP_DAC2",
342 : "SI178",
343 : "MVPU_FPGA",
344 : "INTERNAL_DDI",
345 : "VT1625",
346 : "HDMI_SI1932",
347 : "DP_AN9801",
348 : "DP_DP501",
349 : "INTERNAL_UNIPHY",
350 : "INTERNAL_KLDSCP_LVTMA",
351 : "INTERNAL_UNIPHY1",
352 : "INTERNAL_UNIPHY2",
353 : "NUTMEG",
354 : "TRAVIS",
355 : "INTERNAL_VCE",
356 : "INTERNAL_UNIPHY3",
357 : "HDMI_ANX9805",
358 : "INTERNAL_AMCLK",
359 : "VIRTUAL",
360 : };
361 :
362 : static const char *hpd_names[6] = {
363 : "HPD1",
364 : "HPD2",
365 : "HPD3",
366 : "HPD4",
367 : "HPD5",
368 : "HPD6",
369 : };
370 :
371 0 : void amdgpu_display_print_display_setup(struct drm_device *dev)
372 : {
373 : struct drm_connector *connector;
374 : struct amdgpu_connector *amdgpu_connector;
375 : struct drm_encoder *encoder;
376 : struct amdgpu_encoder *amdgpu_encoder;
377 : struct drm_connector_list_iter iter;
378 : uint32_t devices;
379 0 : int i = 0;
380 :
381 0 : drm_connector_list_iter_begin(dev, &iter);
382 0 : DRM_INFO("AMDGPU Display Connectors\n");
383 0 : drm_for_each_connector_iter(connector, &iter) {
384 0 : amdgpu_connector = to_amdgpu_connector(connector);
385 0 : DRM_INFO("Connector %d:\n", i);
386 0 : DRM_INFO(" %s\n", connector->name);
387 0 : if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
388 0 : DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
389 0 : if (amdgpu_connector->ddc_bus) {
390 0 : DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
391 : amdgpu_connector->ddc_bus->rec.mask_clk_reg,
392 : amdgpu_connector->ddc_bus->rec.mask_data_reg,
393 : amdgpu_connector->ddc_bus->rec.a_clk_reg,
394 : amdgpu_connector->ddc_bus->rec.a_data_reg,
395 : amdgpu_connector->ddc_bus->rec.en_clk_reg,
396 : amdgpu_connector->ddc_bus->rec.en_data_reg,
397 : amdgpu_connector->ddc_bus->rec.y_clk_reg,
398 : amdgpu_connector->ddc_bus->rec.y_data_reg);
399 0 : if (amdgpu_connector->router.ddc_valid)
400 0 : DRM_INFO(" DDC Router 0x%x/0x%x\n",
401 : amdgpu_connector->router.ddc_mux_control_pin,
402 : amdgpu_connector->router.ddc_mux_state);
403 0 : if (amdgpu_connector->router.cd_valid)
404 0 : DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
405 : amdgpu_connector->router.cd_mux_control_pin,
406 : amdgpu_connector->router.cd_mux_state);
407 : } else {
408 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
409 : connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
410 : connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
411 0 : connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
412 0 : connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
413 : connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
414 0 : DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
415 : }
416 0 : DRM_INFO(" Encoders:\n");
417 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
418 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
419 0 : devices = amdgpu_encoder->devices & amdgpu_connector->devices;
420 0 : if (devices) {
421 0 : if (devices & ATOM_DEVICE_CRT1_SUPPORT)
422 0 : DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
423 0 : if (devices & ATOM_DEVICE_CRT2_SUPPORT)
424 0 : DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
425 0 : if (devices & ATOM_DEVICE_LCD1_SUPPORT)
426 0 : DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
427 0 : if (devices & ATOM_DEVICE_DFP1_SUPPORT)
428 0 : DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
429 0 : if (devices & ATOM_DEVICE_DFP2_SUPPORT)
430 0 : DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
431 0 : if (devices & ATOM_DEVICE_DFP3_SUPPORT)
432 0 : DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
433 0 : if (devices & ATOM_DEVICE_DFP4_SUPPORT)
434 0 : DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
435 0 : if (devices & ATOM_DEVICE_DFP5_SUPPORT)
436 0 : DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
437 0 : if (devices & ATOM_DEVICE_DFP6_SUPPORT)
438 0 : DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
439 0 : if (devices & ATOM_DEVICE_TV1_SUPPORT)
440 0 : DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
441 0 : if (devices & ATOM_DEVICE_CV_SUPPORT)
442 0 : DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
443 : }
444 : }
445 0 : i++;
446 : }
447 0 : drm_connector_list_iter_end(&iter);
448 0 : }
449 :
450 0 : bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
451 : bool use_aux)
452 : {
453 0 : u8 out = 0x0;
454 : u8 buf[8];
455 : int ret;
456 0 : struct i2c_msg msgs[] = {
457 : {
458 : .addr = DDC_ADDR,
459 : .flags = 0,
460 : .len = 1,
461 : .buf = &out,
462 : },
463 : {
464 : .addr = DDC_ADDR,
465 : .flags = I2C_M_RD,
466 : .len = 8,
467 : .buf = buf,
468 : }
469 : };
470 :
471 : /* on hw with routers, select right port */
472 0 : if (amdgpu_connector->router.ddc_valid)
473 0 : amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
474 :
475 0 : if (use_aux) {
476 0 : ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
477 : } else {
478 0 : ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
479 : }
480 :
481 0 : if (ret != 2)
482 : /* Couldn't find an accessible DDC on this connector */
483 : return false;
484 : /* Probe also for valid EDID header
485 : * EDID header starts with:
486 : * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
487 : * Only the first 6 bytes must be valid as
488 : * drm_edid_block_valid() can fix the last 2 bytes */
489 0 : if (drm_edid_header_is_valid(buf) < 6) {
490 : /* Couldn't find an accessible EDID on this
491 : * connector */
492 : return false;
493 : }
494 0 : return true;
495 : }
496 :
497 : static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
498 : .destroy = drm_gem_fb_destroy,
499 : .create_handle = drm_gem_fb_create_handle,
500 : .dirty = drm_atomic_helper_dirtyfb,
501 : };
502 :
503 0 : uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
504 : uint64_t bo_flags)
505 : {
506 0 : uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
507 :
508 : #if defined(CONFIG_DRM_AMD_DC)
509 : /*
510 : * if amdgpu_bo_support_uswc returns false it means that USWC mappings
511 : * is not supported for this board. But this mapping is required
512 : * to avoid hang caused by placement of scanout BO in GTT on certain
513 : * APUs. So force the BO placement to VRAM in case this architecture
514 : * will not allow USWC mappings.
515 : * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
516 : */
517 0 : if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
518 0 : amdgpu_bo_support_uswc(bo_flags) &&
519 0 : amdgpu_device_asic_has_dc_support(adev->asic_type) &&
520 0 : adev->mode_info.gpu_vm_support)
521 0 : domain |= AMDGPU_GEM_DOMAIN_GTT;
522 : #endif
523 :
524 0 : return domain;
525 : }
526 :
527 : static const struct drm_format_info dcc_formats[] = {
528 : { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
529 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
530 : { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
531 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
532 : { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
533 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
534 : .has_alpha = true, },
535 : { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
536 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
537 : .has_alpha = true, },
538 : { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
539 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
540 : .has_alpha = true, },
541 : { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
542 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
543 : { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
544 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
545 : { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
546 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
547 : .has_alpha = true, },
548 : { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
549 : .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
550 : .has_alpha = true, },
551 : { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
552 : .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
553 : };
554 :
555 : static const struct drm_format_info dcc_retile_formats[] = {
556 : { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
557 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
558 : { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
559 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
560 : { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
561 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
562 : .has_alpha = true, },
563 : { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
564 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
565 : .has_alpha = true, },
566 : { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
567 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
568 : .has_alpha = true, },
569 : { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
570 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
571 : { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
572 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
573 : { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
574 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
575 : .has_alpha = true, },
576 : { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
577 : .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
578 : .has_alpha = true, },
579 : { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
580 : .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
581 : };
582 :
583 : static const struct drm_format_info *
584 : lookup_format_info(const struct drm_format_info formats[],
585 : int num_formats, u32 format)
586 : {
587 : int i;
588 :
589 0 : for (i = 0; i < num_formats; i++) {
590 0 : if (formats[i].format == format)
591 : return &formats[i];
592 : }
593 :
594 : return NULL;
595 : }
596 :
597 : const struct drm_format_info *
598 0 : amdgpu_lookup_format_info(u32 format, uint64_t modifier)
599 : {
600 0 : if (!IS_AMD_FMT_MOD(modifier))
601 : return NULL;
602 :
603 0 : if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
604 : return lookup_format_info(dcc_retile_formats,
605 : ARRAY_SIZE(dcc_retile_formats),
606 : format);
607 :
608 0 : if (AMD_FMT_MOD_GET(DCC, modifier))
609 : return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
610 : format);
611 :
612 : /* returning NULL will cause the default format structs to be used. */
613 : return NULL;
614 : }
615 :
616 :
617 : /*
618 : * Tries to extract the renderable DCC offset from the opaque metadata attached
619 : * to the buffer.
620 : */
621 : static int
622 0 : extract_render_dcc_offset(struct amdgpu_device *adev,
623 : struct drm_gem_object *obj,
624 : uint64_t *offset)
625 : {
626 : struct amdgpu_bo *rbo;
627 0 : int r = 0;
628 : uint32_t metadata[10]; /* Something that fits a descriptor + header. */
629 : uint32_t size;
630 :
631 0 : rbo = gem_to_amdgpu_bo(obj);
632 0 : r = amdgpu_bo_reserve(rbo, false);
633 :
634 0 : if (unlikely(r)) {
635 : /* Don't show error message when returning -ERESTARTSYS */
636 0 : if (r != -ERESTARTSYS)
637 0 : DRM_ERROR("Unable to reserve buffer: %d\n", r);
638 : return r;
639 : }
640 :
641 0 : r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
642 0 : amdgpu_bo_unreserve(rbo);
643 :
644 0 : if (r)
645 : return r;
646 :
647 : /*
648 : * The first word is the metadata version, and we need space for at least
649 : * the version + pci vendor+device id + 8 words for a descriptor.
650 : */
651 0 : if (size < 40 || metadata[0] != 1)
652 : return -EINVAL;
653 :
654 0 : if (adev->family >= AMDGPU_FAMILY_NV) {
655 : /* resource word 6/7 META_DATA_ADDRESS{_LO} */
656 0 : *offset = ((u64)metadata[9] << 16u) |
657 0 : ((metadata[8] & 0xFF000000u) >> 16);
658 : } else {
659 : /* resource word 5/7 META_DATA_ADDRESS */
660 0 : *offset = ((u64)metadata[9] << 8u) |
661 0 : ((u64)(metadata[7] & 0x1FE0000u) << 23);
662 : }
663 :
664 : return 0;
665 : }
666 :
667 0 : static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
668 : {
669 0 : struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
670 0 : uint64_t modifier = 0;
671 0 : int num_pipes = 0;
672 0 : int num_pkrs = 0;
673 :
674 0 : num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
675 0 : num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
676 :
677 0 : if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
678 : modifier = DRM_FORMAT_MOD_LINEAR;
679 : } else {
680 0 : int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
681 0 : bool has_xor = swizzle >= 16;
682 : int block_size_bits;
683 : int version;
684 0 : int pipe_xor_bits = 0;
685 0 : int bank_xor_bits = 0;
686 0 : int packers = 0;
687 0 : int rb = 0;
688 0 : int pipes = ilog2(num_pipes);
689 0 : uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
690 :
691 0 : switch (swizzle >> 2) {
692 : case 0: /* 256B */
693 : block_size_bits = 8;
694 : break;
695 : case 1: /* 4KiB */
696 : case 5: /* 4KiB _X */
697 0 : block_size_bits = 12;
698 0 : break;
699 : case 2: /* 64KiB */
700 : case 4: /* 64 KiB _T */
701 : case 6: /* 64 KiB _X */
702 0 : block_size_bits = 16;
703 0 : break;
704 : case 7: /* 256 KiB */
705 0 : block_size_bits = 18;
706 0 : break;
707 : default:
708 : /* RESERVED or VAR */
709 : return -EINVAL;
710 : }
711 :
712 0 : if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
713 : version = AMD_FMT_MOD_TILE_VER_GFX11;
714 0 : else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
715 : version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
716 0 : else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
717 : version = AMD_FMT_MOD_TILE_VER_GFX10;
718 : else
719 0 : version = AMD_FMT_MOD_TILE_VER_GFX9;
720 :
721 0 : switch (swizzle & 3) {
722 : case 0: /* Z microtiling */
723 : return -EINVAL;
724 : case 1: /* S microtiling */
725 0 : if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
726 0 : if (!has_xor)
727 0 : version = AMD_FMT_MOD_TILE_VER_GFX9;
728 : }
729 : break;
730 : case 2:
731 0 : if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
732 0 : if (!has_xor && afb->base.format->cpp[0] != 4)
733 0 : version = AMD_FMT_MOD_TILE_VER_GFX9;
734 : }
735 : break;
736 : case 3:
737 : break;
738 : }
739 :
740 0 : if (has_xor) {
741 0 : if (num_pipes == num_pkrs && num_pkrs == 0) {
742 0 : DRM_ERROR("invalid number of pipes and packers\n");
743 0 : return -EINVAL;
744 : }
745 :
746 0 : switch (version) {
747 : case AMD_FMT_MOD_TILE_VER_GFX11:
748 0 : pipe_xor_bits = min(block_size_bits - 8, pipes);
749 0 : packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
750 : break;
751 : case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
752 0 : pipe_xor_bits = min(block_size_bits - 8, pipes);
753 0 : packers = min(block_size_bits - 8 - pipe_xor_bits,
754 : ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
755 0 : break;
756 : case AMD_FMT_MOD_TILE_VER_GFX10:
757 0 : pipe_xor_bits = min(block_size_bits - 8, pipes);
758 0 : break;
759 : case AMD_FMT_MOD_TILE_VER_GFX9:
760 0 : rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
761 0 : ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
762 0 : pipe_xor_bits = min(block_size_bits - 8, pipes +
763 : ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
764 0 : bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
765 : ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
766 0 : break;
767 : }
768 : }
769 :
770 0 : modifier = AMD_FMT_MOD |
771 0 : AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
772 0 : AMD_FMT_MOD_SET(TILE_VERSION, version) |
773 0 : AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
774 0 : AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
775 0 : AMD_FMT_MOD_SET(PACKERS, packers);
776 :
777 0 : if (dcc_offset != 0) {
778 0 : bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
779 0 : bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
780 : const struct drm_format_info *format_info;
781 : u64 render_dcc_offset;
782 :
783 : /* Enable constant encode on RAVEN2 and later. */
784 0 : bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
785 0 : (adev->asic_type == CHIP_RAVEN &&
786 0 : adev->external_rev_id >= 0x81)) &&
787 : adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
788 :
789 0 : int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
790 0 : dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
791 : AMD_FMT_MOD_DCC_BLOCK_256B;
792 :
793 0 : modifier |= AMD_FMT_MOD_SET(DCC, 1) |
794 0 : AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
795 0 : AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
796 0 : AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
797 0 : AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
798 :
799 0 : afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
800 0 : afb->base.pitches[1] =
801 0 : AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
802 :
803 : /*
804 : * If the userspace driver uses retiling the tiling flags do not contain
805 : * info on the renderable DCC buffer. Luckily the opaque metadata contains
806 : * the info so we can try to extract it. The kernel does not use this info
807 : * but we should convert it to a modifier plane for getfb2, so the
808 : * userspace driver that gets it doesn't have to juggle around another DCC
809 : * plane internally.
810 : */
811 0 : if (extract_render_dcc_offset(adev, afb->base.obj[0],
812 0 : &render_dcc_offset) == 0 &&
813 0 : render_dcc_offset != 0 &&
814 0 : render_dcc_offset != afb->base.offsets[1] &&
815 : render_dcc_offset < UINT_MAX) {
816 : uint32_t dcc_block_bits; /* of base surface data */
817 :
818 0 : modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
819 0 : afb->base.offsets[2] = render_dcc_offset;
820 :
821 0 : if (adev->family >= AMDGPU_FAMILY_NV) {
822 0 : int extra_pipe = 0;
823 :
824 0 : if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
825 0 : pipes == packers && pipes > 1)
826 0 : extra_pipe = 1;
827 :
828 0 : dcc_block_bits = max(20, 16 + pipes + extra_pipe);
829 : } else {
830 0 : modifier |= AMD_FMT_MOD_SET(RB, rb) |
831 0 : AMD_FMT_MOD_SET(PIPE, pipes);
832 0 : dcc_block_bits = max(20, 18 + rb);
833 : }
834 :
835 0 : dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
836 0 : afb->base.pitches[2] = ALIGN(afb->base.width,
837 : 1u << ((dcc_block_bits + 1) / 2));
838 : }
839 0 : format_info = amdgpu_lookup_format_info(afb->base.format->format,
840 : modifier);
841 0 : if (!format_info)
842 0 : return -EINVAL;
843 :
844 0 : afb->base.format = format_info;
845 : }
846 : }
847 :
848 0 : afb->base.modifier = modifier;
849 0 : afb->base.flags |= DRM_MODE_FB_MODIFIERS;
850 0 : return 0;
851 : }
852 :
853 : /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
854 0 : static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
855 : {
856 : u64 micro_tile_mode;
857 :
858 : /* Zero swizzle mode means linear */
859 0 : if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
860 : return 0;
861 :
862 0 : micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
863 0 : switch (micro_tile_mode) {
864 : case 0: /* DISPLAY */
865 : case 3: /* RENDER */
866 : return 0;
867 : default:
868 0 : drm_dbg_kms(afb->base.dev,
869 : "Micro tile mode %llu not supported for scanout\n",
870 : micro_tile_mode);
871 : return -EINVAL;
872 : }
873 : }
874 :
875 : static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
876 : unsigned int *width, unsigned int *height)
877 : {
878 0 : unsigned int cpp_log2 = ilog2(cpp);
879 0 : unsigned int pixel_log2 = block_log2 - cpp_log2;
880 0 : unsigned int width_log2 = (pixel_log2 + 1) / 2;
881 0 : unsigned int height_log2 = pixel_log2 - width_log2;
882 :
883 0 : *width = 1 << width_log2;
884 0 : *height = 1 << height_log2;
885 : }
886 :
887 0 : static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
888 : bool pipe_aligned)
889 : {
890 0 : unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
891 :
892 0 : switch (ver) {
893 : case AMD_FMT_MOD_TILE_VER_GFX9: {
894 : /*
895 : * TODO: for pipe aligned we may need to check the alignment of the
896 : * total size of the surface, which may need to be bigger than the
897 : * natural alignment due to some HW workarounds
898 : */
899 0 : return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
900 : }
901 : case AMD_FMT_MOD_TILE_VER_GFX10:
902 : case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
903 : case AMD_FMT_MOD_TILE_VER_GFX11: {
904 0 : int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
905 :
906 0 : if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
907 0 : AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
908 0 : ++pipes_log2;
909 :
910 0 : return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
911 : }
912 : default:
913 : return 0;
914 : }
915 : }
916 :
917 0 : static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
918 : const struct drm_format_info *format,
919 : unsigned int block_width, unsigned int block_height,
920 : unsigned int block_size_log2)
921 : {
922 0 : unsigned int width = rfb->base.width /
923 0 : ((plane && plane < format->num_planes) ? format->hsub : 1);
924 0 : unsigned int height = rfb->base.height /
925 0 : ((plane && plane < format->num_planes) ? format->vsub : 1);
926 0 : unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
927 0 : unsigned int block_pitch = block_width * cpp;
928 0 : unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
929 0 : unsigned int block_size = 1 << block_size_log2;
930 : uint64_t size;
931 :
932 0 : if (rfb->base.pitches[plane] % block_pitch) {
933 0 : drm_dbg_kms(rfb->base.dev,
934 : "pitch %d for plane %d is not a multiple of block pitch %d\n",
935 : rfb->base.pitches[plane], plane, block_pitch);
936 0 : return -EINVAL;
937 : }
938 0 : if (rfb->base.pitches[plane] < min_pitch) {
939 0 : drm_dbg_kms(rfb->base.dev,
940 : "pitch %d for plane %d is less than minimum pitch %d\n",
941 : rfb->base.pitches[plane], plane, min_pitch);
942 0 : return -EINVAL;
943 : }
944 :
945 : /* Force at least natural alignment. */
946 0 : if (rfb->base.offsets[plane] % block_size) {
947 0 : drm_dbg_kms(rfb->base.dev,
948 : "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
949 : rfb->base.offsets[plane], plane, block_size);
950 0 : return -EINVAL;
951 : }
952 :
953 0 : size = rfb->base.offsets[plane] +
954 0 : (uint64_t)rfb->base.pitches[plane] / block_pitch *
955 0 : block_size * DIV_ROUND_UP(height, block_height);
956 :
957 0 : if (rfb->base.obj[0]->size < size) {
958 0 : drm_dbg_kms(rfb->base.dev,
959 : "BO size 0x%zx is less than 0x%llx required for plane %d\n",
960 : rfb->base.obj[0]->size, size, plane);
961 0 : return -EINVAL;
962 : }
963 :
964 : return 0;
965 : }
966 :
967 :
968 0 : static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
969 : {
970 0 : const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
971 0 : uint64_t modifier = rfb->base.modifier;
972 : int ret;
973 : unsigned int i, block_width, block_height, block_size_log2;
974 :
975 0 : if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
976 : return 0;
977 :
978 0 : for (i = 0; i < format_info->num_planes; ++i) {
979 0 : if (modifier == DRM_FORMAT_MOD_LINEAR) {
980 0 : block_width = 256 / format_info->cpp[i];
981 0 : block_height = 1;
982 0 : block_size_log2 = 8;
983 : } else {
984 0 : int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
985 :
986 0 : switch ((swizzle & ~3) + 1) {
987 : case DC_SW_256B_S:
988 : block_size_log2 = 8;
989 : break;
990 : case DC_SW_4KB_S:
991 : case DC_SW_4KB_S_X:
992 0 : block_size_log2 = 12;
993 0 : break;
994 : case DC_SW_64KB_S:
995 : case DC_SW_64KB_S_T:
996 : case DC_SW_64KB_S_X:
997 0 : block_size_log2 = 16;
998 0 : break;
999 : case DC_SW_VAR_S_X:
1000 0 : block_size_log2 = 18;
1001 0 : break;
1002 : default:
1003 0 : drm_dbg_kms(rfb->base.dev,
1004 : "Swizzle mode with unknown block size: %d\n", swizzle);
1005 0 : return -EINVAL;
1006 : }
1007 :
1008 0 : get_block_dimensions(block_size_log2, format_info->cpp[i],
1009 : &block_width, &block_height);
1010 : }
1011 :
1012 0 : ret = amdgpu_display_verify_plane(rfb, i, format_info,
1013 : block_width, block_height, block_size_log2);
1014 0 : if (ret)
1015 : return ret;
1016 : }
1017 :
1018 0 : if (AMD_FMT_MOD_GET(DCC, modifier)) {
1019 0 : if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1020 0 : block_size_log2 = get_dcc_block_size(modifier, false, false);
1021 0 : get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1022 : &block_width, &block_height);
1023 0 : ret = amdgpu_display_verify_plane(rfb, i, format_info,
1024 : block_width, block_height,
1025 : block_size_log2);
1026 0 : if (ret)
1027 : return ret;
1028 :
1029 0 : ++i;
1030 0 : block_size_log2 = get_dcc_block_size(modifier, true, true);
1031 : } else {
1032 0 : bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1033 :
1034 0 : block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1035 : }
1036 0 : get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1037 : &block_width, &block_height);
1038 0 : ret = amdgpu_display_verify_plane(rfb, i, format_info,
1039 : block_width, block_height, block_size_log2);
1040 0 : if (ret)
1041 : return ret;
1042 : }
1043 :
1044 : return 0;
1045 : }
1046 :
1047 0 : static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1048 : uint64_t *tiling_flags, bool *tmz_surface)
1049 : {
1050 : struct amdgpu_bo *rbo;
1051 : int r;
1052 :
1053 0 : if (!amdgpu_fb) {
1054 0 : *tiling_flags = 0;
1055 0 : *tmz_surface = false;
1056 0 : return 0;
1057 : }
1058 :
1059 0 : rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1060 0 : r = amdgpu_bo_reserve(rbo, false);
1061 :
1062 0 : if (unlikely(r)) {
1063 : /* Don't show error message when returning -ERESTARTSYS */
1064 0 : if (r != -ERESTARTSYS)
1065 0 : DRM_ERROR("Unable to reserve buffer: %d\n", r);
1066 : return r;
1067 : }
1068 :
1069 0 : if (tiling_flags)
1070 0 : amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1071 :
1072 0 : if (tmz_surface)
1073 0 : *tmz_surface = amdgpu_bo_encrypted(rbo);
1074 :
1075 0 : amdgpu_bo_unreserve(rbo);
1076 :
1077 0 : return r;
1078 : }
1079 :
1080 0 : static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1081 : struct amdgpu_framebuffer *rfb,
1082 : struct drm_file *file_priv,
1083 : const struct drm_mode_fb_cmd2 *mode_cmd,
1084 : struct drm_gem_object *obj)
1085 : {
1086 : int ret;
1087 :
1088 0 : rfb->base.obj[0] = obj;
1089 0 : drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1090 : /* Verify that the modifier is supported. */
1091 0 : if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1092 : mode_cmd->modifier[0])) {
1093 0 : drm_dbg_kms(dev,
1094 : "unsupported pixel format %p4cc / modifier 0x%llx\n",
1095 : &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1096 :
1097 0 : ret = -EINVAL;
1098 : goto err;
1099 : }
1100 :
1101 0 : ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1102 0 : if (ret)
1103 : goto err;
1104 :
1105 0 : ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1106 0 : if (ret)
1107 : goto err;
1108 :
1109 : return 0;
1110 : err:
1111 0 : drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1112 0 : rfb->base.obj[0] = NULL;
1113 : return ret;
1114 : }
1115 :
1116 0 : static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1117 : struct amdgpu_framebuffer *rfb,
1118 : const struct drm_mode_fb_cmd2 *mode_cmd,
1119 : struct drm_gem_object *obj)
1120 : {
1121 : struct amdgpu_device *adev = drm_to_adev(dev);
1122 : int ret, i;
1123 :
1124 : /*
1125 : * This needs to happen before modifier conversion as that might change
1126 : * the number of planes.
1127 : */
1128 0 : for (i = 1; i < rfb->base.format->num_planes; ++i) {
1129 0 : if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1130 0 : drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1131 : i, mode_cmd->handles[0], mode_cmd->handles[i]);
1132 0 : ret = -EINVAL;
1133 : return ret;
1134 : }
1135 : }
1136 :
1137 0 : ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1138 0 : if (ret)
1139 : return ret;
1140 :
1141 0 : if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1142 0 : drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1143 : "GFX9+ requires FB check based on format modifier\n");
1144 0 : ret = check_tiling_flags_gfx6(rfb);
1145 0 : if (ret)
1146 : return ret;
1147 : }
1148 :
1149 0 : if (!dev->mode_config.fb_modifiers_not_supported &&
1150 0 : !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1151 0 : ret = convert_tiling_flags_to_modifier(rfb);
1152 0 : if (ret) {
1153 0 : drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1154 : rfb->tiling_flags);
1155 : return ret;
1156 : }
1157 : }
1158 :
1159 0 : ret = amdgpu_display_verify_sizes(rfb);
1160 0 : if (ret)
1161 : return ret;
1162 :
1163 0 : for (i = 0; i < rfb->base.format->num_planes; ++i) {
1164 0 : drm_gem_object_get(rfb->base.obj[0]);
1165 0 : rfb->base.obj[i] = rfb->base.obj[0];
1166 : }
1167 :
1168 : return 0;
1169 : }
1170 :
1171 : struct drm_framebuffer *
1172 0 : amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1173 : struct drm_file *file_priv,
1174 : const struct drm_mode_fb_cmd2 *mode_cmd)
1175 : {
1176 : struct amdgpu_framebuffer *amdgpu_fb;
1177 : struct drm_gem_object *obj;
1178 : struct amdgpu_bo *bo;
1179 : uint32_t domains;
1180 : int ret;
1181 :
1182 0 : obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1183 0 : if (obj == NULL) {
1184 0 : drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1185 : "can't create framebuffer\n", mode_cmd->handles[0]);
1186 0 : return ERR_PTR(-ENOENT);
1187 : }
1188 :
1189 : /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1190 0 : bo = gem_to_amdgpu_bo(obj);
1191 0 : domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1192 0 : if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1193 0 : drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1194 0 : drm_gem_object_put(obj);
1195 0 : return ERR_PTR(-EINVAL);
1196 : }
1197 :
1198 0 : amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1199 0 : if (amdgpu_fb == NULL) {
1200 0 : drm_gem_object_put(obj);
1201 0 : return ERR_PTR(-ENOMEM);
1202 : }
1203 :
1204 0 : ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1205 : mode_cmd, obj);
1206 0 : if (ret) {
1207 0 : kfree(amdgpu_fb);
1208 0 : drm_gem_object_put(obj);
1209 0 : return ERR_PTR(ret);
1210 : }
1211 :
1212 0 : drm_gem_object_put(obj);
1213 0 : return &amdgpu_fb->base;
1214 : }
1215 :
1216 : const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1217 : .fb_create = amdgpu_display_user_framebuffer_create,
1218 : .output_poll_changed = drm_fb_helper_output_poll_changed,
1219 : };
1220 :
1221 : static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1222 : { { UNDERSCAN_OFF, "off" },
1223 : { UNDERSCAN_ON, "on" },
1224 : { UNDERSCAN_AUTO, "auto" },
1225 : };
1226 :
1227 : static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1228 : { { AMDGPU_AUDIO_DISABLE, "off" },
1229 : { AMDGPU_AUDIO_ENABLE, "on" },
1230 : { AMDGPU_AUDIO_AUTO, "auto" },
1231 : };
1232 :
1233 : /* XXX support different dither options? spatial, temporal, both, etc. */
1234 : static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1235 : { { AMDGPU_FMT_DITHER_DISABLE, "off" },
1236 : { AMDGPU_FMT_DITHER_ENABLE, "on" },
1237 : };
1238 :
1239 0 : int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1240 : {
1241 : int sz;
1242 :
1243 0 : adev->mode_info.coherent_mode_property =
1244 0 : drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1245 0 : if (!adev->mode_info.coherent_mode_property)
1246 : return -ENOMEM;
1247 :
1248 0 : adev->mode_info.load_detect_property =
1249 0 : drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1250 0 : if (!adev->mode_info.load_detect_property)
1251 : return -ENOMEM;
1252 :
1253 0 : drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1254 :
1255 0 : sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1256 0 : adev->mode_info.underscan_property =
1257 0 : drm_property_create_enum(adev_to_drm(adev), 0,
1258 : "underscan",
1259 : amdgpu_underscan_enum_list, sz);
1260 :
1261 0 : adev->mode_info.underscan_hborder_property =
1262 0 : drm_property_create_range(adev_to_drm(adev), 0,
1263 : "underscan hborder", 0, 128);
1264 0 : if (!adev->mode_info.underscan_hborder_property)
1265 : return -ENOMEM;
1266 :
1267 0 : adev->mode_info.underscan_vborder_property =
1268 0 : drm_property_create_range(adev_to_drm(adev), 0,
1269 : "underscan vborder", 0, 128);
1270 0 : if (!adev->mode_info.underscan_vborder_property)
1271 : return -ENOMEM;
1272 :
1273 0 : sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1274 0 : adev->mode_info.audio_property =
1275 0 : drm_property_create_enum(adev_to_drm(adev), 0,
1276 : "audio",
1277 : amdgpu_audio_enum_list, sz);
1278 :
1279 0 : sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1280 0 : adev->mode_info.dither_property =
1281 0 : drm_property_create_enum(adev_to_drm(adev), 0,
1282 : "dither",
1283 : amdgpu_dither_enum_list, sz);
1284 :
1285 0 : if (amdgpu_device_has_dc_support(adev)) {
1286 0 : adev->mode_info.abm_level_property =
1287 0 : drm_property_create_range(adev_to_drm(adev), 0,
1288 : "abm level", 0, 4);
1289 0 : if (!adev->mode_info.abm_level_property)
1290 : return -ENOMEM;
1291 : }
1292 :
1293 : return 0;
1294 : }
1295 :
1296 0 : void amdgpu_display_update_priority(struct amdgpu_device *adev)
1297 : {
1298 : /* adjustment options for the display watermarks */
1299 0 : if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1300 0 : adev->mode_info.disp_priority = 0;
1301 : else
1302 0 : adev->mode_info.disp_priority = amdgpu_disp_priority;
1303 :
1304 0 : }
1305 :
1306 : static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1307 : {
1308 : /* try and guess if this is a tv or a monitor */
1309 0 : if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1310 0 : (mode->vdisplay == 576) || /* 576p */
1311 0 : (mode->vdisplay == 720) || /* 720p */
1312 : (mode->vdisplay == 1080)) /* 1080p */
1313 : return true;
1314 : else
1315 : return false;
1316 : }
1317 :
1318 0 : bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1319 : const struct drm_display_mode *mode,
1320 : struct drm_display_mode *adjusted_mode)
1321 : {
1322 0 : struct drm_device *dev = crtc->dev;
1323 : struct drm_encoder *encoder;
1324 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1325 : struct amdgpu_encoder *amdgpu_encoder;
1326 : struct drm_connector *connector;
1327 0 : u32 src_v = 1, dst_v = 1;
1328 0 : u32 src_h = 1, dst_h = 1;
1329 :
1330 0 : amdgpu_crtc->h_border = 0;
1331 0 : amdgpu_crtc->v_border = 0;
1332 :
1333 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1334 0 : if (encoder->crtc != crtc)
1335 0 : continue;
1336 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
1337 0 : connector = amdgpu_get_connector_for_encoder(encoder);
1338 :
1339 : /* set scaling */
1340 0 : if (amdgpu_encoder->rmx_type == RMX_OFF)
1341 0 : amdgpu_crtc->rmx_type = RMX_OFF;
1342 0 : else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1343 0 : mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1344 0 : amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1345 : else
1346 0 : amdgpu_crtc->rmx_type = RMX_OFF;
1347 : /* copy native mode */
1348 0 : memcpy(&amdgpu_crtc->native_mode,
1349 0 : &amdgpu_encoder->native_mode,
1350 : sizeof(struct drm_display_mode));
1351 0 : src_v = crtc->mode.vdisplay;
1352 0 : dst_v = amdgpu_crtc->native_mode.vdisplay;
1353 0 : src_h = crtc->mode.hdisplay;
1354 0 : dst_h = amdgpu_crtc->native_mode.hdisplay;
1355 :
1356 : /* fix up for overscan on hdmi */
1357 0 : if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1358 0 : ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1359 0 : ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1360 0 : connector->display_info.is_hdmi &&
1361 0 : amdgpu_display_is_hdtv_mode(mode)))) {
1362 0 : if (amdgpu_encoder->underscan_hborder != 0)
1363 0 : amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1364 : else
1365 0 : amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1366 0 : if (amdgpu_encoder->underscan_vborder != 0)
1367 0 : amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1368 : else
1369 0 : amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1370 0 : amdgpu_crtc->rmx_type = RMX_FULL;
1371 0 : src_v = crtc->mode.vdisplay;
1372 0 : dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1373 0 : src_h = crtc->mode.hdisplay;
1374 0 : dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1375 : }
1376 : }
1377 0 : if (amdgpu_crtc->rmx_type != RMX_OFF) {
1378 : fixed20_12 a, b;
1379 0 : a.full = dfixed_const(src_v);
1380 0 : b.full = dfixed_const(dst_v);
1381 0 : amdgpu_crtc->vsc.full = dfixed_div(a, b);
1382 0 : a.full = dfixed_const(src_h);
1383 0 : b.full = dfixed_const(dst_h);
1384 0 : amdgpu_crtc->hsc.full = dfixed_div(a, b);
1385 : } else {
1386 0 : amdgpu_crtc->vsc.full = dfixed_const(1);
1387 0 : amdgpu_crtc->hsc.full = dfixed_const(1);
1388 : }
1389 0 : return true;
1390 : }
1391 :
1392 : /*
1393 : * Retrieve current video scanout position of crtc on a given gpu, and
1394 : * an optional accurate timestamp of when query happened.
1395 : *
1396 : * \param dev Device to query.
1397 : * \param pipe Crtc to query.
1398 : * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1399 : * For driver internal use only also supports these flags:
1400 : *
1401 : * USE_REAL_VBLANKSTART to use the real start of vblank instead
1402 : * of a fudged earlier start of vblank.
1403 : *
1404 : * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1405 : * fudged earlier start of vblank in *vpos and the distance
1406 : * to true start of vblank in *hpos.
1407 : *
1408 : * \param *vpos Location where vertical scanout position should be stored.
1409 : * \param *hpos Location where horizontal scanout position should go.
1410 : * \param *stime Target location for timestamp taken immediately before
1411 : * scanout position query. Can be NULL to skip timestamp.
1412 : * \param *etime Target location for timestamp taken immediately after
1413 : * scanout position query. Can be NULL to skip timestamp.
1414 : *
1415 : * Returns vpos as a positive number while in active scanout area.
1416 : * Returns vpos as a negative number inside vblank, counting the number
1417 : * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1418 : * until start of active scanout / end of vblank."
1419 : *
1420 : * \return Flags, or'ed together as follows:
1421 : *
1422 : * DRM_SCANOUTPOS_VALID = Query successful.
1423 : * DRM_SCANOUTPOS_INVBL = Inside vblank.
1424 : * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1425 : * this flag means that returned position may be offset by a constant but
1426 : * unknown small number of scanlines wrt. real scanout position.
1427 : *
1428 : */
1429 0 : int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1430 : unsigned int pipe, unsigned int flags, int *vpos,
1431 : int *hpos, ktime_t *stime, ktime_t *etime,
1432 : const struct drm_display_mode *mode)
1433 : {
1434 0 : u32 vbl = 0, position = 0;
1435 0 : int vbl_start, vbl_end, vtotal, ret = 0;
1436 0 : bool in_vbl = true;
1437 :
1438 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1439 :
1440 : /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1441 :
1442 : /* Get optional system timestamp before query. */
1443 0 : if (stime)
1444 0 : *stime = ktime_get();
1445 :
1446 0 : if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1447 0 : ret |= DRM_SCANOUTPOS_VALID;
1448 :
1449 : /* Get optional system timestamp after query. */
1450 0 : if (etime)
1451 0 : *etime = ktime_get();
1452 :
1453 : /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1454 :
1455 : /* Decode into vertical and horizontal scanout position. */
1456 0 : *vpos = position & 0x1fff;
1457 0 : *hpos = (position >> 16) & 0x1fff;
1458 :
1459 : /* Valid vblank area boundaries from gpu retrieved? */
1460 0 : if (vbl > 0) {
1461 : /* Yes: Decode. */
1462 0 : ret |= DRM_SCANOUTPOS_ACCURATE;
1463 0 : vbl_start = vbl & 0x1fff;
1464 0 : vbl_end = (vbl >> 16) & 0x1fff;
1465 : }
1466 : else {
1467 : /* No: Fake something reasonable which gives at least ok results. */
1468 0 : vbl_start = mode->crtc_vdisplay;
1469 0 : vbl_end = 0;
1470 : }
1471 :
1472 : /* Called from driver internal vblank counter query code? */
1473 0 : if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1474 : /* Caller wants distance from real vbl_start in *hpos */
1475 0 : *hpos = *vpos - vbl_start;
1476 : }
1477 :
1478 : /* Fudge vblank to start a few scanlines earlier to handle the
1479 : * problem that vblank irqs fire a few scanlines before start
1480 : * of vblank. Some driver internal callers need the true vblank
1481 : * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1482 : *
1483 : * The cause of the "early" vblank irq is that the irq is triggered
1484 : * by the line buffer logic when the line buffer read position enters
1485 : * the vblank, whereas our crtc scanout position naturally lags the
1486 : * line buffer read position.
1487 : */
1488 0 : if (!(flags & USE_REAL_VBLANKSTART))
1489 0 : vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1490 :
1491 : /* Test scanout position against vblank region. */
1492 0 : if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1493 0 : in_vbl = false;
1494 :
1495 : /* In vblank? */
1496 0 : if (in_vbl)
1497 0 : ret |= DRM_SCANOUTPOS_IN_VBLANK;
1498 :
1499 : /* Called from driver internal vblank counter query code? */
1500 0 : if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1501 : /* Caller wants distance from fudged earlier vbl_start */
1502 0 : *vpos -= vbl_start;
1503 0 : return ret;
1504 : }
1505 :
1506 : /* Check if inside vblank area and apply corrective offsets:
1507 : * vpos will then be >=0 in video scanout area, but negative
1508 : * within vblank area, counting down the number of lines until
1509 : * start of scanout.
1510 : */
1511 :
1512 : /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1513 0 : if (in_vbl && (*vpos >= vbl_start)) {
1514 0 : vtotal = mode->crtc_vtotal;
1515 :
1516 : /* With variable refresh rate displays the vpos can exceed
1517 : * the vtotal value. Clamp to 0 to return -vbl_end instead
1518 : * of guessing the remaining number of lines until scanout.
1519 : */
1520 0 : *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1521 : }
1522 :
1523 : /* Correct for shifted end of vbl at vbl_end. */
1524 0 : *vpos = *vpos - vbl_end;
1525 :
1526 0 : return ret;
1527 : }
1528 :
1529 0 : int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1530 : {
1531 0 : if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1532 : return AMDGPU_CRTC_IRQ_NONE;
1533 :
1534 : switch (crtc) {
1535 : case 0:
1536 : return AMDGPU_CRTC_IRQ_VBLANK1;
1537 : case 1:
1538 : return AMDGPU_CRTC_IRQ_VBLANK2;
1539 : case 2:
1540 : return AMDGPU_CRTC_IRQ_VBLANK3;
1541 : case 3:
1542 : return AMDGPU_CRTC_IRQ_VBLANK4;
1543 : case 4:
1544 : return AMDGPU_CRTC_IRQ_VBLANK5;
1545 : case 5:
1546 : return AMDGPU_CRTC_IRQ_VBLANK6;
1547 : default:
1548 : return AMDGPU_CRTC_IRQ_NONE;
1549 : }
1550 : }
1551 :
1552 0 : bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1553 : bool in_vblank_irq, int *vpos,
1554 : int *hpos, ktime_t *stime, ktime_t *etime,
1555 : const struct drm_display_mode *mode)
1556 : {
1557 0 : struct drm_device *dev = crtc->dev;
1558 0 : unsigned int pipe = crtc->index;
1559 :
1560 0 : return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1561 : stime, etime, mode);
1562 : }
1563 :
1564 : static bool
1565 : amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1566 : {
1567 0 : struct drm_device *dev = adev_to_drm(adev);
1568 0 : struct drm_fb_helper *fb_helper = dev->fb_helper;
1569 :
1570 0 : if (!fb_helper || !fb_helper->buffer)
1571 : return false;
1572 :
1573 0 : if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1574 : return false;
1575 :
1576 : return true;
1577 : }
1578 :
1579 0 : int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1580 : {
1581 0 : struct drm_device *dev = adev_to_drm(adev);
1582 : struct drm_crtc *crtc;
1583 : struct drm_connector *connector;
1584 : struct drm_connector_list_iter iter;
1585 : int r;
1586 :
1587 : /* turn off display hw */
1588 0 : drm_modeset_lock_all(dev);
1589 0 : drm_connector_list_iter_begin(dev, &iter);
1590 0 : drm_for_each_connector_iter(connector, &iter)
1591 0 : drm_helper_connector_dpms(connector,
1592 : DRM_MODE_DPMS_OFF);
1593 0 : drm_connector_list_iter_end(&iter);
1594 0 : drm_modeset_unlock_all(dev);
1595 : /* unpin the front buffers and cursors */
1596 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1597 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1598 0 : struct drm_framebuffer *fb = crtc->primary->fb;
1599 : struct amdgpu_bo *robj;
1600 :
1601 0 : if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1602 0 : struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1603 0 : r = amdgpu_bo_reserve(aobj, true);
1604 0 : if (r == 0) {
1605 0 : amdgpu_bo_unpin(aobj);
1606 : amdgpu_bo_unreserve(aobj);
1607 : }
1608 : }
1609 :
1610 0 : if (fb == NULL || fb->obj[0] == NULL) {
1611 0 : continue;
1612 : }
1613 0 : robj = gem_to_amdgpu_bo(fb->obj[0]);
1614 0 : if (!amdgpu_display_robj_is_fb(adev, robj)) {
1615 0 : r = amdgpu_bo_reserve(robj, true);
1616 0 : if (r == 0) {
1617 0 : amdgpu_bo_unpin(robj);
1618 : amdgpu_bo_unreserve(robj);
1619 : }
1620 : }
1621 : }
1622 0 : return 0;
1623 : }
1624 :
1625 0 : int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1626 : {
1627 0 : struct drm_device *dev = adev_to_drm(adev);
1628 : struct drm_connector *connector;
1629 : struct drm_connector_list_iter iter;
1630 : struct drm_crtc *crtc;
1631 : int r;
1632 :
1633 : /* pin cursors */
1634 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1635 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1636 :
1637 0 : if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1638 0 : struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1639 0 : r = amdgpu_bo_reserve(aobj, true);
1640 0 : if (r == 0) {
1641 0 : r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1642 0 : if (r != 0)
1643 0 : dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1644 0 : amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1645 : amdgpu_bo_unreserve(aobj);
1646 : }
1647 : }
1648 : }
1649 :
1650 0 : drm_helper_resume_force_mode(dev);
1651 :
1652 : /* turn on display hw */
1653 0 : drm_modeset_lock_all(dev);
1654 :
1655 0 : drm_connector_list_iter_begin(dev, &iter);
1656 0 : drm_for_each_connector_iter(connector, &iter)
1657 0 : drm_helper_connector_dpms(connector,
1658 : DRM_MODE_DPMS_ON);
1659 0 : drm_connector_list_iter_end(&iter);
1660 :
1661 0 : drm_modeset_unlock_all(dev);
1662 :
1663 0 : return 0;
1664 : }
1665 :
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