Line data Source code
1 : /*
2 : * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 : * All Rights Reserved.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice (including the next
13 : * paragraph) shall be included in all copies or substantial portions of the
14 : * Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : */
24 :
25 : #include <drm/amdgpu_drm.h>
26 : #include <drm/drm_aperture.h>
27 : #include <drm/drm_drv.h>
28 : #include <drm/drm_gem.h>
29 : #include <drm/drm_vblank.h>
30 : #include <drm/drm_managed.h>
31 : #include "amdgpu_drv.h"
32 :
33 : #include <drm/drm_pciids.h>
34 : #include <linux/module.h>
35 : #include <linux/pm_runtime.h>
36 : #include <linux/vga_switcheroo.h>
37 : #include <drm/drm_probe_helper.h>
38 : #include <linux/mmu_notifier.h>
39 : #include <linux/suspend.h>
40 : #include <linux/cc_platform.h>
41 :
42 : #include "amdgpu.h"
43 : #include "amdgpu_irq.h"
44 : #include "amdgpu_dma_buf.h"
45 : #include "amdgpu_sched.h"
46 : #include "amdgpu_fdinfo.h"
47 : #include "amdgpu_amdkfd.h"
48 :
49 : #include "amdgpu_ras.h"
50 : #include "amdgpu_xgmi.h"
51 : #include "amdgpu_reset.h"
52 :
53 : /*
54 : * KMS wrapper.
55 : * - 3.0.0 - initial driver
56 : * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
57 : * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
58 : * at the end of IBs.
59 : * - 3.3.0 - Add VM support for UVD on supported hardware.
60 : * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
61 : * - 3.5.0 - Add support for new UVD_NO_OP register.
62 : * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
63 : * - 3.7.0 - Add support for VCE clock list packet
64 : * - 3.8.0 - Add support raster config init in the kernel
65 : * - 3.9.0 - Add support for memory query info about VRAM and GTT.
66 : * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
67 : * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
68 : * - 3.12.0 - Add query for double offchip LDS buffers
69 : * - 3.13.0 - Add PRT support
70 : * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
71 : * - 3.15.0 - Export more gpu info for gfx9
72 : * - 3.16.0 - Add reserved vmid support
73 : * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
74 : * - 3.18.0 - Export gpu always on cu bitmap
75 : * - 3.19.0 - Add support for UVD MJPEG decode
76 : * - 3.20.0 - Add support for local BOs
77 : * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
78 : * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
79 : * - 3.23.0 - Add query for VRAM lost counter
80 : * - 3.24.0 - Add high priority compute support for gfx9
81 : * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
82 : * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
83 : * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
84 : * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
85 : * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
86 : * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
87 : * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
88 : * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
89 : * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
90 : * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
91 : * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
92 : * - 3.36.0 - Allow reading more status registers on si/cik
93 : * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
94 : * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
95 : * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
96 : * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
97 : * - 3.41.0 - Add video codec query
98 : * - 3.42.0 - Add 16bpc fixed point display support
99 : * - 3.43.0 - Add device hot plug/unplug support
100 : * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
101 : * - 3.45.0 - Add context ioctl stable pstate interface
102 : * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
103 : * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
104 : * - 3.48.0 - Add IP discovery version info to HW INFO
105 : */
106 : #define KMS_DRIVER_MAJOR 3
107 : #define KMS_DRIVER_MINOR 48
108 : #define KMS_DRIVER_PATCHLEVEL 0
109 :
110 : int amdgpu_vram_limit;
111 : int amdgpu_vis_vram_limit;
112 : int amdgpu_gart_size = -1; /* auto */
113 : int amdgpu_gtt_size = -1; /* auto */
114 : int amdgpu_moverate = -1; /* auto */
115 : int amdgpu_audio = -1;
116 : int amdgpu_disp_priority;
117 : int amdgpu_hw_i2c;
118 : int amdgpu_pcie_gen2 = -1;
119 : int amdgpu_msi = -1;
120 : char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
121 : int amdgpu_dpm = -1;
122 : int amdgpu_fw_load_type = -1;
123 : int amdgpu_aspm = -1;
124 : int amdgpu_runtime_pm = -1;
125 : uint amdgpu_ip_block_mask = 0xffffffff;
126 : int amdgpu_bapm = -1;
127 : int amdgpu_deep_color;
128 : int amdgpu_vm_size = -1;
129 : int amdgpu_vm_fragment_size = -1;
130 : int amdgpu_vm_block_size = -1;
131 : int amdgpu_vm_fault_stop;
132 : int amdgpu_vm_debug;
133 : int amdgpu_vm_update_mode = -1;
134 : int amdgpu_exp_hw_support;
135 : int amdgpu_dc = -1;
136 : int amdgpu_sched_jobs = 32;
137 : int amdgpu_sched_hw_submission = 2;
138 : uint amdgpu_pcie_gen_cap;
139 : uint amdgpu_pcie_lane_cap;
140 : u64 amdgpu_cg_mask = 0xffffffffffffffff;
141 : uint amdgpu_pg_mask = 0xffffffff;
142 : uint amdgpu_sdma_phase_quantum = 32;
143 : char *amdgpu_disable_cu = NULL;
144 : char *amdgpu_virtual_display = NULL;
145 :
146 : /*
147 : * OverDrive(bit 14) disabled by default
148 : * GFX DCS(bit 19) disabled by default
149 : */
150 : uint amdgpu_pp_feature_mask = 0xfff7bfff;
151 : uint amdgpu_force_long_training;
152 : int amdgpu_job_hang_limit;
153 : int amdgpu_lbpw = -1;
154 : int amdgpu_compute_multipipe = -1;
155 : int amdgpu_gpu_recovery = -1; /* auto */
156 : int amdgpu_emu_mode;
157 : uint amdgpu_smu_memory_pool_size;
158 : int amdgpu_smu_pptable_id = -1;
159 : /*
160 : * FBC (bit 0) disabled by default
161 : * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
162 : * - With this, for multiple monitors in sync(e.g. with the same model),
163 : * mclk switching will be allowed. And the mclk will be not foced to the
164 : * highest. That helps saving some idle power.
165 : * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
166 : * PSR (bit 3) disabled by default
167 : * EDP NO POWER SEQUENCING (bit 4) disabled by default
168 : */
169 : uint amdgpu_dc_feature_mask = 2;
170 : uint amdgpu_dc_debug_mask;
171 : uint amdgpu_dc_visual_confirm;
172 : int amdgpu_async_gfx_ring = 1;
173 : int amdgpu_mcbp;
174 : int amdgpu_discovery = -1;
175 : int amdgpu_mes;
176 : int amdgpu_mes_kiq;
177 : int amdgpu_noretry = -1;
178 : int amdgpu_force_asic_type = -1;
179 : int amdgpu_tmz = -1; /* auto */
180 : int amdgpu_reset_method = -1; /* auto */
181 : int amdgpu_num_kcq = -1;
182 : int amdgpu_smartshift_bias;
183 : int amdgpu_use_xgmi_p2p = 1;
184 : int amdgpu_vcnfw_log;
185 :
186 : static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
187 :
188 : struct amdgpu_mgpu_info mgpu_info = {
189 : .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
190 : .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
191 : mgpu_info.delayed_reset_work,
192 : amdgpu_drv_delayed_reset_work_handler, 0),
193 : };
194 : int amdgpu_ras_enable = -1;
195 : uint amdgpu_ras_mask = 0xffffffff;
196 : int amdgpu_bad_page_threshold = -1;
197 : struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
198 : .timeout_fatal_disable = false,
199 : .period = 0x0, /* default to 0x0 (timeout disable) */
200 : };
201 :
202 : /**
203 : * DOC: vramlimit (int)
204 : * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
205 : */
206 : MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
207 : module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
208 :
209 : /**
210 : * DOC: vis_vramlimit (int)
211 : * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
212 : */
213 : MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
214 : module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
215 :
216 : /**
217 : * DOC: gartsize (uint)
218 : * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
219 : */
220 : MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
221 : module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
222 :
223 : /**
224 : * DOC: gttsize (int)
225 : * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
226 : * otherwise 3/4 RAM size).
227 : */
228 : MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
229 : module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
230 :
231 : /**
232 : * DOC: moverate (int)
233 : * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
234 : */
235 : MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
236 : module_param_named(moverate, amdgpu_moverate, int, 0600);
237 :
238 : /**
239 : * DOC: audio (int)
240 : * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
241 : */
242 : MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
243 : module_param_named(audio, amdgpu_audio, int, 0444);
244 :
245 : /**
246 : * DOC: disp_priority (int)
247 : * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
248 : */
249 : MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
250 : module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
251 :
252 : /**
253 : * DOC: hw_i2c (int)
254 : * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
255 : */
256 : MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
257 : module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
258 :
259 : /**
260 : * DOC: pcie_gen2 (int)
261 : * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
262 : */
263 : MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
264 : module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
265 :
266 : /**
267 : * DOC: msi (int)
268 : * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
269 : */
270 : MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
271 : module_param_named(msi, amdgpu_msi, int, 0444);
272 :
273 : /**
274 : * DOC: lockup_timeout (string)
275 : * Set GPU scheduler timeout value in ms.
276 : *
277 : * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
278 : * multiple values specified. 0 and negative values are invalidated. They will be adjusted
279 : * to the default timeout.
280 : *
281 : * - With one value specified, the setting will apply to all non-compute jobs.
282 : * - With multiple values specified, the first one will be for GFX.
283 : * The second one is for Compute. The third and fourth ones are
284 : * for SDMA and Video.
285 : *
286 : * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
287 : * jobs is 10000. The timeout for compute is 60000.
288 : */
289 : MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
290 : "for passthrough or sriov, 10000 for all jobs."
291 : " 0: keep default value. negative: infinity timeout), "
292 : "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
293 : "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
294 : module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
295 :
296 : /**
297 : * DOC: dpm (int)
298 : * Override for dynamic power management setting
299 : * (0 = disable, 1 = enable)
300 : * The default is -1 (auto).
301 : */
302 : MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
303 : module_param_named(dpm, amdgpu_dpm, int, 0444);
304 :
305 : /**
306 : * DOC: fw_load_type (int)
307 : * Set different firmware loading type for debugging, if supported.
308 : * Set to 0 to force direct loading if supported by the ASIC. Set
309 : * to -1 to select the default loading mode for the ASIC, as defined
310 : * by the driver. The default is -1 (auto).
311 : */
312 : MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
313 : module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
314 :
315 : /**
316 : * DOC: aspm (int)
317 : * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
318 : */
319 : MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
320 : module_param_named(aspm, amdgpu_aspm, int, 0444);
321 :
322 : /**
323 : * DOC: runpm (int)
324 : * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
325 : * the dGPUs when they are idle if supported. The default is -1 (auto enable).
326 : * Setting the value to 0 disables this functionality.
327 : */
328 : MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
329 : module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
330 :
331 : /**
332 : * DOC: ip_block_mask (uint)
333 : * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
334 : * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
335 : * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
336 : * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
337 : */
338 : MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
339 : module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
340 :
341 : /**
342 : * DOC: bapm (int)
343 : * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
344 : * The default -1 (auto, enabled)
345 : */
346 : MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
347 : module_param_named(bapm, amdgpu_bapm, int, 0444);
348 :
349 : /**
350 : * DOC: deep_color (int)
351 : * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
352 : */
353 : MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
354 : module_param_named(deep_color, amdgpu_deep_color, int, 0444);
355 :
356 : /**
357 : * DOC: vm_size (int)
358 : * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
359 : */
360 : MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
361 : module_param_named(vm_size, amdgpu_vm_size, int, 0444);
362 :
363 : /**
364 : * DOC: vm_fragment_size (int)
365 : * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
366 : */
367 : MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
368 : module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
369 :
370 : /**
371 : * DOC: vm_block_size (int)
372 : * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
373 : */
374 : MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
375 : module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
376 :
377 : /**
378 : * DOC: vm_fault_stop (int)
379 : * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
380 : */
381 : MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
382 : module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
383 :
384 : /**
385 : * DOC: vm_debug (int)
386 : * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
387 : */
388 : MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
389 : module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
390 :
391 : /**
392 : * DOC: vm_update_mode (int)
393 : * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
394 : * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
395 : */
396 : MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
397 : module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
398 :
399 : /**
400 : * DOC: exp_hw_support (int)
401 : * Enable experimental hw support (1 = enable). The default is 0 (disabled).
402 : */
403 : MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
404 : module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
405 :
406 : /**
407 : * DOC: dc (int)
408 : * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
409 : */
410 : MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
411 : module_param_named(dc, amdgpu_dc, int, 0444);
412 :
413 : /**
414 : * DOC: sched_jobs (int)
415 : * Override the max number of jobs supported in the sw queue. The default is 32.
416 : */
417 : MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
418 : module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
419 :
420 : /**
421 : * DOC: sched_hw_submission (int)
422 : * Override the max number of HW submissions. The default is 2.
423 : */
424 : MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
425 : module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
426 :
427 : /**
428 : * DOC: ppfeaturemask (hexint)
429 : * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
430 : * The default is the current set of stable power features.
431 : */
432 : MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
433 : module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
434 :
435 : /**
436 : * DOC: forcelongtraining (uint)
437 : * Force long memory training in resume.
438 : * The default is zero, indicates short training in resume.
439 : */
440 : MODULE_PARM_DESC(forcelongtraining, "force memory long training");
441 : module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
442 :
443 : /**
444 : * DOC: pcie_gen_cap (uint)
445 : * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
446 : * The default is 0 (automatic for each asic).
447 : */
448 : MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
449 : module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
450 :
451 : /**
452 : * DOC: pcie_lane_cap (uint)
453 : * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
454 : * The default is 0 (automatic for each asic).
455 : */
456 : MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
457 : module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
458 :
459 : /**
460 : * DOC: cg_mask (ullong)
461 : * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
462 : * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
463 : */
464 : MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
465 : module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
466 :
467 : /**
468 : * DOC: pg_mask (uint)
469 : * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
470 : * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
471 : */
472 : MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
473 : module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
474 :
475 : /**
476 : * DOC: sdma_phase_quantum (uint)
477 : * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
478 : */
479 : MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
480 : module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
481 :
482 : /**
483 : * DOC: disable_cu (charp)
484 : * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
485 : */
486 : MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
487 : module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
488 :
489 : /**
490 : * DOC: virtual_display (charp)
491 : * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
492 : * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
493 : * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
494 : * device at 26:00.0. The default is NULL.
495 : */
496 : MODULE_PARM_DESC(virtual_display,
497 : "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
498 : module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
499 :
500 : /**
501 : * DOC: job_hang_limit (int)
502 : * Set how much time allow a job hang and not drop it. The default is 0.
503 : */
504 : MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
505 : module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
506 :
507 : /**
508 : * DOC: lbpw (int)
509 : * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
510 : */
511 : MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
512 : module_param_named(lbpw, amdgpu_lbpw, int, 0444);
513 :
514 : MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
515 : module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
516 :
517 : /**
518 : * DOC: gpu_recovery (int)
519 : * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
520 : */
521 : MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
522 : module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
523 :
524 : /**
525 : * DOC: emu_mode (int)
526 : * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
527 : */
528 : MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
529 : module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
530 :
531 : /**
532 : * DOC: ras_enable (int)
533 : * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
534 : */
535 : MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
536 : module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
537 :
538 : /**
539 : * DOC: ras_mask (uint)
540 : * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
541 : * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
542 : */
543 : MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
544 : module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
545 :
546 : /**
547 : * DOC: timeout_fatal_disable (bool)
548 : * Disable Watchdog timeout fatal error event
549 : */
550 : MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
551 : module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
552 :
553 : /**
554 : * DOC: timeout_period (uint)
555 : * Modify the watchdog timeout max_cycles as (1 << period)
556 : */
557 : MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
558 : module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
559 :
560 : /**
561 : * DOC: si_support (int)
562 : * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
563 : * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
564 : * otherwise using amdgpu driver.
565 : */
566 : #ifdef CONFIG_DRM_AMDGPU_SI
567 :
568 : #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
569 : int amdgpu_si_support = 0;
570 : MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
571 : #else
572 : int amdgpu_si_support = 1;
573 : MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
574 : #endif
575 :
576 : module_param_named(si_support, amdgpu_si_support, int, 0444);
577 : #endif
578 :
579 : /**
580 : * DOC: cik_support (int)
581 : * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
582 : * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
583 : * otherwise using amdgpu driver.
584 : */
585 : #ifdef CONFIG_DRM_AMDGPU_CIK
586 :
587 : #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
588 : int amdgpu_cik_support = 0;
589 : MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
590 : #else
591 : int amdgpu_cik_support = 1;
592 : MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
593 : #endif
594 :
595 : module_param_named(cik_support, amdgpu_cik_support, int, 0444);
596 : #endif
597 :
598 : /**
599 : * DOC: smu_memory_pool_size (uint)
600 : * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
601 : * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
602 : */
603 : MODULE_PARM_DESC(smu_memory_pool_size,
604 : "reserve gtt for smu debug usage, 0 = disable,"
605 : "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
606 : module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
607 :
608 : /**
609 : * DOC: async_gfx_ring (int)
610 : * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
611 : */
612 : MODULE_PARM_DESC(async_gfx_ring,
613 : "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
614 : module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
615 :
616 : /**
617 : * DOC: mcbp (int)
618 : * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
619 : */
620 : MODULE_PARM_DESC(mcbp,
621 : "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
622 : module_param_named(mcbp, amdgpu_mcbp, int, 0444);
623 :
624 : /**
625 : * DOC: discovery (int)
626 : * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
627 : * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
628 : */
629 : MODULE_PARM_DESC(discovery,
630 : "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
631 : module_param_named(discovery, amdgpu_discovery, int, 0444);
632 :
633 : /**
634 : * DOC: mes (int)
635 : * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
636 : * (0 = disabled (default), 1 = enabled)
637 : */
638 : MODULE_PARM_DESC(mes,
639 : "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
640 : module_param_named(mes, amdgpu_mes, int, 0444);
641 :
642 : /**
643 : * DOC: mes_kiq (int)
644 : * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
645 : * (0 = disabled (default), 1 = enabled)
646 : */
647 : MODULE_PARM_DESC(mes_kiq,
648 : "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
649 : module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
650 :
651 : /**
652 : * DOC: noretry (int)
653 : * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
654 : * do not support per-process XNACK this also disables retry page faults.
655 : * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
656 : */
657 : MODULE_PARM_DESC(noretry,
658 : "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
659 : module_param_named(noretry, amdgpu_noretry, int, 0644);
660 :
661 : /**
662 : * DOC: force_asic_type (int)
663 : * A non negative value used to specify the asic type for all supported GPUs.
664 : */
665 : MODULE_PARM_DESC(force_asic_type,
666 : "A non negative value used to specify the asic type for all supported GPUs");
667 : module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
668 :
669 : /**
670 : * DOC: use_xgmi_p2p (int)
671 : * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
672 : */
673 : MODULE_PARM_DESC(use_xgmi_p2p,
674 : "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
675 : module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
676 :
677 :
678 : #ifdef CONFIG_HSA_AMD
679 : /**
680 : * DOC: sched_policy (int)
681 : * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
682 : * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
683 : * assigns queues to HQDs.
684 : */
685 : int sched_policy = KFD_SCHED_POLICY_HWS;
686 : module_param(sched_policy, int, 0444);
687 : MODULE_PARM_DESC(sched_policy,
688 : "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
689 :
690 : /**
691 : * DOC: hws_max_conc_proc (int)
692 : * Maximum number of processes that HWS can schedule concurrently. The maximum is the
693 : * number of VMIDs assigned to the HWS, which is also the default.
694 : */
695 : int hws_max_conc_proc = -1;
696 : module_param(hws_max_conc_proc, int, 0444);
697 : MODULE_PARM_DESC(hws_max_conc_proc,
698 : "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
699 :
700 : /**
701 : * DOC: cwsr_enable (int)
702 : * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
703 : * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
704 : * disables it.
705 : */
706 : int cwsr_enable = 1;
707 : module_param(cwsr_enable, int, 0444);
708 : MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
709 :
710 : /**
711 : * DOC: max_num_of_queues_per_device (int)
712 : * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
713 : * is 4096.
714 : */
715 : int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
716 : module_param(max_num_of_queues_per_device, int, 0444);
717 : MODULE_PARM_DESC(max_num_of_queues_per_device,
718 : "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
719 :
720 : /**
721 : * DOC: send_sigterm (int)
722 : * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
723 : * but just print errors on dmesg. Setting 1 enables sending sigterm.
724 : */
725 : int send_sigterm;
726 : module_param(send_sigterm, int, 0444);
727 : MODULE_PARM_DESC(send_sigterm,
728 : "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
729 :
730 : /**
731 : * DOC: debug_largebar (int)
732 : * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
733 : * system. This limits the VRAM size reported to ROCm applications to the visible
734 : * size, usually 256MB.
735 : * Default value is 0, diabled.
736 : */
737 : int debug_largebar;
738 : module_param(debug_largebar, int, 0444);
739 : MODULE_PARM_DESC(debug_largebar,
740 : "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
741 :
742 : /**
743 : * DOC: ignore_crat (int)
744 : * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
745 : * table to get information about AMD APUs. This option can serve as a workaround on
746 : * systems with a broken CRAT table.
747 : *
748 : * Default is auto (according to asic type, iommu_v2, and crat table, to decide
749 : * whether use CRAT)
750 : */
751 : int ignore_crat;
752 : module_param(ignore_crat, int, 0444);
753 : MODULE_PARM_DESC(ignore_crat,
754 : "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
755 :
756 : /**
757 : * DOC: halt_if_hws_hang (int)
758 : * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
759 : * Setting 1 enables halt on hang.
760 : */
761 : int halt_if_hws_hang;
762 : module_param(halt_if_hws_hang, int, 0644);
763 : MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
764 :
765 : /**
766 : * DOC: hws_gws_support(bool)
767 : * Assume that HWS supports GWS barriers regardless of what firmware version
768 : * check says. Default value: false (rely on MEC2 firmware version check).
769 : */
770 : bool hws_gws_support;
771 : module_param(hws_gws_support, bool, 0444);
772 : MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
773 :
774 : /**
775 : * DOC: queue_preemption_timeout_ms (int)
776 : * queue preemption timeout in ms (1 = Minimum, 9000 = default)
777 : */
778 : int queue_preemption_timeout_ms = 9000;
779 : module_param(queue_preemption_timeout_ms, int, 0644);
780 : MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
781 :
782 : /**
783 : * DOC: debug_evictions(bool)
784 : * Enable extra debug messages to help determine the cause of evictions
785 : */
786 : bool debug_evictions;
787 : module_param(debug_evictions, bool, 0644);
788 : MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
789 :
790 : /**
791 : * DOC: no_system_mem_limit(bool)
792 : * Disable system memory limit, to support multiple process shared memory
793 : */
794 : bool no_system_mem_limit;
795 : module_param(no_system_mem_limit, bool, 0644);
796 : MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
797 :
798 : /**
799 : * DOC: no_queue_eviction_on_vm_fault (int)
800 : * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
801 : */
802 : int amdgpu_no_queue_eviction_on_vm_fault = 0;
803 : MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
804 : module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
805 : #endif
806 :
807 : /**
808 : * DOC: pcie_p2p (bool)
809 : * Enable PCIe P2P (requires large-BAR). Default value: true (on)
810 : */
811 : #ifdef CONFIG_HSA_AMD_P2P
812 : bool pcie_p2p = true;
813 : module_param(pcie_p2p, bool, 0444);
814 : MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
815 : #endif
816 :
817 : /**
818 : * DOC: dcfeaturemask (uint)
819 : * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
820 : * The default is the current set of stable display features.
821 : */
822 : MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
823 : module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
824 :
825 : /**
826 : * DOC: dcdebugmask (uint)
827 : * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
828 : */
829 : MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
830 : module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
831 :
832 : MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
833 : module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
834 :
835 : /**
836 : * DOC: abmlevel (uint)
837 : * Override the default ABM (Adaptive Backlight Management) level used for DC
838 : * enabled hardware. Requires DMCU to be supported and loaded.
839 : * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
840 : * default. Values 1-4 control the maximum allowable brightness reduction via
841 : * the ABM algorithm, with 1 being the least reduction and 4 being the most
842 : * reduction.
843 : *
844 : * Defaults to 0, or disabled. Userspace can still override this level later
845 : * after boot.
846 : */
847 : uint amdgpu_dm_abm_level;
848 : MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
849 : module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
850 :
851 : int amdgpu_backlight = -1;
852 : MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
853 : module_param_named(backlight, amdgpu_backlight, bint, 0444);
854 :
855 : /**
856 : * DOC: tmz (int)
857 : * Trusted Memory Zone (TMZ) is a method to protect data being written
858 : * to or read from memory.
859 : *
860 : * The default value: 0 (off). TODO: change to auto till it is completed.
861 : */
862 : MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
863 : module_param_named(tmz, amdgpu_tmz, int, 0444);
864 :
865 : /**
866 : * DOC: reset_method (int)
867 : * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
868 : */
869 : MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
870 : module_param_named(reset_method, amdgpu_reset_method, int, 0444);
871 :
872 : /**
873 : * DOC: bad_page_threshold (int) Bad page threshold is specifies the
874 : * threshold value of faulty pages detected by RAS ECC, which may
875 : * result in the GPU entering bad status when the number of total
876 : * faulty pages by ECC exceeds the threshold value.
877 : */
878 : MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
879 : module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
880 :
881 : MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
882 : module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
883 :
884 : /**
885 : * DOC: vcnfw_log (int)
886 : * Enable vcnfw log output for debugging, the default is disabled.
887 : */
888 : MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
889 : module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
890 :
891 : /**
892 : * DOC: smu_pptable_id (int)
893 : * Used to override pptable id. id = 0 use VBIOS pptable.
894 : * id > 0 use the soft pptable with specicfied id.
895 : */
896 : MODULE_PARM_DESC(smu_pptable_id,
897 : "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
898 : module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
899 :
900 : /* These devices are not supported by amdgpu.
901 : * They are supported by the mach64, r128, radeon drivers
902 : */
903 : static const u16 amdgpu_unsupported_pciidlist[] = {
904 : /* mach64 */
905 : 0x4354,
906 : 0x4358,
907 : 0x4554,
908 : 0x4742,
909 : 0x4744,
910 : 0x4749,
911 : 0x474C,
912 : 0x474D,
913 : 0x474E,
914 : 0x474F,
915 : 0x4750,
916 : 0x4751,
917 : 0x4752,
918 : 0x4753,
919 : 0x4754,
920 : 0x4755,
921 : 0x4756,
922 : 0x4757,
923 : 0x4758,
924 : 0x4759,
925 : 0x475A,
926 : 0x4C42,
927 : 0x4C44,
928 : 0x4C47,
929 : 0x4C49,
930 : 0x4C4D,
931 : 0x4C4E,
932 : 0x4C50,
933 : 0x4C51,
934 : 0x4C52,
935 : 0x4C53,
936 : 0x5654,
937 : 0x5655,
938 : 0x5656,
939 : /* r128 */
940 : 0x4c45,
941 : 0x4c46,
942 : 0x4d46,
943 : 0x4d4c,
944 : 0x5041,
945 : 0x5042,
946 : 0x5043,
947 : 0x5044,
948 : 0x5045,
949 : 0x5046,
950 : 0x5047,
951 : 0x5048,
952 : 0x5049,
953 : 0x504A,
954 : 0x504B,
955 : 0x504C,
956 : 0x504D,
957 : 0x504E,
958 : 0x504F,
959 : 0x5050,
960 : 0x5051,
961 : 0x5052,
962 : 0x5053,
963 : 0x5054,
964 : 0x5055,
965 : 0x5056,
966 : 0x5057,
967 : 0x5058,
968 : 0x5245,
969 : 0x5246,
970 : 0x5247,
971 : 0x524b,
972 : 0x524c,
973 : 0x534d,
974 : 0x5446,
975 : 0x544C,
976 : 0x5452,
977 : /* radeon */
978 : 0x3150,
979 : 0x3151,
980 : 0x3152,
981 : 0x3154,
982 : 0x3155,
983 : 0x3E50,
984 : 0x3E54,
985 : 0x4136,
986 : 0x4137,
987 : 0x4144,
988 : 0x4145,
989 : 0x4146,
990 : 0x4147,
991 : 0x4148,
992 : 0x4149,
993 : 0x414A,
994 : 0x414B,
995 : 0x4150,
996 : 0x4151,
997 : 0x4152,
998 : 0x4153,
999 : 0x4154,
1000 : 0x4155,
1001 : 0x4156,
1002 : 0x4237,
1003 : 0x4242,
1004 : 0x4336,
1005 : 0x4337,
1006 : 0x4437,
1007 : 0x4966,
1008 : 0x4967,
1009 : 0x4A48,
1010 : 0x4A49,
1011 : 0x4A4A,
1012 : 0x4A4B,
1013 : 0x4A4C,
1014 : 0x4A4D,
1015 : 0x4A4E,
1016 : 0x4A4F,
1017 : 0x4A50,
1018 : 0x4A54,
1019 : 0x4B48,
1020 : 0x4B49,
1021 : 0x4B4A,
1022 : 0x4B4B,
1023 : 0x4B4C,
1024 : 0x4C57,
1025 : 0x4C58,
1026 : 0x4C59,
1027 : 0x4C5A,
1028 : 0x4C64,
1029 : 0x4C66,
1030 : 0x4C67,
1031 : 0x4E44,
1032 : 0x4E45,
1033 : 0x4E46,
1034 : 0x4E47,
1035 : 0x4E48,
1036 : 0x4E49,
1037 : 0x4E4A,
1038 : 0x4E4B,
1039 : 0x4E50,
1040 : 0x4E51,
1041 : 0x4E52,
1042 : 0x4E53,
1043 : 0x4E54,
1044 : 0x4E56,
1045 : 0x5144,
1046 : 0x5145,
1047 : 0x5146,
1048 : 0x5147,
1049 : 0x5148,
1050 : 0x514C,
1051 : 0x514D,
1052 : 0x5157,
1053 : 0x5158,
1054 : 0x5159,
1055 : 0x515A,
1056 : 0x515E,
1057 : 0x5460,
1058 : 0x5462,
1059 : 0x5464,
1060 : 0x5548,
1061 : 0x5549,
1062 : 0x554A,
1063 : 0x554B,
1064 : 0x554C,
1065 : 0x554D,
1066 : 0x554E,
1067 : 0x554F,
1068 : 0x5550,
1069 : 0x5551,
1070 : 0x5552,
1071 : 0x5554,
1072 : 0x564A,
1073 : 0x564B,
1074 : 0x564F,
1075 : 0x5652,
1076 : 0x5653,
1077 : 0x5657,
1078 : 0x5834,
1079 : 0x5835,
1080 : 0x5954,
1081 : 0x5955,
1082 : 0x5974,
1083 : 0x5975,
1084 : 0x5960,
1085 : 0x5961,
1086 : 0x5962,
1087 : 0x5964,
1088 : 0x5965,
1089 : 0x5969,
1090 : 0x5a41,
1091 : 0x5a42,
1092 : 0x5a61,
1093 : 0x5a62,
1094 : 0x5b60,
1095 : 0x5b62,
1096 : 0x5b63,
1097 : 0x5b64,
1098 : 0x5b65,
1099 : 0x5c61,
1100 : 0x5c63,
1101 : 0x5d48,
1102 : 0x5d49,
1103 : 0x5d4a,
1104 : 0x5d4c,
1105 : 0x5d4d,
1106 : 0x5d4e,
1107 : 0x5d4f,
1108 : 0x5d50,
1109 : 0x5d52,
1110 : 0x5d57,
1111 : 0x5e48,
1112 : 0x5e4a,
1113 : 0x5e4b,
1114 : 0x5e4c,
1115 : 0x5e4d,
1116 : 0x5e4f,
1117 : 0x6700,
1118 : 0x6701,
1119 : 0x6702,
1120 : 0x6703,
1121 : 0x6704,
1122 : 0x6705,
1123 : 0x6706,
1124 : 0x6707,
1125 : 0x6708,
1126 : 0x6709,
1127 : 0x6718,
1128 : 0x6719,
1129 : 0x671c,
1130 : 0x671d,
1131 : 0x671f,
1132 : 0x6720,
1133 : 0x6721,
1134 : 0x6722,
1135 : 0x6723,
1136 : 0x6724,
1137 : 0x6725,
1138 : 0x6726,
1139 : 0x6727,
1140 : 0x6728,
1141 : 0x6729,
1142 : 0x6738,
1143 : 0x6739,
1144 : 0x673e,
1145 : 0x6740,
1146 : 0x6741,
1147 : 0x6742,
1148 : 0x6743,
1149 : 0x6744,
1150 : 0x6745,
1151 : 0x6746,
1152 : 0x6747,
1153 : 0x6748,
1154 : 0x6749,
1155 : 0x674A,
1156 : 0x6750,
1157 : 0x6751,
1158 : 0x6758,
1159 : 0x6759,
1160 : 0x675B,
1161 : 0x675D,
1162 : 0x675F,
1163 : 0x6760,
1164 : 0x6761,
1165 : 0x6762,
1166 : 0x6763,
1167 : 0x6764,
1168 : 0x6765,
1169 : 0x6766,
1170 : 0x6767,
1171 : 0x6768,
1172 : 0x6770,
1173 : 0x6771,
1174 : 0x6772,
1175 : 0x6778,
1176 : 0x6779,
1177 : 0x677B,
1178 : 0x6840,
1179 : 0x6841,
1180 : 0x6842,
1181 : 0x6843,
1182 : 0x6849,
1183 : 0x684C,
1184 : 0x6850,
1185 : 0x6858,
1186 : 0x6859,
1187 : 0x6880,
1188 : 0x6888,
1189 : 0x6889,
1190 : 0x688A,
1191 : 0x688C,
1192 : 0x688D,
1193 : 0x6898,
1194 : 0x6899,
1195 : 0x689b,
1196 : 0x689c,
1197 : 0x689d,
1198 : 0x689e,
1199 : 0x68a0,
1200 : 0x68a1,
1201 : 0x68a8,
1202 : 0x68a9,
1203 : 0x68b0,
1204 : 0x68b8,
1205 : 0x68b9,
1206 : 0x68ba,
1207 : 0x68be,
1208 : 0x68bf,
1209 : 0x68c0,
1210 : 0x68c1,
1211 : 0x68c7,
1212 : 0x68c8,
1213 : 0x68c9,
1214 : 0x68d8,
1215 : 0x68d9,
1216 : 0x68da,
1217 : 0x68de,
1218 : 0x68e0,
1219 : 0x68e1,
1220 : 0x68e4,
1221 : 0x68e5,
1222 : 0x68e8,
1223 : 0x68e9,
1224 : 0x68f1,
1225 : 0x68f2,
1226 : 0x68f8,
1227 : 0x68f9,
1228 : 0x68fa,
1229 : 0x68fe,
1230 : 0x7100,
1231 : 0x7101,
1232 : 0x7102,
1233 : 0x7103,
1234 : 0x7104,
1235 : 0x7105,
1236 : 0x7106,
1237 : 0x7108,
1238 : 0x7109,
1239 : 0x710A,
1240 : 0x710B,
1241 : 0x710C,
1242 : 0x710E,
1243 : 0x710F,
1244 : 0x7140,
1245 : 0x7141,
1246 : 0x7142,
1247 : 0x7143,
1248 : 0x7144,
1249 : 0x7145,
1250 : 0x7146,
1251 : 0x7147,
1252 : 0x7149,
1253 : 0x714A,
1254 : 0x714B,
1255 : 0x714C,
1256 : 0x714D,
1257 : 0x714E,
1258 : 0x714F,
1259 : 0x7151,
1260 : 0x7152,
1261 : 0x7153,
1262 : 0x715E,
1263 : 0x715F,
1264 : 0x7180,
1265 : 0x7181,
1266 : 0x7183,
1267 : 0x7186,
1268 : 0x7187,
1269 : 0x7188,
1270 : 0x718A,
1271 : 0x718B,
1272 : 0x718C,
1273 : 0x718D,
1274 : 0x718F,
1275 : 0x7193,
1276 : 0x7196,
1277 : 0x719B,
1278 : 0x719F,
1279 : 0x71C0,
1280 : 0x71C1,
1281 : 0x71C2,
1282 : 0x71C3,
1283 : 0x71C4,
1284 : 0x71C5,
1285 : 0x71C6,
1286 : 0x71C7,
1287 : 0x71CD,
1288 : 0x71CE,
1289 : 0x71D2,
1290 : 0x71D4,
1291 : 0x71D5,
1292 : 0x71D6,
1293 : 0x71DA,
1294 : 0x71DE,
1295 : 0x7200,
1296 : 0x7210,
1297 : 0x7211,
1298 : 0x7240,
1299 : 0x7243,
1300 : 0x7244,
1301 : 0x7245,
1302 : 0x7246,
1303 : 0x7247,
1304 : 0x7248,
1305 : 0x7249,
1306 : 0x724A,
1307 : 0x724B,
1308 : 0x724C,
1309 : 0x724D,
1310 : 0x724E,
1311 : 0x724F,
1312 : 0x7280,
1313 : 0x7281,
1314 : 0x7283,
1315 : 0x7284,
1316 : 0x7287,
1317 : 0x7288,
1318 : 0x7289,
1319 : 0x728B,
1320 : 0x728C,
1321 : 0x7290,
1322 : 0x7291,
1323 : 0x7293,
1324 : 0x7297,
1325 : 0x7834,
1326 : 0x7835,
1327 : 0x791e,
1328 : 0x791f,
1329 : 0x793f,
1330 : 0x7941,
1331 : 0x7942,
1332 : 0x796c,
1333 : 0x796d,
1334 : 0x796e,
1335 : 0x796f,
1336 : 0x9400,
1337 : 0x9401,
1338 : 0x9402,
1339 : 0x9403,
1340 : 0x9405,
1341 : 0x940A,
1342 : 0x940B,
1343 : 0x940F,
1344 : 0x94A0,
1345 : 0x94A1,
1346 : 0x94A3,
1347 : 0x94B1,
1348 : 0x94B3,
1349 : 0x94B4,
1350 : 0x94B5,
1351 : 0x94B9,
1352 : 0x9440,
1353 : 0x9441,
1354 : 0x9442,
1355 : 0x9443,
1356 : 0x9444,
1357 : 0x9446,
1358 : 0x944A,
1359 : 0x944B,
1360 : 0x944C,
1361 : 0x944E,
1362 : 0x9450,
1363 : 0x9452,
1364 : 0x9456,
1365 : 0x945A,
1366 : 0x945B,
1367 : 0x945E,
1368 : 0x9460,
1369 : 0x9462,
1370 : 0x946A,
1371 : 0x946B,
1372 : 0x947A,
1373 : 0x947B,
1374 : 0x9480,
1375 : 0x9487,
1376 : 0x9488,
1377 : 0x9489,
1378 : 0x948A,
1379 : 0x948F,
1380 : 0x9490,
1381 : 0x9491,
1382 : 0x9495,
1383 : 0x9498,
1384 : 0x949C,
1385 : 0x949E,
1386 : 0x949F,
1387 : 0x94C0,
1388 : 0x94C1,
1389 : 0x94C3,
1390 : 0x94C4,
1391 : 0x94C5,
1392 : 0x94C6,
1393 : 0x94C7,
1394 : 0x94C8,
1395 : 0x94C9,
1396 : 0x94CB,
1397 : 0x94CC,
1398 : 0x94CD,
1399 : 0x9500,
1400 : 0x9501,
1401 : 0x9504,
1402 : 0x9505,
1403 : 0x9506,
1404 : 0x9507,
1405 : 0x9508,
1406 : 0x9509,
1407 : 0x950F,
1408 : 0x9511,
1409 : 0x9515,
1410 : 0x9517,
1411 : 0x9519,
1412 : 0x9540,
1413 : 0x9541,
1414 : 0x9542,
1415 : 0x954E,
1416 : 0x954F,
1417 : 0x9552,
1418 : 0x9553,
1419 : 0x9555,
1420 : 0x9557,
1421 : 0x955f,
1422 : 0x9580,
1423 : 0x9581,
1424 : 0x9583,
1425 : 0x9586,
1426 : 0x9587,
1427 : 0x9588,
1428 : 0x9589,
1429 : 0x958A,
1430 : 0x958B,
1431 : 0x958C,
1432 : 0x958D,
1433 : 0x958E,
1434 : 0x958F,
1435 : 0x9590,
1436 : 0x9591,
1437 : 0x9593,
1438 : 0x9595,
1439 : 0x9596,
1440 : 0x9597,
1441 : 0x9598,
1442 : 0x9599,
1443 : 0x959B,
1444 : 0x95C0,
1445 : 0x95C2,
1446 : 0x95C4,
1447 : 0x95C5,
1448 : 0x95C6,
1449 : 0x95C7,
1450 : 0x95C9,
1451 : 0x95CC,
1452 : 0x95CD,
1453 : 0x95CE,
1454 : 0x95CF,
1455 : 0x9610,
1456 : 0x9611,
1457 : 0x9612,
1458 : 0x9613,
1459 : 0x9614,
1460 : 0x9615,
1461 : 0x9616,
1462 : 0x9640,
1463 : 0x9641,
1464 : 0x9642,
1465 : 0x9643,
1466 : 0x9644,
1467 : 0x9645,
1468 : 0x9647,
1469 : 0x9648,
1470 : 0x9649,
1471 : 0x964a,
1472 : 0x964b,
1473 : 0x964c,
1474 : 0x964e,
1475 : 0x964f,
1476 : 0x9710,
1477 : 0x9711,
1478 : 0x9712,
1479 : 0x9713,
1480 : 0x9714,
1481 : 0x9715,
1482 : 0x9802,
1483 : 0x9803,
1484 : 0x9804,
1485 : 0x9805,
1486 : 0x9806,
1487 : 0x9807,
1488 : 0x9808,
1489 : 0x9809,
1490 : 0x980A,
1491 : 0x9900,
1492 : 0x9901,
1493 : 0x9903,
1494 : 0x9904,
1495 : 0x9905,
1496 : 0x9906,
1497 : 0x9907,
1498 : 0x9908,
1499 : 0x9909,
1500 : 0x990A,
1501 : 0x990B,
1502 : 0x990C,
1503 : 0x990D,
1504 : 0x990E,
1505 : 0x990F,
1506 : 0x9910,
1507 : 0x9913,
1508 : 0x9917,
1509 : 0x9918,
1510 : 0x9919,
1511 : 0x9990,
1512 : 0x9991,
1513 : 0x9992,
1514 : 0x9993,
1515 : 0x9994,
1516 : 0x9995,
1517 : 0x9996,
1518 : 0x9997,
1519 : 0x9998,
1520 : 0x9999,
1521 : 0x999A,
1522 : 0x999B,
1523 : 0x999C,
1524 : 0x999D,
1525 : 0x99A0,
1526 : 0x99A2,
1527 : 0x99A4,
1528 : /* radeon secondary ids */
1529 : 0x3171,
1530 : 0x3e70,
1531 : 0x4164,
1532 : 0x4165,
1533 : 0x4166,
1534 : 0x4168,
1535 : 0x4170,
1536 : 0x4171,
1537 : 0x4172,
1538 : 0x4173,
1539 : 0x496e,
1540 : 0x4a69,
1541 : 0x4a6a,
1542 : 0x4a6b,
1543 : 0x4a70,
1544 : 0x4a74,
1545 : 0x4b69,
1546 : 0x4b6b,
1547 : 0x4b6c,
1548 : 0x4c6e,
1549 : 0x4e64,
1550 : 0x4e65,
1551 : 0x4e66,
1552 : 0x4e67,
1553 : 0x4e68,
1554 : 0x4e69,
1555 : 0x4e6a,
1556 : 0x4e71,
1557 : 0x4f73,
1558 : 0x5569,
1559 : 0x556b,
1560 : 0x556d,
1561 : 0x556f,
1562 : 0x5571,
1563 : 0x5854,
1564 : 0x5874,
1565 : 0x5940,
1566 : 0x5941,
1567 : 0x5b72,
1568 : 0x5b73,
1569 : 0x5b74,
1570 : 0x5b75,
1571 : 0x5d44,
1572 : 0x5d45,
1573 : 0x5d6d,
1574 : 0x5d6f,
1575 : 0x5d72,
1576 : 0x5d77,
1577 : 0x5e6b,
1578 : 0x5e6d,
1579 : 0x7120,
1580 : 0x7124,
1581 : 0x7129,
1582 : 0x712e,
1583 : 0x712f,
1584 : 0x7162,
1585 : 0x7163,
1586 : 0x7166,
1587 : 0x7167,
1588 : 0x7172,
1589 : 0x7173,
1590 : 0x71a0,
1591 : 0x71a1,
1592 : 0x71a3,
1593 : 0x71a7,
1594 : 0x71bb,
1595 : 0x71e0,
1596 : 0x71e1,
1597 : 0x71e2,
1598 : 0x71e6,
1599 : 0x71e7,
1600 : 0x71f2,
1601 : 0x7269,
1602 : 0x726b,
1603 : 0x726e,
1604 : 0x72a0,
1605 : 0x72a8,
1606 : 0x72b1,
1607 : 0x72b3,
1608 : 0x793f,
1609 : };
1610 :
1611 : static const struct pci_device_id pciidlist[] = {
1612 : #ifdef CONFIG_DRM_AMDGPU_SI
1613 : {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1614 : {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1615 : {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1616 : {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1617 : {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1618 : {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1619 : {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1620 : {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1621 : {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1622 : {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1623 : {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1624 : {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1625 : {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1626 : {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1627 : {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1628 : {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1629 : {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1630 : {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1631 : {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1632 : {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1633 : {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1634 : {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1635 : {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1636 : {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1637 : {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1638 : {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1639 : {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1640 : {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1641 : {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1642 : {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1643 : {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1644 : {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1645 : {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1646 : {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1647 : {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1648 : {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1649 : {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1650 : {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1651 : {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1652 : {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1653 : {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1654 : {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1655 : {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1656 : {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1657 : {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1658 : {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1659 : {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1660 : {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1661 : {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1662 : {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1663 : {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1664 : {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1665 : {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1666 : {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1667 : {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1668 : {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1669 : {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1670 : {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1671 : {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1672 : {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1673 : {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1674 : {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1675 : {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1676 : {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1677 : {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1678 : {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1679 : {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1680 : {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1681 : {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1682 : {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1683 : {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1684 : {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1685 : #endif
1686 : #ifdef CONFIG_DRM_AMDGPU_CIK
1687 : /* Kaveri */
1688 : {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1689 : {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1690 : {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1691 : {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1692 : {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1693 : {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1694 : {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1695 : {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1696 : {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1697 : {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1698 : {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1699 : {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1700 : {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1701 : {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1702 : {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1703 : {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1704 : {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1705 : {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1706 : {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1707 : {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1708 : {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1709 : {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1710 : /* Bonaire */
1711 : {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1712 : {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1713 : {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1714 : {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1715 : {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1716 : {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1717 : {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1718 : {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1719 : {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1720 : {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1721 : {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1722 : /* Hawaii */
1723 : {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1724 : {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1725 : {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1726 : {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1727 : {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1728 : {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1729 : {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1730 : {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1731 : {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1732 : {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1733 : {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1734 : {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1735 : /* Kabini */
1736 : {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1737 : {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1738 : {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1739 : {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1740 : {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1741 : {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1742 : {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1743 : {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1744 : {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1745 : {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1746 : {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1747 : {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1748 : {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1749 : {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1750 : {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1751 : {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1752 : /* mullins */
1753 : {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1754 : {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1755 : {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1756 : {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1757 : {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1758 : {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1759 : {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1760 : {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1761 : {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1762 : {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1763 : {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1764 : {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1765 : {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1766 : {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1767 : {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1768 : {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1769 : #endif
1770 : /* topaz */
1771 : {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1772 : {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1773 : {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1774 : {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1775 : {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1776 : /* tonga */
1777 : {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1778 : {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1779 : {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1780 : {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1781 : {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1782 : {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1783 : {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1784 : {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1785 : {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1786 : /* fiji */
1787 : {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1788 : {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1789 : /* carrizo */
1790 : {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1791 : {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1792 : {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1793 : {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1794 : {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1795 : /* stoney */
1796 : {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1797 : /* Polaris11 */
1798 : {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1799 : {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1800 : {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1801 : {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1802 : {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1803 : {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1804 : {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1805 : {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1806 : {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1807 : /* Polaris10 */
1808 : {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1809 : {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1810 : {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1811 : {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1812 : {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1813 : {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1814 : {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1815 : {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1816 : {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1817 : {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1818 : {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1819 : {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1820 : {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1821 : /* Polaris12 */
1822 : {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1823 : {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1824 : {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1825 : {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1826 : {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1827 : {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1828 : {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1829 : {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1830 : /* VEGAM */
1831 : {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1832 : {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1833 : {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1834 : /* Vega 10 */
1835 : {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1836 : {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1837 : {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1838 : {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1839 : {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1840 : {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1841 : {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1842 : {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1843 : {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1844 : {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1845 : {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1846 : {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1847 : {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1848 : {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1849 : {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1850 : /* Vega 12 */
1851 : {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1852 : {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1853 : {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1854 : {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1855 : {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1856 : /* Vega 20 */
1857 : {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1858 : {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1859 : {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1860 : {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1861 : {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1862 : {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1863 : {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1864 : /* Raven */
1865 : {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1866 : {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1867 : /* Arcturus */
1868 : {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1869 : {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1870 : {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1871 : {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1872 : /* Navi10 */
1873 : {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1874 : {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1875 : {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1876 : {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1877 : {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1878 : {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1879 : {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1880 : {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1881 : /* Navi14 */
1882 : {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1883 : {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1884 : {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1885 : {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1886 :
1887 : /* Renoir */
1888 : {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1889 : {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1890 : {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1891 : {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1892 :
1893 : /* Navi12 */
1894 : {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1895 : {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1896 :
1897 : /* Sienna_Cichlid */
1898 : {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1899 : {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1900 : {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1901 : {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1902 : {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1903 : {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1904 : {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1905 : {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1906 : {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1907 : {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1908 : {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1909 : {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1910 : {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1911 :
1912 : /* Van Gogh */
1913 : {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1914 :
1915 : /* Yellow Carp */
1916 : {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1917 : {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1918 :
1919 : /* Navy_Flounder */
1920 : {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1921 : {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1922 : {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1923 : {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1924 : {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1925 : {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1926 : {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1927 : {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1928 : {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1929 :
1930 : /* DIMGREY_CAVEFISH */
1931 : {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1932 : {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1933 : {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1934 : {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1935 : {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1936 : {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1937 : {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1938 : {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1939 : {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1940 : {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1941 : {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1942 : {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1943 :
1944 : /* Aldebaran */
1945 : {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1946 : {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1947 : {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1948 : {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1949 :
1950 : /* CYAN_SKILLFISH */
1951 : {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1952 : {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1953 :
1954 : /* BEIGE_GOBY */
1955 : {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1956 : {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1957 : {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1958 : {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1959 : {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1960 : {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1961 :
1962 : { PCI_DEVICE(0x1002, PCI_ANY_ID),
1963 : .class = PCI_CLASS_DISPLAY_VGA << 8,
1964 : .class_mask = 0xffffff,
1965 : .driver_data = CHIP_IP_DISCOVERY },
1966 :
1967 : { PCI_DEVICE(0x1002, PCI_ANY_ID),
1968 : .class = PCI_CLASS_DISPLAY_OTHER << 8,
1969 : .class_mask = 0xffffff,
1970 : .driver_data = CHIP_IP_DISCOVERY },
1971 :
1972 : {0, 0, 0}
1973 : };
1974 :
1975 : MODULE_DEVICE_TABLE(pci, pciidlist);
1976 :
1977 : static const struct drm_driver amdgpu_kms_driver;
1978 :
1979 0 : static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
1980 : {
1981 0 : struct pci_dev *p = NULL;
1982 : int i;
1983 :
1984 : /* 0 - GPU
1985 : * 1 - audio
1986 : * 2 - USB
1987 : * 3 - UCSI
1988 : */
1989 0 : for (i = 1; i < 4; i++) {
1990 0 : p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1991 0 : adev->pdev->bus->number, i);
1992 0 : if (p) {
1993 0 : pm_runtime_get_sync(&p->dev);
1994 0 : pm_runtime_mark_last_busy(&p->dev);
1995 0 : pm_runtime_put_autosuspend(&p->dev);
1996 0 : pci_dev_put(p);
1997 : }
1998 : }
1999 0 : }
2000 :
2001 0 : static int amdgpu_pci_probe(struct pci_dev *pdev,
2002 : const struct pci_device_id *ent)
2003 : {
2004 : struct drm_device *ddev;
2005 : struct amdgpu_device *adev;
2006 0 : unsigned long flags = ent->driver_data;
2007 0 : int ret, retry = 0, i;
2008 0 : bool supports_atomic = false;
2009 :
2010 : /* skip devices which are owned by radeon */
2011 0 : for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2012 0 : if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2013 : return -ENODEV;
2014 : }
2015 :
2016 0 : if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2017 0 : amdgpu_aspm = 0;
2018 :
2019 0 : if (amdgpu_virtual_display ||
2020 0 : amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2021 : supports_atomic = true;
2022 :
2023 0 : if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2024 0 : DRM_INFO("This hardware requires experimental hardware support.\n"
2025 : "See modparam exp_hw_support\n");
2026 0 : return -ENODEV;
2027 : }
2028 :
2029 : /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2030 : * however, SME requires an indirect IOMMU mapping because the encryption
2031 : * bit is beyond the DMA mask of the chip.
2032 : */
2033 0 : if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2034 : ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2035 : dev_info(&pdev->dev,
2036 : "SME is not compatible with RAVEN\n");
2037 : return -ENOTSUPP;
2038 : }
2039 :
2040 : #ifdef CONFIG_DRM_AMDGPU_SI
2041 : if (!amdgpu_si_support) {
2042 : switch (flags & AMD_ASIC_MASK) {
2043 : case CHIP_TAHITI:
2044 : case CHIP_PITCAIRN:
2045 : case CHIP_VERDE:
2046 : case CHIP_OLAND:
2047 : case CHIP_HAINAN:
2048 : dev_info(&pdev->dev,
2049 : "SI support provided by radeon.\n");
2050 : dev_info(&pdev->dev,
2051 : "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2052 : );
2053 : return -ENODEV;
2054 : }
2055 : }
2056 : #endif
2057 : #ifdef CONFIG_DRM_AMDGPU_CIK
2058 : if (!amdgpu_cik_support) {
2059 : switch (flags & AMD_ASIC_MASK) {
2060 : case CHIP_KAVERI:
2061 : case CHIP_BONAIRE:
2062 : case CHIP_HAWAII:
2063 : case CHIP_KABINI:
2064 : case CHIP_MULLINS:
2065 : dev_info(&pdev->dev,
2066 : "CIK support provided by radeon.\n");
2067 : dev_info(&pdev->dev,
2068 : "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2069 : );
2070 : return -ENODEV;
2071 : }
2072 : }
2073 : #endif
2074 :
2075 : /* Get rid of things like offb */
2076 0 : ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
2077 0 : if (ret)
2078 : return ret;
2079 :
2080 0 : adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2081 0 : if (IS_ERR(adev))
2082 0 : return PTR_ERR(adev);
2083 :
2084 0 : adev->dev = &pdev->dev;
2085 0 : adev->pdev = pdev;
2086 0 : ddev = adev_to_drm(adev);
2087 :
2088 0 : if (!supports_atomic)
2089 0 : ddev->driver_features &= ~DRIVER_ATOMIC;
2090 :
2091 0 : ret = pci_enable_device(pdev);
2092 0 : if (ret)
2093 : return ret;
2094 :
2095 0 : pci_set_drvdata(pdev, ddev);
2096 :
2097 0 : ret = amdgpu_driver_load_kms(adev, ent->driver_data);
2098 0 : if (ret)
2099 : goto err_pci;
2100 :
2101 : retry_init:
2102 0 : ret = drm_dev_register(ddev, ent->driver_data);
2103 0 : if (ret == -EAGAIN && ++retry <= 3) {
2104 0 : DRM_INFO("retry init %d\n", retry);
2105 : /* Don't request EX mode too frequently which is attacking */
2106 0 : msleep(5000);
2107 0 : goto retry_init;
2108 0 : } else if (ret) {
2109 : goto err_pci;
2110 : }
2111 :
2112 : /*
2113 : * 1. don't init fbdev on hw without DCE
2114 : * 2. don't init fbdev if there are no connectors
2115 : */
2116 0 : if (adev->mode_info.mode_config_initialized &&
2117 0 : !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2118 : /* select 8 bpp console on low vram cards */
2119 : if (adev->gmc.real_vram_size <= (32*1024*1024))
2120 : drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2121 : else
2122 : drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2123 : }
2124 :
2125 0 : ret = amdgpu_debugfs_init(adev);
2126 0 : if (ret)
2127 0 : DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2128 :
2129 0 : if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2130 : /* only need to skip on ATPX */
2131 0 : if (amdgpu_device_supports_px(ddev))
2132 0 : dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2133 : /* we want direct complete for BOCO */
2134 0 : if (amdgpu_device_supports_boco(ddev))
2135 0 : dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2136 : DPM_FLAG_SMART_SUSPEND |
2137 : DPM_FLAG_MAY_SKIP_RESUME);
2138 0 : pm_runtime_use_autosuspend(ddev->dev);
2139 0 : pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2140 :
2141 0 : pm_runtime_allow(ddev->dev);
2142 :
2143 0 : pm_runtime_mark_last_busy(ddev->dev);
2144 0 : pm_runtime_put_autosuspend(ddev->dev);
2145 :
2146 : /*
2147 : * For runpm implemented via BACO, PMFW will handle the
2148 : * timing for BACO in and out:
2149 : * - put ASIC into BACO state only when both video and
2150 : * audio functions are in D3 state.
2151 : * - pull ASIC out of BACO state when either video or
2152 : * audio function is in D0 state.
2153 : * Also, at startup, PMFW assumes both functions are in
2154 : * D0 state.
2155 : *
2156 : * So if snd driver was loaded prior to amdgpu driver
2157 : * and audio function was put into D3 state, there will
2158 : * be no PMFW-aware D-state transition(D0->D3) on runpm
2159 : * suspend. Thus the BACO will be not correctly kicked in.
2160 : *
2161 : * Via amdgpu_get_secondary_funcs(), the audio dev is put
2162 : * into D0 state. Then there will be a PMFW-aware D-state
2163 : * transition(D0->D3) on runpm suspend.
2164 : */
2165 0 : if (amdgpu_device_supports_baco(ddev) &&
2166 0 : !(adev->flags & AMD_IS_APU) &&
2167 0 : (adev->asic_type >= CHIP_NAVI10))
2168 0 : amdgpu_get_secondary_funcs(adev);
2169 : }
2170 :
2171 : return 0;
2172 :
2173 : err_pci:
2174 0 : pci_disable_device(pdev);
2175 0 : return ret;
2176 : }
2177 :
2178 : static void
2179 0 : amdgpu_pci_remove(struct pci_dev *pdev)
2180 : {
2181 0 : struct drm_device *dev = pci_get_drvdata(pdev);
2182 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2183 :
2184 0 : if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2185 0 : pm_runtime_get_sync(dev->dev);
2186 0 : pm_runtime_forbid(dev->dev);
2187 : }
2188 :
2189 0 : amdgpu_driver_unload_kms(dev);
2190 :
2191 0 : drm_dev_unplug(dev);
2192 :
2193 : /*
2194 : * Flush any in flight DMA operations from device.
2195 : * Clear the Bus Master Enable bit and then wait on the PCIe Device
2196 : * StatusTransactions Pending bit.
2197 : */
2198 0 : pci_disable_device(pdev);
2199 0 : pci_wait_for_pending_transaction(pdev);
2200 0 : }
2201 :
2202 : static void
2203 0 : amdgpu_pci_shutdown(struct pci_dev *pdev)
2204 : {
2205 0 : struct drm_device *dev = pci_get_drvdata(pdev);
2206 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2207 :
2208 0 : if (amdgpu_ras_intr_triggered())
2209 : return;
2210 :
2211 : /* if we are running in a VM, make sure the device
2212 : * torn down properly on reboot/shutdown.
2213 : * unfortunately we can't detect certain
2214 : * hypervisors so just do this all the time.
2215 : */
2216 0 : if (!amdgpu_passthrough(adev))
2217 0 : adev->mp1_state = PP_MP1_STATE_UNLOAD;
2218 0 : amdgpu_device_ip_suspend(adev);
2219 0 : adev->mp1_state = PP_MP1_STATE_NONE;
2220 : }
2221 :
2222 : /**
2223 : * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2224 : *
2225 : * @work: work_struct.
2226 : */
2227 0 : static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2228 : {
2229 : struct list_head device_list;
2230 : struct amdgpu_device *adev;
2231 : int i, r;
2232 : struct amdgpu_reset_context reset_context;
2233 :
2234 0 : memset(&reset_context, 0, sizeof(reset_context));
2235 :
2236 0 : mutex_lock(&mgpu_info.mutex);
2237 0 : if (mgpu_info.pending_reset == true) {
2238 0 : mutex_unlock(&mgpu_info.mutex);
2239 0 : return;
2240 : }
2241 0 : mgpu_info.pending_reset = true;
2242 0 : mutex_unlock(&mgpu_info.mutex);
2243 :
2244 : /* Use a common context, just need to make sure full reset is done */
2245 0 : reset_context.method = AMD_RESET_METHOD_NONE;
2246 0 : set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2247 :
2248 0 : for (i = 0; i < mgpu_info.num_dgpu; i++) {
2249 0 : adev = mgpu_info.gpu_ins[i].adev;
2250 0 : reset_context.reset_req_dev = adev;
2251 0 : r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2252 0 : if (r) {
2253 0 : dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2254 : r, adev_to_drm(adev)->unique);
2255 : }
2256 0 : if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2257 : r = -EALREADY;
2258 : }
2259 0 : for (i = 0; i < mgpu_info.num_dgpu; i++) {
2260 0 : adev = mgpu_info.gpu_ins[i].adev;
2261 0 : flush_work(&adev->xgmi_reset_work);
2262 0 : adev->gmc.xgmi.pending_reset = false;
2263 : }
2264 :
2265 : /* reset function will rebuild the xgmi hive info , clear it now */
2266 0 : for (i = 0; i < mgpu_info.num_dgpu; i++)
2267 0 : amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2268 :
2269 0 : INIT_LIST_HEAD(&device_list);
2270 :
2271 0 : for (i = 0; i < mgpu_info.num_dgpu; i++)
2272 0 : list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2273 :
2274 : /* unregister the GPU first, reset function will add them back */
2275 0 : list_for_each_entry(adev, &device_list, reset_list)
2276 0 : amdgpu_unregister_gpu_instance(adev);
2277 :
2278 : /* Use a common context, just need to make sure full reset is done */
2279 0 : set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2280 0 : r = amdgpu_do_asic_reset(&device_list, &reset_context);
2281 :
2282 0 : if (r) {
2283 0 : DRM_ERROR("reinit gpus failure");
2284 0 : return;
2285 : }
2286 0 : for (i = 0; i < mgpu_info.num_dgpu; i++) {
2287 0 : adev = mgpu_info.gpu_ins[i].adev;
2288 0 : if (!adev->kfd.init_complete)
2289 0 : amdgpu_amdkfd_device_init(adev);
2290 0 : amdgpu_ttm_set_buffer_funcs_status(adev, true);
2291 : }
2292 : return;
2293 : }
2294 :
2295 0 : static int amdgpu_pmops_prepare(struct device *dev)
2296 : {
2297 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2298 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2299 :
2300 : /* Return a positive number here so
2301 : * DPM_FLAG_SMART_SUSPEND works properly
2302 : */
2303 0 : if (amdgpu_device_supports_boco(drm_dev))
2304 0 : return pm_runtime_suspended(dev);
2305 :
2306 : /* if we will not support s3 or s2i for the device
2307 : * then skip suspend
2308 : */
2309 : if (!amdgpu_acpi_is_s0ix_active(adev) &&
2310 : !amdgpu_acpi_is_s3_active(adev))
2311 : return 1;
2312 :
2313 : return 0;
2314 : }
2315 :
2316 0 : static void amdgpu_pmops_complete(struct device *dev)
2317 : {
2318 : /* nothing to do */
2319 0 : }
2320 :
2321 0 : static int amdgpu_pmops_suspend(struct device *dev)
2322 : {
2323 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2324 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2325 :
2326 : if (amdgpu_acpi_is_s0ix_active(adev))
2327 : adev->in_s0ix = true;
2328 : else
2329 0 : adev->in_s3 = true;
2330 0 : return amdgpu_device_suspend(drm_dev, true);
2331 : }
2332 :
2333 0 : static int amdgpu_pmops_suspend_noirq(struct device *dev)
2334 : {
2335 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2336 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2337 :
2338 : if (amdgpu_acpi_should_gpu_reset(adev))
2339 : return amdgpu_asic_reset(adev);
2340 :
2341 : return 0;
2342 : }
2343 :
2344 0 : static int amdgpu_pmops_resume(struct device *dev)
2345 : {
2346 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2347 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2348 : int r;
2349 :
2350 : /* Avoids registers access if device is physically gone */
2351 0 : if (!pci_device_is_present(adev->pdev))
2352 0 : adev->no_hw_access = true;
2353 :
2354 0 : r = amdgpu_device_resume(drm_dev, true);
2355 : if (amdgpu_acpi_is_s0ix_active(adev))
2356 : adev->in_s0ix = false;
2357 : else
2358 0 : adev->in_s3 = false;
2359 0 : return r;
2360 : }
2361 :
2362 0 : static int amdgpu_pmops_freeze(struct device *dev)
2363 : {
2364 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2365 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2366 : int r;
2367 :
2368 0 : adev->in_s4 = true;
2369 0 : r = amdgpu_device_suspend(drm_dev, true);
2370 0 : adev->in_s4 = false;
2371 0 : if (r)
2372 : return r;
2373 0 : return amdgpu_asic_reset(adev);
2374 : }
2375 :
2376 0 : static int amdgpu_pmops_thaw(struct device *dev)
2377 : {
2378 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2379 :
2380 0 : return amdgpu_device_resume(drm_dev, true);
2381 : }
2382 :
2383 0 : static int amdgpu_pmops_poweroff(struct device *dev)
2384 : {
2385 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2386 :
2387 0 : return amdgpu_device_suspend(drm_dev, true);
2388 : }
2389 :
2390 0 : static int amdgpu_pmops_restore(struct device *dev)
2391 : {
2392 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2393 :
2394 0 : return amdgpu_device_resume(drm_dev, true);
2395 : }
2396 :
2397 0 : static int amdgpu_runtime_idle_check_display(struct device *dev)
2398 : {
2399 0 : struct pci_dev *pdev = to_pci_dev(dev);
2400 0 : struct drm_device *drm_dev = pci_get_drvdata(pdev);
2401 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2402 :
2403 0 : if (adev->mode_info.num_crtc) {
2404 : struct drm_connector *list_connector;
2405 : struct drm_connector_list_iter iter;
2406 0 : int ret = 0;
2407 :
2408 : /* XXX: Return busy if any displays are connected to avoid
2409 : * possible display wakeups after runtime resume due to
2410 : * hotplug events in case any displays were connected while
2411 : * the GPU was in suspend. Remove this once that is fixed.
2412 : */
2413 0 : mutex_lock(&drm_dev->mode_config.mutex);
2414 0 : drm_connector_list_iter_begin(drm_dev, &iter);
2415 0 : drm_for_each_connector_iter(list_connector, &iter) {
2416 0 : if (list_connector->status == connector_status_connected) {
2417 : ret = -EBUSY;
2418 : break;
2419 : }
2420 : }
2421 0 : drm_connector_list_iter_end(&iter);
2422 0 : mutex_unlock(&drm_dev->mode_config.mutex);
2423 :
2424 0 : if (ret)
2425 0 : return ret;
2426 :
2427 0 : if (amdgpu_device_has_dc_support(adev)) {
2428 : struct drm_crtc *crtc;
2429 :
2430 0 : drm_for_each_crtc(crtc, drm_dev) {
2431 0 : drm_modeset_lock(&crtc->mutex, NULL);
2432 0 : if (crtc->state->active)
2433 0 : ret = -EBUSY;
2434 0 : drm_modeset_unlock(&crtc->mutex);
2435 0 : if (ret < 0)
2436 : break;
2437 : }
2438 : } else {
2439 0 : mutex_lock(&drm_dev->mode_config.mutex);
2440 0 : drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2441 :
2442 0 : drm_connector_list_iter_begin(drm_dev, &iter);
2443 0 : drm_for_each_connector_iter(list_connector, &iter) {
2444 0 : if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2445 : ret = -EBUSY;
2446 : break;
2447 : }
2448 : }
2449 :
2450 0 : drm_connector_list_iter_end(&iter);
2451 :
2452 0 : drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2453 0 : mutex_unlock(&drm_dev->mode_config.mutex);
2454 : }
2455 0 : if (ret)
2456 : return ret;
2457 : }
2458 :
2459 : return 0;
2460 : }
2461 :
2462 0 : static int amdgpu_pmops_runtime_suspend(struct device *dev)
2463 : {
2464 0 : struct pci_dev *pdev = to_pci_dev(dev);
2465 0 : struct drm_device *drm_dev = pci_get_drvdata(pdev);
2466 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2467 : int ret, i;
2468 :
2469 0 : if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2470 0 : pm_runtime_forbid(dev);
2471 0 : return -EBUSY;
2472 : }
2473 :
2474 0 : ret = amdgpu_runtime_idle_check_display(dev);
2475 0 : if (ret)
2476 : return ret;
2477 :
2478 : /* wait for all rings to drain before suspending */
2479 0 : for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2480 0 : struct amdgpu_ring *ring = adev->rings[i];
2481 0 : if (ring && ring->sched.ready) {
2482 0 : ret = amdgpu_fence_wait_empty(ring);
2483 0 : if (ret)
2484 : return -EBUSY;
2485 : }
2486 : }
2487 :
2488 0 : adev->in_runpm = true;
2489 0 : if (amdgpu_device_supports_px(drm_dev))
2490 0 : drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2491 :
2492 : /*
2493 : * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2494 : * proper cleanups and put itself into a state ready for PNP. That
2495 : * can address some random resuming failure observed on BOCO capable
2496 : * platforms.
2497 : * TODO: this may be also needed for PX capable platform.
2498 : */
2499 0 : if (amdgpu_device_supports_boco(drm_dev))
2500 0 : adev->mp1_state = PP_MP1_STATE_UNLOAD;
2501 :
2502 0 : ret = amdgpu_device_suspend(drm_dev, false);
2503 0 : if (ret) {
2504 0 : adev->in_runpm = false;
2505 0 : if (amdgpu_device_supports_boco(drm_dev))
2506 0 : adev->mp1_state = PP_MP1_STATE_NONE;
2507 : return ret;
2508 : }
2509 :
2510 0 : if (amdgpu_device_supports_boco(drm_dev))
2511 0 : adev->mp1_state = PP_MP1_STATE_NONE;
2512 :
2513 0 : if (amdgpu_device_supports_px(drm_dev)) {
2514 : /* Only need to handle PCI state in the driver for ATPX
2515 : * PCI core handles it for _PR3.
2516 : */
2517 0 : amdgpu_device_cache_pci_state(pdev);
2518 0 : pci_disable_device(pdev);
2519 0 : pci_ignore_hotplug(pdev);
2520 0 : pci_set_power_state(pdev, PCI_D3cold);
2521 0 : drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2522 0 : } else if (amdgpu_device_supports_boco(drm_dev)) {
2523 : /* nothing to do */
2524 0 : } else if (amdgpu_device_supports_baco(drm_dev)) {
2525 0 : amdgpu_device_baco_enter(drm_dev);
2526 : }
2527 :
2528 : return 0;
2529 : }
2530 :
2531 0 : static int amdgpu_pmops_runtime_resume(struct device *dev)
2532 : {
2533 0 : struct pci_dev *pdev = to_pci_dev(dev);
2534 0 : struct drm_device *drm_dev = pci_get_drvdata(pdev);
2535 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2536 : int ret;
2537 :
2538 0 : if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2539 : return -EINVAL;
2540 :
2541 : /* Avoids registers access if device is physically gone */
2542 0 : if (!pci_device_is_present(adev->pdev))
2543 0 : adev->no_hw_access = true;
2544 :
2545 0 : if (amdgpu_device_supports_px(drm_dev)) {
2546 0 : drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2547 :
2548 : /* Only need to handle PCI state in the driver for ATPX
2549 : * PCI core handles it for _PR3.
2550 : */
2551 0 : pci_set_power_state(pdev, PCI_D0);
2552 0 : amdgpu_device_load_pci_state(pdev);
2553 0 : ret = pci_enable_device(pdev);
2554 0 : if (ret)
2555 : return ret;
2556 0 : pci_set_master(pdev);
2557 0 : } else if (amdgpu_device_supports_boco(drm_dev)) {
2558 : /* Only need to handle PCI state in the driver for ATPX
2559 : * PCI core handles it for _PR3.
2560 : */
2561 0 : pci_set_master(pdev);
2562 0 : } else if (amdgpu_device_supports_baco(drm_dev)) {
2563 0 : amdgpu_device_baco_exit(drm_dev);
2564 : }
2565 0 : ret = amdgpu_device_resume(drm_dev, false);
2566 0 : if (ret) {
2567 0 : if (amdgpu_device_supports_px(drm_dev))
2568 0 : pci_disable_device(pdev);
2569 : return ret;
2570 : }
2571 :
2572 0 : if (amdgpu_device_supports_px(drm_dev))
2573 0 : drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2574 0 : adev->in_runpm = false;
2575 0 : return 0;
2576 : }
2577 :
2578 0 : static int amdgpu_pmops_runtime_idle(struct device *dev)
2579 : {
2580 0 : struct drm_device *drm_dev = dev_get_drvdata(dev);
2581 0 : struct amdgpu_device *adev = drm_to_adev(drm_dev);
2582 : /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2583 0 : int ret = 1;
2584 :
2585 0 : if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2586 0 : pm_runtime_forbid(dev);
2587 0 : return -EBUSY;
2588 : }
2589 :
2590 0 : ret = amdgpu_runtime_idle_check_display(dev);
2591 :
2592 0 : pm_runtime_mark_last_busy(dev);
2593 0 : pm_runtime_autosuspend(dev);
2594 0 : return ret;
2595 : }
2596 :
2597 0 : long amdgpu_drm_ioctl(struct file *filp,
2598 : unsigned int cmd, unsigned long arg)
2599 : {
2600 0 : struct drm_file *file_priv = filp->private_data;
2601 : struct drm_device *dev;
2602 : long ret;
2603 0 : dev = file_priv->minor->dev;
2604 0 : ret = pm_runtime_get_sync(dev->dev);
2605 0 : if (ret < 0)
2606 : goto out;
2607 :
2608 0 : ret = drm_ioctl(filp, cmd, arg);
2609 :
2610 0 : pm_runtime_mark_last_busy(dev->dev);
2611 : out:
2612 0 : pm_runtime_put_autosuspend(dev->dev);
2613 0 : return ret;
2614 : }
2615 :
2616 : static const struct dev_pm_ops amdgpu_pm_ops = {
2617 : .prepare = amdgpu_pmops_prepare,
2618 : .complete = amdgpu_pmops_complete,
2619 : .suspend = amdgpu_pmops_suspend,
2620 : .suspend_noirq = amdgpu_pmops_suspend_noirq,
2621 : .resume = amdgpu_pmops_resume,
2622 : .freeze = amdgpu_pmops_freeze,
2623 : .thaw = amdgpu_pmops_thaw,
2624 : .poweroff = amdgpu_pmops_poweroff,
2625 : .restore = amdgpu_pmops_restore,
2626 : .runtime_suspend = amdgpu_pmops_runtime_suspend,
2627 : .runtime_resume = amdgpu_pmops_runtime_resume,
2628 : .runtime_idle = amdgpu_pmops_runtime_idle,
2629 : };
2630 :
2631 0 : static int amdgpu_flush(struct file *f, fl_owner_t id)
2632 : {
2633 0 : struct drm_file *file_priv = f->private_data;
2634 0 : struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2635 0 : long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2636 :
2637 0 : timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2638 0 : timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2639 :
2640 0 : return timeout >= 0 ? 0 : timeout;
2641 : }
2642 :
2643 : static const struct file_operations amdgpu_driver_kms_fops = {
2644 : .owner = THIS_MODULE,
2645 : .open = drm_open,
2646 : .flush = amdgpu_flush,
2647 : .release = drm_release,
2648 : .unlocked_ioctl = amdgpu_drm_ioctl,
2649 : .mmap = drm_gem_mmap,
2650 : .poll = drm_poll,
2651 : .read = drm_read,
2652 : #ifdef CONFIG_COMPAT
2653 : .compat_ioctl = amdgpu_kms_compat_ioctl,
2654 : #endif
2655 : #ifdef CONFIG_PROC_FS
2656 : .show_fdinfo = amdgpu_show_fdinfo
2657 : #endif
2658 : };
2659 :
2660 0 : int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2661 : {
2662 : struct drm_file *file;
2663 :
2664 0 : if (!filp)
2665 : return -EINVAL;
2666 :
2667 0 : if (filp->f_op != &amdgpu_driver_kms_fops) {
2668 : return -EINVAL;
2669 : }
2670 :
2671 0 : file = filp->private_data;
2672 0 : *fpriv = file->driver_priv;
2673 0 : return 0;
2674 : }
2675 :
2676 : const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2677 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2678 : DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2679 : DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2680 : DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2681 : DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2682 : DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2683 : /* KMS */
2684 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2685 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2686 : DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2687 : DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2688 : DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2689 : DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2690 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2691 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2692 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2693 : DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2694 : };
2695 :
2696 : static const struct drm_driver amdgpu_kms_driver = {
2697 : .driver_features =
2698 : DRIVER_ATOMIC |
2699 : DRIVER_GEM |
2700 : DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2701 : DRIVER_SYNCOBJ_TIMELINE,
2702 : .open = amdgpu_driver_open_kms,
2703 : .postclose = amdgpu_driver_postclose_kms,
2704 : .lastclose = amdgpu_driver_lastclose_kms,
2705 : .ioctls = amdgpu_ioctls_kms,
2706 : .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2707 : .dumb_create = amdgpu_mode_dumb_create,
2708 : .dumb_map_offset = amdgpu_mode_dumb_mmap,
2709 : .fops = &amdgpu_driver_kms_fops,
2710 : .release = &amdgpu_driver_release_kms,
2711 :
2712 : .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2713 : .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2714 : .gem_prime_import = amdgpu_gem_prime_import,
2715 : .gem_prime_mmap = drm_gem_prime_mmap,
2716 :
2717 : .name = DRIVER_NAME,
2718 : .desc = DRIVER_DESC,
2719 : .date = DRIVER_DATE,
2720 : .major = KMS_DRIVER_MAJOR,
2721 : .minor = KMS_DRIVER_MINOR,
2722 : .patchlevel = KMS_DRIVER_PATCHLEVEL,
2723 : };
2724 :
2725 : static struct pci_error_handlers amdgpu_pci_err_handler = {
2726 : .error_detected = amdgpu_pci_error_detected,
2727 : .mmio_enabled = amdgpu_pci_mmio_enabled,
2728 : .slot_reset = amdgpu_pci_slot_reset,
2729 : .resume = amdgpu_pci_resume,
2730 : };
2731 :
2732 : extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2733 : extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2734 : extern const struct attribute_group amdgpu_vbios_version_attr_group;
2735 :
2736 : static const struct attribute_group *amdgpu_sysfs_groups[] = {
2737 : &amdgpu_vram_mgr_attr_group,
2738 : &amdgpu_gtt_mgr_attr_group,
2739 : &amdgpu_vbios_version_attr_group,
2740 : NULL,
2741 : };
2742 :
2743 :
2744 : static struct pci_driver amdgpu_kms_pci_driver = {
2745 : .name = DRIVER_NAME,
2746 : .id_table = pciidlist,
2747 : .probe = amdgpu_pci_probe,
2748 : .remove = amdgpu_pci_remove,
2749 : .shutdown = amdgpu_pci_shutdown,
2750 : .driver.pm = &amdgpu_pm_ops,
2751 : .err_handler = &amdgpu_pci_err_handler,
2752 : .dev_groups = amdgpu_sysfs_groups,
2753 : };
2754 :
2755 1 : static int __init amdgpu_init(void)
2756 : {
2757 : int r;
2758 :
2759 1 : if (drm_firmware_drivers_only())
2760 : return -EINVAL;
2761 :
2762 1 : r = amdgpu_sync_init();
2763 1 : if (r)
2764 : goto error_sync;
2765 :
2766 1 : r = amdgpu_fence_slab_init();
2767 1 : if (r)
2768 : goto error_fence;
2769 :
2770 1 : DRM_INFO("amdgpu kernel modesetting enabled.\n");
2771 : amdgpu_register_atpx_handler();
2772 : amdgpu_acpi_detect();
2773 :
2774 : /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2775 1 : amdgpu_amdkfd_init();
2776 :
2777 : /* let modprobe override vga console setting */
2778 1 : return pci_register_driver(&amdgpu_kms_pci_driver);
2779 :
2780 : error_fence:
2781 0 : amdgpu_sync_fini();
2782 :
2783 : error_sync:
2784 : return r;
2785 : }
2786 :
2787 0 : static void __exit amdgpu_exit(void)
2788 : {
2789 0 : amdgpu_amdkfd_fini();
2790 0 : pci_unregister_driver(&amdgpu_kms_pci_driver);
2791 : amdgpu_unregister_atpx_handler();
2792 0 : amdgpu_sync_fini();
2793 0 : amdgpu_fence_slab_fini();
2794 : mmu_notifier_synchronize();
2795 0 : }
2796 :
2797 : module_init(amdgpu_init);
2798 : module_exit(amdgpu_exit);
2799 :
2800 : MODULE_AUTHOR(DRIVER_AUTHOR);
2801 : MODULE_DESCRIPTION(DRIVER_DESC);
2802 : MODULE_LICENSE("GPL and additional rights");
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