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1 : /*
2 : * Copyright 2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include "amdgpu_eeprom.h"
25 : #include "amdgpu.h"
26 :
27 : /* AT24CM02 and M24M02-R have a 256-byte write page size.
28 : */
29 : #define EEPROM_PAGE_BITS 8
30 : #define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)
31 : #define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
32 :
33 : #define EEPROM_OFFSET_SIZE 2
34 :
35 : /* EEPROM memory addresses are 19-bits long, which can
36 : * be partitioned into 3, 8, 8 bits, for a total of 19.
37 : * The upper 3 bits are sent as part of the 7-bit
38 : * "Device Type Identifier"--an I2C concept, which for EEPROM devices
39 : * is hard-coded as 1010b, indicating that it is an EEPROM
40 : * device--this is the wire format, followed by the upper
41 : * 3 bits of the 19-bit address, followed by the direction,
42 : * followed by two bytes holding the rest of the 16-bits of
43 : * the EEPROM memory address. The format on the wire for EEPROM
44 : * devices is: 1010XYZD, A15:A8, A7:A0,
45 : * Where D is the direction and sequenced out by the hardware.
46 : * Bits XYZ are memory address bits 18, 17 and 16.
47 : * These bits are compared to how pins 1-3 of the part are connected,
48 : * depending on the size of the part, more on that later.
49 : *
50 : * Note that of this wire format, a client is in control
51 : * of, and needs to specify only XYZ, A15:A8, A7:0, bits,
52 : * which is exactly the EEPROM memory address, or offset,
53 : * in order to address up to 8 EEPROM devices on the I2C bus.
54 : *
55 : * For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes,
56 : * using an 18-bit address, bit 17 to 0 and thus would use all but one bit of
57 : * the 19 bits previously mentioned. The designer would then not connect
58 : * pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to
59 : * either Vcc or GND. This would allow for up to two 2-Mbit parts on
60 : * the same bus, where one would be addressable with bit 18 as 1, and
61 : * the other with bit 18 of the address as 0.
62 : *
63 : * For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or
64 : * "Hardware Address Bit". This bit is compared to the load on pin 3
65 : * of the device, described above, and if there is a match, then this
66 : * device responds to the command. This way, you can connect two
67 : * 2-Mbit EEPROM devices on the same bus, but see one contiguous
68 : * memory from 0 to 7FFFFh, where address 0 to 3FFFF is in the device
69 : * whose pin 3 is connected to GND, and address 40000 to 7FFFFh is in
70 : * the 2nd device, whose pin 3 is connected to Vcc.
71 : *
72 : * This addressing you encode in the 32-bit "eeprom_addr" below,
73 : * namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For
74 : * instance, eeprom_addr = 0x6DA01, is 110_1101_1010_0000_0001, where
75 : * XYZ=110b, and A15:A0=DA01h. The XYZ bits become part of the device
76 : * address, and the rest of the address bits are sent as the memory
77 : * address bytes.
78 : *
79 : * That is, for an I2C EEPROM driver everything is controlled by
80 : * the "eeprom_addr".
81 : *
82 : * P.S. If you need to write, lock and read the Identification Page,
83 : * (M24M02-DR device only, which we do not use), change the "7" to
84 : * "0xF" in the macro below, and let the client set bit 20 to 1 in
85 : * "eeprom_addr", and set A10 to 0 to write into it, and A10 and A1 to
86 : * 1 to lock it permanently.
87 : */
88 : #define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 7))
89 :
90 0 : static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
91 : u8 *eeprom_buf, u16 buf_size, bool read)
92 : {
93 : u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
94 0 : struct i2c_msg msgs[] = {
95 : {
96 : .flags = 0,
97 : .len = EEPROM_OFFSET_SIZE,
98 : .buf = eeprom_offset_buf,
99 : },
100 : {
101 0 : .flags = read ? I2C_M_RD : 0,
102 : },
103 : };
104 0 : const u8 *p = eeprom_buf;
105 : int r;
106 : u16 len;
107 :
108 0 : for (r = 0; buf_size > 0;
109 0 : buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
110 : /* Set the EEPROM address we want to write to/read from.
111 : */
112 0 : msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr);
113 0 : msgs[1].addr = msgs[0].addr;
114 0 : msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;
115 0 : msgs[0].buf[1] = eeprom_addr & 0xff;
116 :
117 0 : if (!read) {
118 : /* Write the maximum amount of data, without
119 : * crossing the device's page boundary, as per
120 : * its spec. Partial page writes are allowed,
121 : * starting at any location within the page,
122 : * so long as the page boundary isn't crossed
123 : * over (actually the page pointer rolls
124 : * over).
125 : *
126 : * As per the AT24CM02 EEPROM spec, after
127 : * writing into a page, the I2C driver should
128 : * terminate the transfer, i.e. in
129 : * "i2c_transfer()" below, with a STOP
130 : * condition, so that the self-timed write
131 : * cycle begins. This is implied for the
132 : * "i2c_transfer()" abstraction.
133 : */
134 0 : len = min(EEPROM_PAGE_SIZE - (eeprom_addr &
135 : EEPROM_PAGE_MASK),
136 : (u32)buf_size);
137 : } else {
138 : /* Reading from the EEPROM has no limitation
139 : * on the number of bytes read from the EEPROM
140 : * device--they are simply sequenced out.
141 : */
142 : len = buf_size;
143 : }
144 0 : msgs[1].len = len;
145 0 : msgs[1].buf = eeprom_buf;
146 :
147 : /* This constitutes a START-STOP transaction.
148 : */
149 0 : r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));
150 0 : if (r != ARRAY_SIZE(msgs))
151 : break;
152 :
153 0 : if (!read) {
154 : /* According to EEPROM specs the length of the
155 : * self-writing cycle, tWR (tW), is 10 ms.
156 : *
157 : * TODO: Use polling on ACK, aka Acknowledge
158 : * Polling, to minimize waiting for the
159 : * internal write cycle to complete, as it is
160 : * usually smaller than tWR (tW).
161 : */
162 0 : msleep(10);
163 : }
164 : }
165 :
166 0 : return r < 0 ? r : eeprom_buf - p;
167 : }
168 :
169 : /**
170 : * amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device
171 : * @i2c_adap: pointer to the I2C adapter to use
172 : * @eeprom_addr: EEPROM address from which to read/write
173 : * @eeprom_buf: pointer to data buffer to read into/write from
174 : * @buf_size: the size of @eeprom_buf
175 : * @read: True if reading from the EEPROM, false if writing
176 : *
177 : * Returns the number of bytes read/written; -errno on error.
178 : */
179 0 : static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
180 : u8 *eeprom_buf, u16 buf_size, bool read)
181 : {
182 0 : const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;
183 : u16 limit;
184 :
185 0 : if (!quirks)
186 : limit = 0;
187 0 : else if (read)
188 0 : limit = quirks->max_read_len;
189 : else
190 0 : limit = quirks->max_write_len;
191 :
192 0 : if (limit == 0) {
193 0 : return __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
194 : eeprom_buf, buf_size, read);
195 0 : } else if (limit <= EEPROM_OFFSET_SIZE) {
196 0 : dev_err_ratelimited(&i2c_adap->dev,
197 : "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d",
198 : eeprom_addr, buf_size,
199 : read ? "read" : "write", EEPROM_OFFSET_SIZE);
200 : return -EINVAL;
201 : } else {
202 : u16 ps; /* Partial size */
203 0 : int res = 0, r;
204 :
205 : /* The "limit" includes all data bytes sent/received,
206 : * which would include the EEPROM_OFFSET_SIZE bytes.
207 : * Account for them here.
208 : */
209 0 : limit -= EEPROM_OFFSET_SIZE;
210 0 : for ( ; buf_size > 0;
211 0 : buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {
212 0 : ps = min(limit, buf_size);
213 :
214 0 : r = __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
215 : eeprom_buf, ps, read);
216 0 : if (r < 0)
217 : return r;
218 0 : res += r;
219 : }
220 :
221 : return res;
222 : }
223 : }
224 :
225 0 : int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
226 : u32 eeprom_addr, u8 *eeprom_buf,
227 : u16 bytes)
228 : {
229 0 : return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
230 : true);
231 : }
232 :
233 0 : int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
234 : u32 eeprom_addr, u8 *eeprom_buf,
235 : u16 bytes)
236 : {
237 0 : return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
238 : false);
239 : }
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