Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 :
29 : #include "amdgpu.h"
30 : #include <drm/amdgpu_drm.h>
31 : #include <drm/drm_drv.h>
32 : #include "amdgpu_uvd.h"
33 : #include "amdgpu_vce.h"
34 : #include "atom.h"
35 :
36 : #include <linux/vga_switcheroo.h>
37 : #include <linux/slab.h>
38 : #include <linux/uaccess.h>
39 : #include <linux/pci.h>
40 : #include <linux/pm_runtime.h>
41 : #include "amdgpu_amdkfd.h"
42 : #include "amdgpu_gem.h"
43 : #include "amdgpu_display.h"
44 : #include "amdgpu_ras.h"
45 :
46 0 : void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
47 : {
48 : struct amdgpu_gpu_instance *gpu_instance;
49 : int i;
50 :
51 0 : mutex_lock(&mgpu_info.mutex);
52 :
53 0 : for (i = 0; i < mgpu_info.num_gpu; i++) {
54 0 : gpu_instance = &(mgpu_info.gpu_ins[i]);
55 0 : if (gpu_instance->adev == adev) {
56 0 : mgpu_info.gpu_ins[i] =
57 0 : mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
58 0 : mgpu_info.num_gpu--;
59 0 : if (adev->flags & AMD_IS_APU)
60 0 : mgpu_info.num_apu--;
61 : else
62 0 : mgpu_info.num_dgpu--;
63 : break;
64 : }
65 : }
66 :
67 0 : mutex_unlock(&mgpu_info.mutex);
68 0 : }
69 :
70 : /**
71 : * amdgpu_driver_unload_kms - Main unload function for KMS.
72 : *
73 : * @dev: drm dev pointer
74 : *
75 : * This is the main unload function for KMS (all asics).
76 : * Returns 0 on success.
77 : */
78 0 : void amdgpu_driver_unload_kms(struct drm_device *dev)
79 : {
80 0 : struct amdgpu_device *adev = drm_to_adev(dev);
81 :
82 0 : if (adev == NULL)
83 : return;
84 :
85 0 : amdgpu_unregister_gpu_instance(adev);
86 :
87 0 : if (adev->rmmio == NULL)
88 : return;
89 :
90 0 : if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
91 : DRM_WARN("smart shift update failed\n");
92 :
93 : amdgpu_acpi_fini(adev);
94 0 : amdgpu_device_fini_hw(adev);
95 : }
96 :
97 0 : void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
98 : {
99 : struct amdgpu_gpu_instance *gpu_instance;
100 :
101 0 : mutex_lock(&mgpu_info.mutex);
102 :
103 0 : if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
104 0 : DRM_ERROR("Cannot register more gpu instance\n");
105 0 : mutex_unlock(&mgpu_info.mutex);
106 0 : return;
107 : }
108 :
109 0 : gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
110 0 : gpu_instance->adev = adev;
111 0 : gpu_instance->mgpu_fan_enabled = 0;
112 :
113 0 : mgpu_info.num_gpu++;
114 0 : if (adev->flags & AMD_IS_APU)
115 0 : mgpu_info.num_apu++;
116 : else
117 0 : mgpu_info.num_dgpu++;
118 :
119 0 : mutex_unlock(&mgpu_info.mutex);
120 : }
121 :
122 : /**
123 : * amdgpu_driver_load_kms - Main load function for KMS.
124 : *
125 : * @adev: pointer to struct amdgpu_device
126 : * @flags: device flags
127 : *
128 : * This is the main load function for KMS (all asics).
129 : * Returns 0 on success, error on failure.
130 : */
131 0 : int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
132 : {
133 : struct drm_device *dev;
134 : int r, acpi_status;
135 :
136 0 : dev = adev_to_drm(adev);
137 :
138 : /* amdgpu_device_init should report only fatal error
139 : * like memory allocation failure or iomapping failure,
140 : * or memory manager initialization failure, it must
141 : * properly initialize the GPU MC controller and permit
142 : * VRAM allocation
143 : */
144 0 : r = amdgpu_device_init(adev, flags);
145 0 : if (r) {
146 0 : dev_err(dev->dev, "Fatal error during GPU init\n");
147 0 : goto out;
148 : }
149 :
150 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
151 0 : if (amdgpu_device_supports_px(dev) &&
152 0 : (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
153 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
154 0 : dev_info(adev->dev, "Using ATPX for runtime pm\n");
155 0 : } else if (amdgpu_device_supports_boco(dev) &&
156 0 : (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
157 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
158 0 : dev_info(adev->dev, "Using BOCO for runtime pm\n");
159 0 : } else if (amdgpu_device_supports_baco(dev) &&
160 0 : (amdgpu_runtime_pm != 0)) {
161 0 : switch (adev->asic_type) {
162 : case CHIP_VEGA20:
163 : case CHIP_ARCTURUS:
164 : /* enable BACO as runpm mode if runpm=1 */
165 0 : if (amdgpu_runtime_pm > 0)
166 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
167 : break;
168 : case CHIP_VEGA10:
169 : /* enable BACO as runpm mode if noretry=0 */
170 0 : if (!adev->gmc.noretry)
171 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
172 : break;
173 : default:
174 : /* enable BACO as runpm mode on CI+ */
175 0 : adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
176 0 : break;
177 : }
178 :
179 0 : if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
180 0 : dev_info(adev->dev, "Using BACO for runtime pm\n");
181 : }
182 :
183 : /* Call ACPI methods: require modeset init
184 : * but failure is not fatal
185 : */
186 :
187 : acpi_status = amdgpu_acpi_init(adev);
188 : if (acpi_status)
189 : dev_dbg(dev->dev, "Error during ACPI methods call\n");
190 :
191 : if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
192 : DRM_WARN("smart shift update failed\n");
193 :
194 : out:
195 0 : if (r)
196 0 : amdgpu_driver_unload_kms(dev);
197 :
198 0 : return r;
199 : }
200 :
201 0 : static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
202 : struct drm_amdgpu_query_fw *query_fw,
203 : struct amdgpu_device *adev)
204 : {
205 0 : switch (query_fw->fw_type) {
206 : case AMDGPU_INFO_FW_VCE:
207 0 : fw_info->ver = adev->vce.fw_version;
208 0 : fw_info->feature = adev->vce.fb_version;
209 : break;
210 : case AMDGPU_INFO_FW_UVD:
211 0 : fw_info->ver = adev->uvd.fw_version;
212 0 : fw_info->feature = 0;
213 : break;
214 : case AMDGPU_INFO_FW_VCN:
215 0 : fw_info->ver = adev->vcn.fw_version;
216 0 : fw_info->feature = 0;
217 : break;
218 : case AMDGPU_INFO_FW_GMC:
219 0 : fw_info->ver = adev->gmc.fw_version;
220 0 : fw_info->feature = 0;
221 : break;
222 : case AMDGPU_INFO_FW_GFX_ME:
223 0 : fw_info->ver = adev->gfx.me_fw_version;
224 0 : fw_info->feature = adev->gfx.me_feature_version;
225 : break;
226 : case AMDGPU_INFO_FW_GFX_PFP:
227 0 : fw_info->ver = adev->gfx.pfp_fw_version;
228 0 : fw_info->feature = adev->gfx.pfp_feature_version;
229 : break;
230 : case AMDGPU_INFO_FW_GFX_CE:
231 0 : fw_info->ver = adev->gfx.ce_fw_version;
232 0 : fw_info->feature = adev->gfx.ce_feature_version;
233 : break;
234 : case AMDGPU_INFO_FW_GFX_RLC:
235 0 : fw_info->ver = adev->gfx.rlc_fw_version;
236 0 : fw_info->feature = adev->gfx.rlc_feature_version;
237 : break;
238 : case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
239 0 : fw_info->ver = adev->gfx.rlc_srlc_fw_version;
240 0 : fw_info->feature = adev->gfx.rlc_srlc_feature_version;
241 : break;
242 : case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
243 0 : fw_info->ver = adev->gfx.rlc_srlg_fw_version;
244 0 : fw_info->feature = adev->gfx.rlc_srlg_feature_version;
245 : break;
246 : case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
247 0 : fw_info->ver = adev->gfx.rlc_srls_fw_version;
248 0 : fw_info->feature = adev->gfx.rlc_srls_feature_version;
249 : break;
250 : case AMDGPU_INFO_FW_GFX_MEC:
251 0 : if (query_fw->index == 0) {
252 0 : fw_info->ver = adev->gfx.mec_fw_version;
253 0 : fw_info->feature = adev->gfx.mec_feature_version;
254 0 : } else if (query_fw->index == 1) {
255 0 : fw_info->ver = adev->gfx.mec2_fw_version;
256 0 : fw_info->feature = adev->gfx.mec2_feature_version;
257 : } else
258 : return -EINVAL;
259 : break;
260 : case AMDGPU_INFO_FW_SMC:
261 0 : fw_info->ver = adev->pm.fw_version;
262 0 : fw_info->feature = 0;
263 : break;
264 : case AMDGPU_INFO_FW_TA:
265 0 : switch (query_fw->index) {
266 : case TA_FW_TYPE_PSP_XGMI:
267 0 : fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
268 0 : fw_info->feature = adev->psp.xgmi_context.context
269 0 : .bin_desc.feature_version;
270 : break;
271 : case TA_FW_TYPE_PSP_RAS:
272 0 : fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
273 0 : fw_info->feature = adev->psp.ras_context.context
274 0 : .bin_desc.feature_version;
275 : break;
276 : case TA_FW_TYPE_PSP_HDCP:
277 0 : fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
278 0 : fw_info->feature = adev->psp.hdcp_context.context
279 0 : .bin_desc.feature_version;
280 : break;
281 : case TA_FW_TYPE_PSP_DTM:
282 0 : fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
283 0 : fw_info->feature = adev->psp.dtm_context.context
284 0 : .bin_desc.feature_version;
285 : break;
286 : case TA_FW_TYPE_PSP_RAP:
287 0 : fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
288 0 : fw_info->feature = adev->psp.rap_context.context
289 0 : .bin_desc.feature_version;
290 : break;
291 : case TA_FW_TYPE_PSP_SECUREDISPLAY:
292 0 : fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
293 0 : fw_info->feature =
294 : adev->psp.securedisplay_context.context.bin_desc
295 0 : .feature_version;
296 : break;
297 : default:
298 : return -EINVAL;
299 : }
300 : break;
301 : case AMDGPU_INFO_FW_SDMA:
302 0 : if (query_fw->index >= adev->sdma.num_instances)
303 : return -EINVAL;
304 0 : fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
305 0 : fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
306 : break;
307 : case AMDGPU_INFO_FW_SOS:
308 0 : fw_info->ver = adev->psp.sos.fw_version;
309 0 : fw_info->feature = adev->psp.sos.feature_version;
310 : break;
311 : case AMDGPU_INFO_FW_ASD:
312 0 : fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
313 0 : fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
314 : break;
315 : case AMDGPU_INFO_FW_DMCU:
316 0 : fw_info->ver = adev->dm.dmcu_fw_version;
317 0 : fw_info->feature = 0;
318 : break;
319 : case AMDGPU_INFO_FW_DMCUB:
320 0 : fw_info->ver = adev->dm.dmcub_fw_version;
321 0 : fw_info->feature = 0;
322 : break;
323 : case AMDGPU_INFO_FW_TOC:
324 0 : fw_info->ver = adev->psp.toc.fw_version;
325 0 : fw_info->feature = adev->psp.toc.feature_version;
326 : break;
327 : case AMDGPU_INFO_FW_CAP:
328 0 : fw_info->ver = adev->psp.cap_fw_version;
329 0 : fw_info->feature = adev->psp.cap_feature_version;
330 : break;
331 : default:
332 : return -EINVAL;
333 : }
334 : return 0;
335 : }
336 :
337 0 : static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
338 : struct drm_amdgpu_info *info,
339 : struct drm_amdgpu_info_hw_ip *result)
340 : {
341 0 : uint32_t ib_start_alignment = 0;
342 0 : uint32_t ib_size_alignment = 0;
343 : enum amd_ip_block_type type;
344 0 : unsigned int num_rings = 0;
345 : unsigned int i, j;
346 :
347 0 : if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
348 : return -EINVAL;
349 :
350 0 : switch (info->query_hw_ip.type) {
351 : case AMDGPU_HW_IP_GFX:
352 : type = AMD_IP_BLOCK_TYPE_GFX;
353 0 : for (i = 0; i < adev->gfx.num_gfx_rings; i++)
354 0 : if (adev->gfx.gfx_ring[i].sched.ready)
355 0 : ++num_rings;
356 : ib_start_alignment = 32;
357 : ib_size_alignment = 32;
358 : break;
359 : case AMDGPU_HW_IP_COMPUTE:
360 : type = AMD_IP_BLOCK_TYPE_GFX;
361 0 : for (i = 0; i < adev->gfx.num_compute_rings; i++)
362 0 : if (adev->gfx.compute_ring[i].sched.ready)
363 0 : ++num_rings;
364 : ib_start_alignment = 32;
365 : ib_size_alignment = 32;
366 : break;
367 : case AMDGPU_HW_IP_DMA:
368 : type = AMD_IP_BLOCK_TYPE_SDMA;
369 0 : for (i = 0; i < adev->sdma.num_instances; i++)
370 0 : if (adev->sdma.instance[i].ring.sched.ready)
371 0 : ++num_rings;
372 : ib_start_alignment = 256;
373 : ib_size_alignment = 4;
374 : break;
375 : case AMDGPU_HW_IP_UVD:
376 : type = AMD_IP_BLOCK_TYPE_UVD;
377 0 : for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
378 0 : if (adev->uvd.harvest_config & (1 << i))
379 0 : continue;
380 :
381 0 : if (adev->uvd.inst[i].ring.sched.ready)
382 0 : ++num_rings;
383 : }
384 : ib_start_alignment = 64;
385 : ib_size_alignment = 64;
386 : break;
387 : case AMDGPU_HW_IP_VCE:
388 : type = AMD_IP_BLOCK_TYPE_VCE;
389 0 : for (i = 0; i < adev->vce.num_rings; i++)
390 0 : if (adev->vce.ring[i].sched.ready)
391 0 : ++num_rings;
392 : ib_start_alignment = 4;
393 : ib_size_alignment = 1;
394 : break;
395 : case AMDGPU_HW_IP_UVD_ENC:
396 : type = AMD_IP_BLOCK_TYPE_UVD;
397 0 : for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
398 0 : if (adev->uvd.harvest_config & (1 << i))
399 0 : continue;
400 :
401 0 : for (j = 0; j < adev->uvd.num_enc_rings; j++)
402 0 : if (adev->uvd.inst[i].ring_enc[j].sched.ready)
403 0 : ++num_rings;
404 : }
405 : ib_start_alignment = 64;
406 : ib_size_alignment = 64;
407 : break;
408 : case AMDGPU_HW_IP_VCN_DEC:
409 : type = AMD_IP_BLOCK_TYPE_VCN;
410 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
411 0 : if (adev->uvd.harvest_config & (1 << i))
412 0 : continue;
413 :
414 0 : if (adev->vcn.inst[i].ring_dec.sched.ready)
415 0 : ++num_rings;
416 : }
417 : ib_start_alignment = 16;
418 : ib_size_alignment = 16;
419 : break;
420 : case AMDGPU_HW_IP_VCN_ENC:
421 : type = AMD_IP_BLOCK_TYPE_VCN;
422 0 : for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
423 0 : if (adev->uvd.harvest_config & (1 << i))
424 0 : continue;
425 :
426 0 : for (j = 0; j < adev->vcn.num_enc_rings; j++)
427 0 : if (adev->vcn.inst[i].ring_enc[j].sched.ready)
428 0 : ++num_rings;
429 : }
430 : ib_start_alignment = 64;
431 : ib_size_alignment = 1;
432 : break;
433 : case AMDGPU_HW_IP_VCN_JPEG:
434 0 : type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
435 0 : AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
436 :
437 0 : for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
438 0 : if (adev->jpeg.harvest_config & (1 << i))
439 0 : continue;
440 :
441 0 : if (adev->jpeg.inst[i].ring_dec.sched.ready)
442 0 : ++num_rings;
443 : }
444 : ib_start_alignment = 16;
445 : ib_size_alignment = 16;
446 : break;
447 : default:
448 : return -EINVAL;
449 : }
450 :
451 0 : for (i = 0; i < adev->num_ip_blocks; i++)
452 0 : if (adev->ip_blocks[i].version->type == type &&
453 0 : adev->ip_blocks[i].status.valid)
454 : break;
455 :
456 0 : if (i == adev->num_ip_blocks)
457 : return 0;
458 :
459 0 : num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
460 : num_rings);
461 :
462 0 : result->hw_ip_version_major = adev->ip_blocks[i].version->major;
463 0 : result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
464 :
465 0 : if (adev->asic_type >= CHIP_VEGA10) {
466 0 : switch (type) {
467 : case AMD_IP_BLOCK_TYPE_GFX:
468 0 : result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
469 : break;
470 : case AMD_IP_BLOCK_TYPE_SDMA:
471 0 : result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
472 : break;
473 : case AMD_IP_BLOCK_TYPE_UVD:
474 : case AMD_IP_BLOCK_TYPE_VCN:
475 : case AMD_IP_BLOCK_TYPE_JPEG:
476 0 : result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
477 : break;
478 : case AMD_IP_BLOCK_TYPE_VCE:
479 0 : result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
480 : break;
481 : default:
482 0 : result->ip_discovery_version = 0;
483 : break;
484 : }
485 : } else {
486 0 : result->ip_discovery_version = 0;
487 : }
488 0 : result->capabilities_flags = 0;
489 0 : result->available_rings = (1 << num_rings) - 1;
490 0 : result->ib_start_alignment = ib_start_alignment;
491 0 : result->ib_size_alignment = ib_size_alignment;
492 : return 0;
493 : }
494 :
495 : /*
496 : * Userspace get information ioctl
497 : */
498 : /**
499 : * amdgpu_info_ioctl - answer a device specific request.
500 : *
501 : * @dev: drm device pointer
502 : * @data: request object
503 : * @filp: drm filp
504 : *
505 : * This function is used to pass device specific parameters to the userspace
506 : * drivers. Examples include: pci device id, pipeline parms, tiling params,
507 : * etc. (all asics).
508 : * Returns 0 on success, -EINVAL on failure.
509 : */
510 0 : int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
511 : {
512 0 : struct amdgpu_device *adev = drm_to_adev(dev);
513 0 : struct drm_amdgpu_info *info = data;
514 0 : struct amdgpu_mode_info *minfo = &adev->mode_info;
515 0 : void __user *out = (void __user *)(uintptr_t)info->return_pointer;
516 0 : uint32_t size = info->return_size;
517 : struct drm_crtc *crtc;
518 0 : uint32_t ui32 = 0;
519 0 : uint64_t ui64 = 0;
520 : int i, found;
521 0 : int ui32_size = sizeof(ui32);
522 :
523 0 : if (!info->return_size || !info->return_pointer)
524 : return -EINVAL;
525 :
526 0 : switch (info->query) {
527 : case AMDGPU_INFO_ACCEL_WORKING:
528 0 : ui32 = adev->accel_working;
529 0 : return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
530 : case AMDGPU_INFO_CRTC_FROM_ID:
531 0 : for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
532 0 : crtc = (struct drm_crtc *)minfo->crtcs[i];
533 0 : if (crtc && crtc->base.id == info->mode_crtc.id) {
534 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
535 0 : ui32 = amdgpu_crtc->crtc_id;
536 0 : found = 1;
537 0 : break;
538 : }
539 : }
540 0 : if (!found) {
541 0 : DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
542 0 : return -EINVAL;
543 : }
544 0 : return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
545 : case AMDGPU_INFO_HW_IP_INFO: {
546 0 : struct drm_amdgpu_info_hw_ip ip = {};
547 : int ret;
548 :
549 0 : ret = amdgpu_hw_ip_info(adev, info, &ip);
550 0 : if (ret)
551 : return ret;
552 :
553 0 : ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
554 0 : return ret ? -EFAULT : 0;
555 : }
556 : case AMDGPU_INFO_HW_IP_COUNT: {
557 : enum amd_ip_block_type type;
558 0 : uint32_t count = 0;
559 :
560 0 : switch (info->query_hw_ip.type) {
561 : case AMDGPU_HW_IP_GFX:
562 : type = AMD_IP_BLOCK_TYPE_GFX;
563 : break;
564 : case AMDGPU_HW_IP_COMPUTE:
565 : type = AMD_IP_BLOCK_TYPE_GFX;
566 : break;
567 : case AMDGPU_HW_IP_DMA:
568 0 : type = AMD_IP_BLOCK_TYPE_SDMA;
569 0 : break;
570 : case AMDGPU_HW_IP_UVD:
571 0 : type = AMD_IP_BLOCK_TYPE_UVD;
572 0 : break;
573 : case AMDGPU_HW_IP_VCE:
574 0 : type = AMD_IP_BLOCK_TYPE_VCE;
575 0 : break;
576 : case AMDGPU_HW_IP_UVD_ENC:
577 0 : type = AMD_IP_BLOCK_TYPE_UVD;
578 0 : break;
579 : case AMDGPU_HW_IP_VCN_DEC:
580 : case AMDGPU_HW_IP_VCN_ENC:
581 0 : type = AMD_IP_BLOCK_TYPE_VCN;
582 0 : break;
583 : case AMDGPU_HW_IP_VCN_JPEG:
584 0 : type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
585 0 : AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
586 : break;
587 : default:
588 : return -EINVAL;
589 : }
590 :
591 0 : for (i = 0; i < adev->num_ip_blocks; i++)
592 0 : if (adev->ip_blocks[i].version->type == type &&
593 0 : adev->ip_blocks[i].status.valid &&
594 0 : count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
595 0 : count++;
596 :
597 0 : return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
598 : }
599 : case AMDGPU_INFO_TIMESTAMP:
600 0 : ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
601 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
602 : case AMDGPU_INFO_FW_VERSION: {
603 : struct drm_amdgpu_info_firmware fw_info;
604 : int ret;
605 :
606 : /* We only support one instance of each IP block right now. */
607 0 : if (info->query_fw.ip_instance != 0)
608 : return -EINVAL;
609 :
610 0 : ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
611 0 : if (ret)
612 : return ret;
613 :
614 0 : return copy_to_user(out, &fw_info,
615 0 : min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
616 : }
617 : case AMDGPU_INFO_NUM_BYTES_MOVED:
618 0 : ui64 = atomic64_read(&adev->num_bytes_moved);
619 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
620 : case AMDGPU_INFO_NUM_EVICTIONS:
621 0 : ui64 = atomic64_read(&adev->num_evictions);
622 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
623 : case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
624 0 : ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
625 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
626 : case AMDGPU_INFO_VRAM_USAGE:
627 0 : ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
628 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
629 : case AMDGPU_INFO_VIS_VRAM_USAGE:
630 0 : ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
631 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
632 : case AMDGPU_INFO_GTT_USAGE:
633 0 : ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
634 0 : return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
635 : case AMDGPU_INFO_GDS_CONFIG: {
636 : struct drm_amdgpu_info_gds gds_info;
637 :
638 0 : memset(&gds_info, 0, sizeof(gds_info));
639 0 : gds_info.compute_partition_size = adev->gds.gds_size;
640 0 : gds_info.gds_total_size = adev->gds.gds_size;
641 0 : gds_info.gws_per_compute_partition = adev->gds.gws_size;
642 0 : gds_info.oa_per_compute_partition = adev->gds.oa_size;
643 0 : return copy_to_user(out, &gds_info,
644 0 : min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
645 : }
646 : case AMDGPU_INFO_VRAM_GTT: {
647 : struct drm_amdgpu_info_vram_gtt vram_gtt;
648 :
649 0 : vram_gtt.vram_size = adev->gmc.real_vram_size -
650 0 : atomic64_read(&adev->vram_pin_size) -
651 : AMDGPU_VM_RESERVED_VRAM;
652 0 : vram_gtt.vram_cpu_accessible_size =
653 0 : min(adev->gmc.visible_vram_size -
654 : atomic64_read(&adev->visible_pin_size),
655 : vram_gtt.vram_size);
656 0 : vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
657 0 : vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
658 0 : return copy_to_user(out, &vram_gtt,
659 0 : min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
660 : }
661 : case AMDGPU_INFO_MEMORY: {
662 : struct drm_amdgpu_memory_info mem;
663 0 : struct ttm_resource_manager *gtt_man =
664 : &adev->mman.gtt_mgr.manager;
665 0 : struct ttm_resource_manager *vram_man =
666 : &adev->mman.vram_mgr.manager;
667 :
668 0 : memset(&mem, 0, sizeof(mem));
669 0 : mem.vram.total_heap_size = adev->gmc.real_vram_size;
670 0 : mem.vram.usable_heap_size = adev->gmc.real_vram_size -
671 0 : atomic64_read(&adev->vram_pin_size) -
672 : AMDGPU_VM_RESERVED_VRAM;
673 0 : mem.vram.heap_usage =
674 0 : ttm_resource_manager_usage(vram_man);
675 0 : mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
676 :
677 0 : mem.cpu_accessible_vram.total_heap_size =
678 0 : adev->gmc.visible_vram_size;
679 0 : mem.cpu_accessible_vram.usable_heap_size =
680 0 : min(adev->gmc.visible_vram_size -
681 : atomic64_read(&adev->visible_pin_size),
682 : mem.vram.usable_heap_size);
683 0 : mem.cpu_accessible_vram.heap_usage =
684 0 : amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
685 0 : mem.cpu_accessible_vram.max_allocation =
686 0 : mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
687 :
688 0 : mem.gtt.total_heap_size = gtt_man->size;
689 0 : mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
690 0 : atomic64_read(&adev->gart_pin_size);
691 0 : mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
692 0 : mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
693 :
694 0 : return copy_to_user(out, &mem,
695 0 : min((size_t)size, sizeof(mem)))
696 0 : ? -EFAULT : 0;
697 : }
698 : case AMDGPU_INFO_READ_MMR_REG: {
699 : unsigned n, alloc_size;
700 : uint32_t *regs;
701 0 : unsigned se_num = (info->read_mmr_reg.instance >>
702 : AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
703 : AMDGPU_INFO_MMR_SE_INDEX_MASK;
704 0 : unsigned sh_num = (info->read_mmr_reg.instance >>
705 : AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
706 : AMDGPU_INFO_MMR_SH_INDEX_MASK;
707 :
708 : /* set full masks if the userspace set all bits
709 : * in the bitfields */
710 0 : if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
711 : se_num = 0xffffffff;
712 0 : else if (se_num >= AMDGPU_GFX_MAX_SE)
713 : return -EINVAL;
714 0 : if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
715 : sh_num = 0xffffffff;
716 0 : else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
717 : return -EINVAL;
718 :
719 0 : if (info->read_mmr_reg.count > 128)
720 : return -EINVAL;
721 :
722 0 : regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
723 0 : if (!regs)
724 : return -ENOMEM;
725 0 : alloc_size = info->read_mmr_reg.count * sizeof(*regs);
726 :
727 0 : amdgpu_gfx_off_ctrl(adev, false);
728 0 : for (i = 0; i < info->read_mmr_reg.count; i++) {
729 0 : if (amdgpu_asic_read_register(adev, se_num, sh_num,
730 : info->read_mmr_reg.dword_offset + i,
731 : ®s[i])) {
732 0 : DRM_DEBUG_KMS("unallowed offset %#x\n",
733 : info->read_mmr_reg.dword_offset + i);
734 0 : kfree(regs);
735 0 : amdgpu_gfx_off_ctrl(adev, true);
736 0 : return -EFAULT;
737 : }
738 : }
739 0 : amdgpu_gfx_off_ctrl(adev, true);
740 0 : n = copy_to_user(out, regs, min(size, alloc_size));
741 0 : kfree(regs);
742 0 : return n ? -EFAULT : 0;
743 : }
744 : case AMDGPU_INFO_DEV_INFO: {
745 : struct drm_amdgpu_info_device *dev_info;
746 : uint64_t vm_size;
747 : int ret;
748 :
749 0 : dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
750 0 : if (!dev_info)
751 : return -ENOMEM;
752 :
753 0 : dev_info->device_id = adev->pdev->device;
754 0 : dev_info->chip_rev = adev->rev_id;
755 0 : dev_info->external_rev = adev->external_rev_id;
756 0 : dev_info->pci_rev = adev->pdev->revision;
757 0 : dev_info->family = adev->family;
758 0 : dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
759 0 : dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
760 : /* return all clocks in KHz */
761 0 : dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
762 0 : if (adev->pm.dpm_enabled) {
763 0 : dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
764 0 : dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
765 : } else {
766 0 : dev_info->max_engine_clock = adev->clock.default_sclk * 10;
767 0 : dev_info->max_memory_clock = adev->clock.default_mclk * 10;
768 : }
769 0 : dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
770 0 : dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
771 0 : adev->gfx.config.max_shader_engines;
772 0 : dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
773 0 : dev_info->_pad = 0;
774 0 : dev_info->ids_flags = 0;
775 0 : if (adev->flags & AMD_IS_APU)
776 0 : dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
777 0 : if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
778 0 : dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
779 0 : if (amdgpu_is_tmz(adev))
780 0 : dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
781 :
782 0 : vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
783 0 : vm_size -= AMDGPU_VA_RESERVED_SIZE;
784 :
785 : /* Older VCE FW versions are buggy and can handle only 40bits */
786 0 : if (adev->vce.fw_version &&
787 : adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
788 0 : vm_size = min(vm_size, 1ULL << 40);
789 :
790 0 : dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
791 0 : dev_info->virtual_address_max =
792 0 : min(vm_size, AMDGPU_GMC_HOLE_START);
793 :
794 0 : if (vm_size > AMDGPU_GMC_HOLE_START) {
795 0 : dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
796 0 : dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
797 : }
798 0 : dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
799 0 : dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
800 0 : dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
801 0 : dev_info->cu_active_number = adev->gfx.cu_info.number;
802 0 : dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
803 0 : dev_info->ce_ram_size = adev->gfx.ce_ram_size;
804 0 : memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
805 : sizeof(adev->gfx.cu_info.ao_cu_bitmap));
806 0 : memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
807 : sizeof(adev->gfx.cu_info.bitmap));
808 0 : dev_info->vram_type = adev->gmc.vram_type;
809 0 : dev_info->vram_bit_width = adev->gmc.vram_width;
810 0 : dev_info->vce_harvest_config = adev->vce.harvest_config;
811 0 : dev_info->gc_double_offchip_lds_buf =
812 0 : adev->gfx.config.double_offchip_lds_buf;
813 0 : dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
814 0 : dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
815 0 : dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
816 0 : dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
817 0 : dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
818 0 : dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
819 0 : dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
820 :
821 0 : if (adev->family >= AMDGPU_FAMILY_NV)
822 0 : dev_info->pa_sc_tile_steering_override =
823 0 : adev->gfx.config.pa_sc_tile_steering_override;
824 :
825 0 : dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
826 :
827 0 : ret = copy_to_user(out, dev_info,
828 0 : min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
829 0 : kfree(dev_info);
830 0 : return ret;
831 : }
832 : case AMDGPU_INFO_VCE_CLOCK_TABLE: {
833 : unsigned i;
834 0 : struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
835 : struct amd_vce_state *vce_state;
836 :
837 0 : for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
838 0 : vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
839 0 : if (vce_state) {
840 0 : vce_clk_table.entries[i].sclk = vce_state->sclk;
841 0 : vce_clk_table.entries[i].mclk = vce_state->mclk;
842 0 : vce_clk_table.entries[i].eclk = vce_state->evclk;
843 0 : vce_clk_table.num_valid_entries++;
844 : }
845 : }
846 :
847 0 : return copy_to_user(out, &vce_clk_table,
848 0 : min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
849 : }
850 : case AMDGPU_INFO_VBIOS: {
851 0 : uint32_t bios_size = adev->bios_size;
852 :
853 0 : switch (info->vbios_info.type) {
854 : case AMDGPU_INFO_VBIOS_SIZE:
855 0 : return copy_to_user(out, &bios_size,
856 0 : min((size_t)size, sizeof(bios_size)))
857 0 : ? -EFAULT : 0;
858 : case AMDGPU_INFO_VBIOS_IMAGE: {
859 : uint8_t *bios;
860 0 : uint32_t bios_offset = info->vbios_info.offset;
861 :
862 0 : if (bios_offset >= bios_size)
863 : return -EINVAL;
864 :
865 0 : bios = adev->bios + bios_offset;
866 0 : return copy_to_user(out, bios,
867 0 : min((size_t)size, (size_t)(bios_size - bios_offset)))
868 0 : ? -EFAULT : 0;
869 : }
870 : case AMDGPU_INFO_VBIOS_INFO: {
871 0 : struct drm_amdgpu_info_vbios vbios_info = {};
872 : struct atom_context *atom_context;
873 :
874 0 : atom_context = adev->mode_info.atom_context;
875 0 : memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
876 0 : memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
877 0 : vbios_info.version = atom_context->version;
878 0 : memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
879 : sizeof(atom_context->vbios_ver_str));
880 0 : memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
881 :
882 0 : return copy_to_user(out, &vbios_info,
883 0 : min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
884 : }
885 : default:
886 0 : DRM_DEBUG_KMS("Invalid request %d\n",
887 : info->vbios_info.type);
888 0 : return -EINVAL;
889 : }
890 : }
891 : case AMDGPU_INFO_NUM_HANDLES: {
892 : struct drm_amdgpu_info_num_handles handle;
893 :
894 0 : switch (info->query_hw_ip.type) {
895 : case AMDGPU_HW_IP_UVD:
896 : /* Starting Polaris, we support unlimited UVD handles */
897 0 : if (adev->asic_type < CHIP_POLARIS10) {
898 0 : handle.uvd_max_handles = adev->uvd.max_handles;
899 0 : handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
900 :
901 0 : return copy_to_user(out, &handle,
902 0 : min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
903 : } else {
904 : return -ENODATA;
905 : }
906 :
907 : break;
908 : default:
909 : return -EINVAL;
910 : }
911 : }
912 : case AMDGPU_INFO_SENSOR: {
913 0 : if (!adev->pm.dpm_enabled)
914 : return -ENOENT;
915 :
916 0 : switch (info->sensor_info.type) {
917 : case AMDGPU_INFO_SENSOR_GFX_SCLK:
918 : /* get sclk in Mhz */
919 0 : if (amdgpu_dpm_read_sensor(adev,
920 : AMDGPU_PP_SENSOR_GFX_SCLK,
921 : (void *)&ui32, &ui32_size)) {
922 : return -EINVAL;
923 : }
924 0 : ui32 /= 100;
925 0 : break;
926 : case AMDGPU_INFO_SENSOR_GFX_MCLK:
927 : /* get mclk in Mhz */
928 0 : if (amdgpu_dpm_read_sensor(adev,
929 : AMDGPU_PP_SENSOR_GFX_MCLK,
930 : (void *)&ui32, &ui32_size)) {
931 : return -EINVAL;
932 : }
933 0 : ui32 /= 100;
934 0 : break;
935 : case AMDGPU_INFO_SENSOR_GPU_TEMP:
936 : /* get temperature in millidegrees C */
937 0 : if (amdgpu_dpm_read_sensor(adev,
938 : AMDGPU_PP_SENSOR_GPU_TEMP,
939 : (void *)&ui32, &ui32_size)) {
940 : return -EINVAL;
941 : }
942 : break;
943 : case AMDGPU_INFO_SENSOR_GPU_LOAD:
944 : /* get GPU load */
945 0 : if (amdgpu_dpm_read_sensor(adev,
946 : AMDGPU_PP_SENSOR_GPU_LOAD,
947 : (void *)&ui32, &ui32_size)) {
948 : return -EINVAL;
949 : }
950 : break;
951 : case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
952 : /* get average GPU power */
953 0 : if (amdgpu_dpm_read_sensor(adev,
954 : AMDGPU_PP_SENSOR_GPU_POWER,
955 : (void *)&ui32, &ui32_size)) {
956 : return -EINVAL;
957 : }
958 0 : ui32 >>= 8;
959 0 : break;
960 : case AMDGPU_INFO_SENSOR_VDDNB:
961 : /* get VDDNB in millivolts */
962 0 : if (amdgpu_dpm_read_sensor(adev,
963 : AMDGPU_PP_SENSOR_VDDNB,
964 : (void *)&ui32, &ui32_size)) {
965 : return -EINVAL;
966 : }
967 : break;
968 : case AMDGPU_INFO_SENSOR_VDDGFX:
969 : /* get VDDGFX in millivolts */
970 0 : if (amdgpu_dpm_read_sensor(adev,
971 : AMDGPU_PP_SENSOR_VDDGFX,
972 : (void *)&ui32, &ui32_size)) {
973 : return -EINVAL;
974 : }
975 : break;
976 : case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
977 : /* get stable pstate sclk in Mhz */
978 0 : if (amdgpu_dpm_read_sensor(adev,
979 : AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
980 : (void *)&ui32, &ui32_size)) {
981 : return -EINVAL;
982 : }
983 0 : ui32 /= 100;
984 0 : break;
985 : case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
986 : /* get stable pstate mclk in Mhz */
987 0 : if (amdgpu_dpm_read_sensor(adev,
988 : AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
989 : (void *)&ui32, &ui32_size)) {
990 : return -EINVAL;
991 : }
992 0 : ui32 /= 100;
993 0 : break;
994 : default:
995 0 : DRM_DEBUG_KMS("Invalid request %d\n",
996 : info->sensor_info.type);
997 0 : return -EINVAL;
998 : }
999 0 : return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1000 : }
1001 : case AMDGPU_INFO_VRAM_LOST_COUNTER:
1002 0 : ui32 = atomic_read(&adev->vram_lost_counter);
1003 0 : return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1004 : case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1005 0 : struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1006 : uint64_t ras_mask;
1007 :
1008 0 : if (!ras)
1009 : return -EINVAL;
1010 0 : ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1011 :
1012 0 : return copy_to_user(out, &ras_mask,
1013 0 : min_t(u64, size, sizeof(ras_mask))) ?
1014 0 : -EFAULT : 0;
1015 : }
1016 : case AMDGPU_INFO_VIDEO_CAPS: {
1017 : const struct amdgpu_video_codecs *codecs;
1018 : struct drm_amdgpu_info_video_caps *caps;
1019 : int r;
1020 :
1021 0 : switch (info->video_cap.type) {
1022 : case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1023 0 : r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1024 0 : if (r)
1025 : return -EINVAL;
1026 : break;
1027 : case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1028 0 : r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1029 0 : if (r)
1030 : return -EINVAL;
1031 : break;
1032 : default:
1033 0 : DRM_DEBUG_KMS("Invalid request %d\n",
1034 : info->video_cap.type);
1035 0 : return -EINVAL;
1036 : }
1037 :
1038 0 : caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1039 0 : if (!caps)
1040 : return -ENOMEM;
1041 :
1042 0 : for (i = 0; i < codecs->codec_count; i++) {
1043 0 : int idx = codecs->codec_array[i].codec_type;
1044 :
1045 0 : switch (idx) {
1046 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1047 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1048 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1049 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1050 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1051 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1052 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1053 : case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1054 0 : caps->codec_info[idx].valid = 1;
1055 0 : caps->codec_info[idx].max_width =
1056 0 : codecs->codec_array[i].max_width;
1057 0 : caps->codec_info[idx].max_height =
1058 0 : codecs->codec_array[i].max_height;
1059 0 : caps->codec_info[idx].max_pixels_per_frame =
1060 0 : codecs->codec_array[i].max_pixels_per_frame;
1061 0 : caps->codec_info[idx].max_level =
1062 0 : codecs->codec_array[i].max_level;
1063 0 : break;
1064 : default:
1065 : break;
1066 : }
1067 : }
1068 0 : r = copy_to_user(out, caps,
1069 0 : min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1070 0 : kfree(caps);
1071 0 : return r;
1072 : }
1073 : default:
1074 0 : DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1075 0 : return -EINVAL;
1076 : }
1077 : return 0;
1078 : }
1079 :
1080 :
1081 : /*
1082 : * Outdated mess for old drm with Xorg being in charge (void function now).
1083 : */
1084 : /**
1085 : * amdgpu_driver_lastclose_kms - drm callback for last close
1086 : *
1087 : * @dev: drm dev pointer
1088 : *
1089 : * Switch vga_switcheroo state after last close (all asics).
1090 : */
1091 0 : void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1092 : {
1093 0 : drm_fb_helper_lastclose(dev);
1094 : vga_switcheroo_process_delayed_switch();
1095 0 : }
1096 :
1097 : /**
1098 : * amdgpu_driver_open_kms - drm callback for open
1099 : *
1100 : * @dev: drm dev pointer
1101 : * @file_priv: drm file
1102 : *
1103 : * On device open, init vm on cayman+ (all asics).
1104 : * Returns 0 on success, error on failure.
1105 : */
1106 0 : int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1107 : {
1108 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1109 : struct amdgpu_fpriv *fpriv;
1110 : int r, pasid;
1111 :
1112 : /* Ensure IB tests are run on ring */
1113 0 : flush_delayed_work(&adev->delayed_init_work);
1114 :
1115 :
1116 0 : if (amdgpu_ras_intr_triggered()) {
1117 0 : DRM_ERROR("RAS Intr triggered, device disabled!!");
1118 0 : return -EHWPOISON;
1119 : }
1120 :
1121 0 : file_priv->driver_priv = NULL;
1122 :
1123 0 : r = pm_runtime_get_sync(dev->dev);
1124 0 : if (r < 0)
1125 : goto pm_put;
1126 :
1127 0 : fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1128 0 : if (unlikely(!fpriv)) {
1129 : r = -ENOMEM;
1130 : goto out_suspend;
1131 : }
1132 :
1133 0 : pasid = amdgpu_pasid_alloc(16);
1134 0 : if (pasid < 0) {
1135 0 : dev_warn(adev->dev, "No more PASIDs available!");
1136 0 : pasid = 0;
1137 : }
1138 :
1139 0 : r = amdgpu_vm_init(adev, &fpriv->vm);
1140 0 : if (r)
1141 : goto error_pasid;
1142 :
1143 0 : r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1144 0 : if (r)
1145 : goto error_vm;
1146 :
1147 0 : fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1148 0 : if (!fpriv->prt_va) {
1149 : r = -ENOMEM;
1150 : goto error_vm;
1151 : }
1152 :
1153 0 : if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1154 0 : uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1155 :
1156 0 : r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1157 : &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1158 0 : if (r)
1159 : goto error_vm;
1160 : }
1161 :
1162 0 : mutex_init(&fpriv->bo_list_lock);
1163 0 : idr_init(&fpriv->bo_list_handles);
1164 :
1165 0 : amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1166 :
1167 0 : file_priv->driver_priv = fpriv;
1168 0 : goto out_suspend;
1169 :
1170 : error_vm:
1171 0 : amdgpu_vm_fini(adev, &fpriv->vm);
1172 :
1173 : error_pasid:
1174 0 : if (pasid) {
1175 0 : amdgpu_pasid_free(pasid);
1176 0 : amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1177 : }
1178 :
1179 0 : kfree(fpriv);
1180 :
1181 : out_suspend:
1182 0 : pm_runtime_mark_last_busy(dev->dev);
1183 : pm_put:
1184 0 : pm_runtime_put_autosuspend(dev->dev);
1185 :
1186 0 : return r;
1187 : }
1188 :
1189 : /**
1190 : * amdgpu_driver_postclose_kms - drm callback for post close
1191 : *
1192 : * @dev: drm dev pointer
1193 : * @file_priv: drm file
1194 : *
1195 : * On device post close, tear down vm on cayman+ (all asics).
1196 : */
1197 0 : void amdgpu_driver_postclose_kms(struct drm_device *dev,
1198 : struct drm_file *file_priv)
1199 : {
1200 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1201 0 : struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1202 : struct amdgpu_bo_list *list;
1203 : struct amdgpu_bo *pd;
1204 : u32 pasid;
1205 : int handle;
1206 :
1207 0 : if (!fpriv)
1208 0 : return;
1209 :
1210 0 : pm_runtime_get_sync(dev->dev);
1211 :
1212 0 : if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1213 0 : amdgpu_uvd_free_handles(adev, file_priv);
1214 0 : if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1215 0 : amdgpu_vce_free_handles(adev, file_priv);
1216 :
1217 0 : if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1218 : /* TODO: how to handle reserve failure */
1219 0 : BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1220 0 : amdgpu_vm_bo_del(adev, fpriv->csa_va);
1221 0 : fpriv->csa_va = NULL;
1222 0 : amdgpu_bo_unreserve(adev->virt.csa_obj);
1223 : }
1224 :
1225 0 : pasid = fpriv->vm.pasid;
1226 0 : pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1227 0 : if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1228 0 : amdgpu_vm_bo_del(adev, fpriv->prt_va);
1229 0 : amdgpu_bo_unreserve(pd);
1230 : }
1231 :
1232 0 : amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1233 0 : amdgpu_vm_fini(adev, &fpriv->vm);
1234 :
1235 0 : if (pasid)
1236 0 : amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1237 0 : amdgpu_bo_unref(&pd);
1238 :
1239 0 : idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1240 0 : amdgpu_bo_list_put(list);
1241 :
1242 0 : idr_destroy(&fpriv->bo_list_handles);
1243 0 : mutex_destroy(&fpriv->bo_list_lock);
1244 :
1245 0 : kfree(fpriv);
1246 0 : file_priv->driver_priv = NULL;
1247 :
1248 0 : pm_runtime_mark_last_busy(dev->dev);
1249 0 : pm_runtime_put_autosuspend(dev->dev);
1250 : }
1251 :
1252 :
1253 0 : void amdgpu_driver_release_kms(struct drm_device *dev)
1254 : {
1255 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1256 :
1257 0 : amdgpu_device_fini_sw(adev);
1258 0 : pci_set_drvdata(adev->pdev, NULL);
1259 0 : }
1260 :
1261 : /*
1262 : * VBlank related functions.
1263 : */
1264 : /**
1265 : * amdgpu_get_vblank_counter_kms - get frame count
1266 : *
1267 : * @crtc: crtc to get the frame count from
1268 : *
1269 : * Gets the frame count on the requested crtc (all asics).
1270 : * Returns frame count on success, -EINVAL on failure.
1271 : */
1272 0 : u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1273 : {
1274 0 : struct drm_device *dev = crtc->dev;
1275 0 : unsigned int pipe = crtc->index;
1276 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1277 : int vpos, hpos, stat;
1278 : u32 count;
1279 :
1280 0 : if (pipe >= adev->mode_info.num_crtc) {
1281 0 : DRM_ERROR("Invalid crtc %u\n", pipe);
1282 0 : return -EINVAL;
1283 : }
1284 :
1285 : /* The hw increments its frame counter at start of vsync, not at start
1286 : * of vblank, as is required by DRM core vblank counter handling.
1287 : * Cook the hw count here to make it appear to the caller as if it
1288 : * incremented at start of vblank. We measure distance to start of
1289 : * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1290 : * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1291 : * result by 1 to give the proper appearance to caller.
1292 : */
1293 0 : if (adev->mode_info.crtcs[pipe]) {
1294 : /* Repeat readout if needed to provide stable result if
1295 : * we cross start of vsync during the queries.
1296 : */
1297 : do {
1298 0 : count = amdgpu_display_vblank_get_counter(adev, pipe);
1299 : /* Ask amdgpu_display_get_crtc_scanoutpos to return
1300 : * vpos as distance to start of vblank, instead of
1301 : * regular vertical scanout pos.
1302 : */
1303 0 : stat = amdgpu_display_get_crtc_scanoutpos(
1304 : dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1305 : &vpos, &hpos, NULL, NULL,
1306 0 : &adev->mode_info.crtcs[pipe]->base.hwmode);
1307 0 : } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1308 :
1309 0 : if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1310 : (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1311 0 : DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1312 : } else {
1313 0 : DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1314 : pipe, vpos);
1315 :
1316 : /* Bump counter if we are at >= leading edge of vblank,
1317 : * but before vsync where vpos would turn negative and
1318 : * the hw counter really increments.
1319 : */
1320 0 : if (vpos >= 0)
1321 0 : count++;
1322 : }
1323 : } else {
1324 : /* Fallback to use value as is. */
1325 0 : count = amdgpu_display_vblank_get_counter(adev, pipe);
1326 0 : DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1327 : }
1328 :
1329 : return count;
1330 : }
1331 :
1332 : /**
1333 : * amdgpu_enable_vblank_kms - enable vblank interrupt
1334 : *
1335 : * @crtc: crtc to enable vblank interrupt for
1336 : *
1337 : * Enable the interrupt on the requested crtc (all asics).
1338 : * Returns 0 on success, -EINVAL on failure.
1339 : */
1340 0 : int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1341 : {
1342 0 : struct drm_device *dev = crtc->dev;
1343 0 : unsigned int pipe = crtc->index;
1344 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1345 0 : int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1346 :
1347 0 : return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1348 : }
1349 :
1350 : /**
1351 : * amdgpu_disable_vblank_kms - disable vblank interrupt
1352 : *
1353 : * @crtc: crtc to disable vblank interrupt for
1354 : *
1355 : * Disable the interrupt on the requested crtc (all asics).
1356 : */
1357 0 : void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1358 : {
1359 0 : struct drm_device *dev = crtc->dev;
1360 0 : unsigned int pipe = crtc->index;
1361 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1362 0 : int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1363 :
1364 0 : amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1365 0 : }
1366 :
1367 : /*
1368 : * Debugfs info
1369 : */
1370 : #if defined(CONFIG_DEBUG_FS)
1371 :
1372 : static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1373 : {
1374 : struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1375 : struct drm_amdgpu_info_firmware fw_info;
1376 : struct drm_amdgpu_query_fw query_fw;
1377 : struct atom_context *ctx = adev->mode_info.atom_context;
1378 : uint8_t smu_program, smu_major, smu_minor, smu_debug;
1379 : int ret, i;
1380 :
1381 : static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1382 : #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1383 : TA_FW_NAME(XGMI),
1384 : TA_FW_NAME(RAS),
1385 : TA_FW_NAME(HDCP),
1386 : TA_FW_NAME(DTM),
1387 : TA_FW_NAME(RAP),
1388 : TA_FW_NAME(SECUREDISPLAY),
1389 : #undef TA_FW_NAME
1390 : };
1391 :
1392 : /* VCE */
1393 : query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1394 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395 : if (ret)
1396 : return ret;
1397 : seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1398 : fw_info.feature, fw_info.ver);
1399 :
1400 : /* UVD */
1401 : query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1402 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1403 : if (ret)
1404 : return ret;
1405 : seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1406 : fw_info.feature, fw_info.ver);
1407 :
1408 : /* GMC */
1409 : query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1410 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1411 : if (ret)
1412 : return ret;
1413 : seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1414 : fw_info.feature, fw_info.ver);
1415 :
1416 : /* ME */
1417 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1418 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1419 : if (ret)
1420 : return ret;
1421 : seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1422 : fw_info.feature, fw_info.ver);
1423 :
1424 : /* PFP */
1425 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1426 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427 : if (ret)
1428 : return ret;
1429 : seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1430 : fw_info.feature, fw_info.ver);
1431 :
1432 : /* CE */
1433 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1434 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435 : if (ret)
1436 : return ret;
1437 : seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1438 : fw_info.feature, fw_info.ver);
1439 :
1440 : /* RLC */
1441 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1442 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443 : if (ret)
1444 : return ret;
1445 : seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1446 : fw_info.feature, fw_info.ver);
1447 :
1448 : /* RLC SAVE RESTORE LIST CNTL */
1449 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1450 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451 : if (ret)
1452 : return ret;
1453 : seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1454 : fw_info.feature, fw_info.ver);
1455 :
1456 : /* RLC SAVE RESTORE LIST GPM MEM */
1457 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1458 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459 : if (ret)
1460 : return ret;
1461 : seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1462 : fw_info.feature, fw_info.ver);
1463 :
1464 : /* RLC SAVE RESTORE LIST SRM MEM */
1465 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1466 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467 : if (ret)
1468 : return ret;
1469 : seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1470 : fw_info.feature, fw_info.ver);
1471 :
1472 : /* MEC */
1473 : query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1474 : query_fw.index = 0;
1475 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1476 : if (ret)
1477 : return ret;
1478 : seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1479 : fw_info.feature, fw_info.ver);
1480 :
1481 : /* MEC2 */
1482 : if (adev->gfx.mec2_fw) {
1483 : query_fw.index = 1;
1484 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485 : if (ret)
1486 : return ret;
1487 : seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1488 : fw_info.feature, fw_info.ver);
1489 : }
1490 :
1491 : /* PSP SOS */
1492 : query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1493 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1494 : if (ret)
1495 : return ret;
1496 : seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1497 : fw_info.feature, fw_info.ver);
1498 :
1499 :
1500 : /* PSP ASD */
1501 : query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1502 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1503 : if (ret)
1504 : return ret;
1505 : seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1506 : fw_info.feature, fw_info.ver);
1507 :
1508 : query_fw.fw_type = AMDGPU_INFO_FW_TA;
1509 : for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1510 : query_fw.index = i;
1511 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512 : if (ret)
1513 : continue;
1514 :
1515 : seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1516 : ta_fw_name[i], fw_info.feature, fw_info.ver);
1517 : }
1518 :
1519 : /* SMC */
1520 : query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1521 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1522 : if (ret)
1523 : return ret;
1524 : smu_program = (fw_info.ver >> 24) & 0xff;
1525 : smu_major = (fw_info.ver >> 16) & 0xff;
1526 : smu_minor = (fw_info.ver >> 8) & 0xff;
1527 : smu_debug = (fw_info.ver >> 0) & 0xff;
1528 : seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1529 : fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1530 :
1531 : /* SDMA */
1532 : query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1533 : for (i = 0; i < adev->sdma.num_instances; i++) {
1534 : query_fw.index = i;
1535 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1536 : if (ret)
1537 : return ret;
1538 : seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1539 : i, fw_info.feature, fw_info.ver);
1540 : }
1541 :
1542 : /* VCN */
1543 : query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1544 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1545 : if (ret)
1546 : return ret;
1547 : seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1548 : fw_info.feature, fw_info.ver);
1549 :
1550 : /* DMCU */
1551 : query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1552 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1553 : if (ret)
1554 : return ret;
1555 : seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1556 : fw_info.feature, fw_info.ver);
1557 :
1558 : /* DMCUB */
1559 : query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1560 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1561 : if (ret)
1562 : return ret;
1563 : seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1564 : fw_info.feature, fw_info.ver);
1565 :
1566 : /* TOC */
1567 : query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1568 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1569 : if (ret)
1570 : return ret;
1571 : seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1572 : fw_info.feature, fw_info.ver);
1573 :
1574 : /* CAP */
1575 : if (adev->psp.cap_fw) {
1576 : query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1577 : ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1578 : if (ret)
1579 : return ret;
1580 : seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1581 : fw_info.feature, fw_info.ver);
1582 : }
1583 :
1584 : seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1585 :
1586 : return 0;
1587 : }
1588 :
1589 : DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1590 :
1591 : #endif
1592 :
1593 0 : void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1594 : {
1595 : #if defined(CONFIG_DEBUG_FS)
1596 : struct drm_minor *minor = adev_to_drm(adev)->primary;
1597 : struct dentry *root = minor->debugfs_root;
1598 :
1599 : debugfs_create_file("amdgpu_firmware_info", 0444, root,
1600 : adev, &amdgpu_debugfs_firmware_info_fops);
1601 :
1602 : #endif
1603 0 : }
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