Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Author: Huang Rui
23 : *
24 : */
25 :
26 : #include <linux/firmware.h>
27 : #include <drm/drm_drv.h>
28 :
29 : #include "amdgpu.h"
30 : #include "amdgpu_psp.h"
31 : #include "amdgpu_ucode.h"
32 : #include "amdgpu_xgmi.h"
33 : #include "soc15_common.h"
34 : #include "psp_v3_1.h"
35 : #include "psp_v10_0.h"
36 : #include "psp_v11_0.h"
37 : #include "psp_v11_0_8.h"
38 : #include "psp_v12_0.h"
39 : #include "psp_v13_0.h"
40 : #include "psp_v13_0_4.h"
41 :
42 : #include "amdgpu_ras.h"
43 : #include "amdgpu_securedisplay.h"
44 : #include "amdgpu_atomfirmware.h"
45 :
46 : #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
47 :
48 : static int psp_sysfs_init(struct amdgpu_device *adev);
49 : static void psp_sysfs_fini(struct amdgpu_device *adev);
50 :
51 : static int psp_load_smu_fw(struct psp_context *psp);
52 : static int psp_rap_terminate(struct psp_context *psp);
53 : static int psp_securedisplay_terminate(struct psp_context *psp);
54 :
55 : /*
56 : * Due to DF Cstate management centralized to PMFW, the firmware
57 : * loading sequence will be updated as below:
58 : * - Load KDB
59 : * - Load SYS_DRV
60 : * - Load tOS
61 : * - Load PMFW
62 : * - Setup TMR
63 : * - Load other non-psp fw
64 : * - Load ASD
65 : * - Load XGMI/RAS/HDCP/DTM TA if any
66 : *
67 : * This new sequence is required for
68 : * - Arcturus and onwards
69 : */
70 0 : static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
71 : {
72 0 : struct amdgpu_device *adev = psp->adev;
73 :
74 0 : if (amdgpu_sriov_vf(adev)) {
75 0 : psp->pmfw_centralized_cstate_management = false;
76 : return;
77 : }
78 :
79 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
80 : case IP_VERSION(11, 0, 0):
81 : case IP_VERSION(11, 0, 4):
82 : case IP_VERSION(11, 0, 5):
83 : case IP_VERSION(11, 0, 7):
84 : case IP_VERSION(11, 0, 9):
85 : case IP_VERSION(11, 0, 11):
86 : case IP_VERSION(11, 0, 12):
87 : case IP_VERSION(11, 0, 13):
88 : case IP_VERSION(13, 0, 0):
89 : case IP_VERSION(13, 0, 2):
90 : case IP_VERSION(13, 0, 7):
91 0 : psp->pmfw_centralized_cstate_management = true;
92 : break;
93 : default:
94 0 : psp->pmfw_centralized_cstate_management = false;
95 : break;
96 : }
97 : }
98 :
99 0 : static int psp_early_init(void *handle)
100 : {
101 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
102 0 : struct psp_context *psp = &adev->psp;
103 :
104 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
105 : case IP_VERSION(9, 0, 0):
106 0 : psp_v3_1_set_psp_funcs(psp);
107 0 : psp->autoload_supported = false;
108 0 : break;
109 : case IP_VERSION(10, 0, 0):
110 : case IP_VERSION(10, 0, 1):
111 0 : psp_v10_0_set_psp_funcs(psp);
112 0 : psp->autoload_supported = false;
113 0 : break;
114 : case IP_VERSION(11, 0, 2):
115 : case IP_VERSION(11, 0, 4):
116 0 : psp_v11_0_set_psp_funcs(psp);
117 0 : psp->autoload_supported = false;
118 0 : break;
119 : case IP_VERSION(11, 0, 0):
120 : case IP_VERSION(11, 0, 5):
121 : case IP_VERSION(11, 0, 9):
122 : case IP_VERSION(11, 0, 7):
123 : case IP_VERSION(11, 0, 11):
124 : case IP_VERSION(11, 5, 0):
125 : case IP_VERSION(11, 0, 12):
126 : case IP_VERSION(11, 0, 13):
127 0 : psp_v11_0_set_psp_funcs(psp);
128 0 : psp->autoload_supported = true;
129 0 : break;
130 : case IP_VERSION(11, 0, 3):
131 : case IP_VERSION(12, 0, 1):
132 0 : psp_v12_0_set_psp_funcs(psp);
133 0 : break;
134 : case IP_VERSION(13, 0, 2):
135 0 : psp_v13_0_set_psp_funcs(psp);
136 0 : break;
137 : case IP_VERSION(13, 0, 1):
138 : case IP_VERSION(13, 0, 3):
139 : case IP_VERSION(13, 0, 5):
140 : case IP_VERSION(13, 0, 8):
141 : case IP_VERSION(13, 0, 10):
142 0 : psp_v13_0_set_psp_funcs(psp);
143 0 : psp->autoload_supported = true;
144 0 : break;
145 : case IP_VERSION(11, 0, 8):
146 0 : if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
147 0 : psp_v11_0_8_set_psp_funcs(psp);
148 0 : psp->autoload_supported = false;
149 : }
150 : break;
151 : case IP_VERSION(13, 0, 0):
152 : case IP_VERSION(13, 0, 7):
153 0 : psp_v13_0_set_psp_funcs(psp);
154 0 : psp->autoload_supported = true;
155 0 : break;
156 : case IP_VERSION(13, 0, 4):
157 0 : psp_v13_0_4_set_psp_funcs(psp);
158 0 : psp->autoload_supported = true;
159 0 : break;
160 : default:
161 : return -EINVAL;
162 : }
163 :
164 0 : psp->adev = adev;
165 :
166 0 : psp_check_pmfw_centralized_cstate_management(psp);
167 :
168 0 : return 0;
169 : }
170 :
171 0 : void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
172 : {
173 0 : amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
174 : &mem_ctx->shared_buf);
175 0 : }
176 :
177 0 : static void psp_free_shared_bufs(struct psp_context *psp)
178 : {
179 : void *tmr_buf;
180 : void **pptr;
181 :
182 : /* free TMR memory buffer */
183 0 : pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
184 0 : amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
185 :
186 : /* free xgmi shared memory */
187 0 : psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
188 :
189 : /* free ras shared memory */
190 0 : psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
191 :
192 : /* free hdcp shared memory */
193 0 : psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
194 :
195 : /* free dtm shared memory */
196 0 : psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
197 :
198 : /* free rap shared memory */
199 0 : psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
200 :
201 : /* free securedisplay shared memory */
202 0 : psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
203 :
204 :
205 0 : }
206 :
207 : static void psp_memory_training_fini(struct psp_context *psp)
208 : {
209 0 : struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
210 :
211 0 : ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
212 0 : kfree(ctx->sys_cache);
213 0 : ctx->sys_cache = NULL;
214 : }
215 :
216 0 : static int psp_memory_training_init(struct psp_context *psp)
217 : {
218 : int ret;
219 0 : struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
220 :
221 0 : if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
222 0 : DRM_DEBUG("memory training is not supported!\n");
223 0 : return 0;
224 : }
225 :
226 0 : ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
227 0 : if (ctx->sys_cache == NULL) {
228 0 : DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
229 0 : ret = -ENOMEM;
230 : goto Err_out;
231 : }
232 :
233 0 : DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
234 : ctx->train_data_size,
235 : ctx->p2c_train_data_offset,
236 : ctx->c2p_train_data_offset);
237 0 : ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
238 0 : return 0;
239 :
240 : Err_out:
241 0 : psp_memory_training_fini(psp);
242 0 : return ret;
243 : }
244 :
245 : /*
246 : * Helper funciton to query psp runtime database entry
247 : *
248 : * @adev: amdgpu_device pointer
249 : * @entry_type: the type of psp runtime database entry
250 : * @db_entry: runtime database entry pointer
251 : *
252 : * Return false if runtime database doesn't exit or entry is invalid
253 : * or true if the specific database entry is found, and copy to @db_entry
254 : */
255 0 : static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
256 : enum psp_runtime_entry_type entry_type,
257 : void *db_entry)
258 : {
259 : uint64_t db_header_pos, db_dir_pos;
260 0 : struct psp_runtime_data_header db_header = {0};
261 0 : struct psp_runtime_data_directory db_dir = {0};
262 0 : bool ret = false;
263 : int i;
264 :
265 0 : db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
266 0 : db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
267 :
268 : /* read runtime db header from vram */
269 0 : amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
270 : sizeof(struct psp_runtime_data_header), false);
271 :
272 0 : if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
273 : /* runtime db doesn't exist, exit */
274 0 : dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
275 0 : return false;
276 : }
277 :
278 : /* read runtime database entry from vram */
279 0 : amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
280 : sizeof(struct psp_runtime_data_directory), false);
281 :
282 0 : if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
283 : /* invalid db entry count, exit */
284 0 : dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
285 0 : return false;
286 : }
287 :
288 : /* look up for requested entry type */
289 0 : for (i = 0; i < db_dir.entry_count && !ret; i++) {
290 0 : if (db_dir.entry_list[i].entry_type == entry_type) {
291 0 : switch (entry_type) {
292 : case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
293 0 : if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
294 : /* invalid db entry size */
295 0 : dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
296 0 : return false;
297 : }
298 : /* read runtime database entry */
299 0 : amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
300 : (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
301 0 : ret = true;
302 0 : break;
303 : case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
304 0 : if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
305 : /* invalid db entry size */
306 0 : dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
307 0 : return false;
308 : }
309 : /* read runtime database entry */
310 0 : amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
311 : (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
312 0 : ret = true;
313 0 : break;
314 : default:
315 : ret = false;
316 : break;
317 : }
318 : }
319 : }
320 :
321 : return ret;
322 : }
323 :
324 0 : static int psp_init_sriov_microcode(struct psp_context *psp)
325 : {
326 0 : struct amdgpu_device *adev = psp->adev;
327 0 : int ret = 0;
328 :
329 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
330 : case IP_VERSION(9, 0, 0):
331 0 : adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
332 0 : ret = psp_init_cap_microcode(psp, "vega10");
333 0 : break;
334 : case IP_VERSION(11, 0, 9):
335 0 : adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
336 0 : ret = psp_init_cap_microcode(psp, "navi12");
337 0 : break;
338 : case IP_VERSION(11, 0, 7):
339 0 : adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
340 0 : ret = psp_init_cap_microcode(psp, "sienna_cichlid");
341 0 : break;
342 : case IP_VERSION(13, 0, 2):
343 0 : adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
344 0 : ret = psp_init_cap_microcode(psp, "aldebaran");
345 0 : ret &= psp_init_ta_microcode(psp, "aldebaran");
346 0 : break;
347 : case IP_VERSION(13, 0, 0):
348 0 : adev->virt.autoload_ucode_id = 0;
349 0 : break;
350 : case IP_VERSION(13, 0, 10):
351 0 : adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
352 0 : break;
353 : default:
354 0 : BUG();
355 : break;
356 : }
357 0 : return ret;
358 : }
359 :
360 0 : static int psp_sw_init(void *handle)
361 : {
362 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
363 0 : struct psp_context *psp = &adev->psp;
364 : int ret;
365 : struct psp_runtime_boot_cfg_entry boot_cfg_entry;
366 0 : struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
367 : struct psp_runtime_scpm_entry scpm_entry;
368 :
369 0 : psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
370 0 : if (!psp->cmd) {
371 0 : DRM_ERROR("Failed to allocate memory to command buffer!\n");
372 0 : ret = -ENOMEM;
373 : }
374 :
375 0 : if (amdgpu_sriov_vf(adev))
376 0 : ret = psp_init_sriov_microcode(psp);
377 : else
378 0 : ret = psp_init_microcode(psp);
379 0 : if (ret) {
380 0 : DRM_ERROR("Failed to load psp firmware!\n");
381 0 : return ret;
382 : }
383 :
384 0 : adev->psp.xgmi_context.supports_extended_data =
385 0 : !adev->gmc.xgmi.connected_to_cpu &&
386 0 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
387 :
388 0 : memset(&scpm_entry, 0, sizeof(scpm_entry));
389 0 : if ((psp_get_runtime_db_entry(adev,
390 : PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
391 0 : &scpm_entry)) &&
392 0 : (SCPM_DISABLE != scpm_entry.scpm_status)) {
393 0 : adev->scpm_enabled = true;
394 0 : adev->scpm_status = scpm_entry.scpm_status;
395 : } else {
396 0 : adev->scpm_enabled = false;
397 0 : adev->scpm_status = SCPM_DISABLE;
398 : }
399 :
400 : /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
401 :
402 0 : memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
403 0 : if (psp_get_runtime_db_entry(adev,
404 : PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
405 : &boot_cfg_entry)) {
406 0 : psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
407 0 : if ((psp->boot_cfg_bitmask) &
408 : BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
409 : /* If psp runtime database exists, then
410 : * only enable two stage memory training
411 : * when TWO_STAGE_DRAM_TRAINING bit is set
412 : * in runtime database */
413 0 : mem_training_ctx->enable_mem_training = true;
414 : }
415 :
416 : } else {
417 : /* If psp runtime database doesn't exist or
418 : * is invalid, force enable two stage memory
419 : * training */
420 0 : mem_training_ctx->enable_mem_training = true;
421 : }
422 :
423 0 : if (mem_training_ctx->enable_mem_training) {
424 0 : ret = psp_memory_training_init(psp);
425 0 : if (ret) {
426 0 : DRM_ERROR("Failed to initialize memory training!\n");
427 0 : return ret;
428 : }
429 :
430 0 : ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
431 0 : if (ret) {
432 0 : DRM_ERROR("Failed to process memory training!\n");
433 0 : return ret;
434 : }
435 : }
436 :
437 0 : if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
438 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
439 0 : ret= psp_sysfs_init(adev);
440 0 : if (ret) {
441 : return ret;
442 : }
443 : }
444 :
445 0 : ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
446 0 : amdgpu_sriov_vf(adev) ?
447 : AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
448 : &psp->fw_pri_bo,
449 0 : &psp->fw_pri_mc_addr,
450 : &psp->fw_pri_buf);
451 0 : if (ret)
452 : return ret;
453 :
454 0 : ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
455 : AMDGPU_GEM_DOMAIN_VRAM,
456 : &psp->fence_buf_bo,
457 0 : &psp->fence_buf_mc_addr,
458 : &psp->fence_buf);
459 0 : if (ret)
460 : goto failed1;
461 :
462 0 : ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
463 : AMDGPU_GEM_DOMAIN_VRAM,
464 0 : &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
465 0 : (void **)&psp->cmd_buf_mem);
466 0 : if (ret)
467 : goto failed2;
468 :
469 : return 0;
470 :
471 : failed2:
472 0 : amdgpu_bo_free_kernel(&psp->fw_pri_bo,
473 : &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
474 : failed1:
475 0 : amdgpu_bo_free_kernel(&psp->fence_buf_bo,
476 : &psp->fence_buf_mc_addr, &psp->fence_buf);
477 0 : return ret;
478 : }
479 :
480 0 : static int psp_sw_fini(void *handle)
481 : {
482 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
483 0 : struct psp_context *psp = &adev->psp;
484 0 : struct psp_gfx_cmd_resp *cmd = psp->cmd;
485 :
486 0 : psp_memory_training_fini(psp);
487 0 : if (psp->sos_fw) {
488 0 : release_firmware(psp->sos_fw);
489 0 : psp->sos_fw = NULL;
490 : }
491 0 : if (psp->asd_fw) {
492 0 : release_firmware(psp->asd_fw);
493 0 : psp->asd_fw = NULL;
494 : }
495 0 : if (psp->ta_fw) {
496 0 : release_firmware(psp->ta_fw);
497 0 : psp->ta_fw = NULL;
498 : }
499 0 : if (psp->cap_fw) {
500 0 : release_firmware(psp->cap_fw);
501 0 : psp->cap_fw = NULL;
502 : }
503 0 : if (psp->toc_fw) {
504 0 : release_firmware(psp->toc_fw);
505 0 : psp->toc_fw = NULL;
506 : }
507 0 : if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
508 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
509 0 : psp_sysfs_fini(adev);
510 :
511 0 : kfree(cmd);
512 0 : cmd = NULL;
513 :
514 0 : amdgpu_bo_free_kernel(&psp->fw_pri_bo,
515 0 : &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
516 0 : amdgpu_bo_free_kernel(&psp->fence_buf_bo,
517 0 : &psp->fence_buf_mc_addr, &psp->fence_buf);
518 0 : amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
519 0 : (void **)&psp->cmd_buf_mem);
520 :
521 0 : return 0;
522 : }
523 :
524 0 : int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
525 : uint32_t reg_val, uint32_t mask, bool check_changed)
526 : {
527 : uint32_t val;
528 : int i;
529 0 : struct amdgpu_device *adev = psp->adev;
530 :
531 0 : if (psp->adev->no_hw_access)
532 : return 0;
533 :
534 0 : for (i = 0; i < adev->usec_timeout; i++) {
535 0 : val = RREG32(reg_index);
536 0 : if (check_changed) {
537 0 : if (val != reg_val)
538 : return 0;
539 : } else {
540 0 : if ((val & mask) == reg_val)
541 : return 0;
542 : }
543 0 : udelay(1);
544 : }
545 :
546 : return -ETIME;
547 : }
548 :
549 : static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
550 : {
551 : switch (cmd_id) {
552 : case GFX_CMD_ID_LOAD_TA:
553 : return "LOAD_TA";
554 : case GFX_CMD_ID_UNLOAD_TA:
555 : return "UNLOAD_TA";
556 : case GFX_CMD_ID_INVOKE_CMD:
557 : return "INVOKE_CMD";
558 : case GFX_CMD_ID_LOAD_ASD:
559 : return "LOAD_ASD";
560 : case GFX_CMD_ID_SETUP_TMR:
561 : return "SETUP_TMR";
562 : case GFX_CMD_ID_LOAD_IP_FW:
563 : return "LOAD_IP_FW";
564 : case GFX_CMD_ID_DESTROY_TMR:
565 : return "DESTROY_TMR";
566 : case GFX_CMD_ID_SAVE_RESTORE:
567 : return "SAVE_RESTORE_IP_FW";
568 : case GFX_CMD_ID_SETUP_VMR:
569 : return "SETUP_VMR";
570 : case GFX_CMD_ID_DESTROY_VMR:
571 : return "DESTROY_VMR";
572 : case GFX_CMD_ID_PROG_REG:
573 : return "PROG_REG";
574 : case GFX_CMD_ID_GET_FW_ATTESTATION:
575 : return "GET_FW_ATTESTATION";
576 : case GFX_CMD_ID_LOAD_TOC:
577 : return "ID_LOAD_TOC";
578 : case GFX_CMD_ID_AUTOLOAD_RLC:
579 : return "AUTOLOAD_RLC";
580 : case GFX_CMD_ID_BOOT_CFG:
581 : return "BOOT_CFG";
582 : default:
583 : return "UNKNOWN CMD";
584 : }
585 : }
586 :
587 : static int
588 0 : psp_cmd_submit_buf(struct psp_context *psp,
589 : struct amdgpu_firmware_info *ucode,
590 : struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
591 : {
592 : int ret;
593 : int index, idx;
594 0 : int timeout = 20000;
595 0 : bool ras_intr = false;
596 0 : bool skip_unsupport = false;
597 :
598 0 : if (psp->adev->no_hw_access)
599 : return 0;
600 :
601 0 : if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
602 : return 0;
603 :
604 0 : memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
605 :
606 0 : memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
607 :
608 0 : index = atomic_inc_return(&psp->fence_value);
609 0 : ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
610 0 : if (ret) {
611 0 : atomic_dec(&psp->fence_value);
612 : goto exit;
613 : }
614 :
615 0 : amdgpu_device_invalidate_hdp(psp->adev, NULL);
616 0 : while (*((unsigned int *)psp->fence_buf) != index) {
617 0 : if (--timeout == 0)
618 : break;
619 : /*
620 : * Shouldn't wait for timeout when err_event_athub occurs,
621 : * because gpu reset thread triggered and lock resource should
622 : * be released for psp resume sequence.
623 : */
624 0 : ras_intr = amdgpu_ras_intr_triggered();
625 0 : if (ras_intr)
626 : break;
627 0 : usleep_range(10, 100);
628 0 : amdgpu_device_invalidate_hdp(psp->adev, NULL);
629 : }
630 :
631 : /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
632 0 : skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
633 0 : psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
634 :
635 0 : memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
636 :
637 : /* In some cases, psp response status is not 0 even there is no
638 : * problem while the command is submitted. Some version of PSP FW
639 : * doesn't write 0 to that field.
640 : * So here we would like to only print a warning instead of an error
641 : * during psp initialization to avoid breaking hw_init and it doesn't
642 : * return -EINVAL.
643 : */
644 0 : if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
645 0 : if (ucode)
646 0 : DRM_WARN("failed to load ucode %s(0x%X) ",
647 : amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
648 0 : DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
649 : psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
650 : psp->cmd_buf_mem->resp.status);
651 : /* If any firmware (including CAP) load fails under SRIOV, it should
652 : * return failure to stop the VF from initializing.
653 : * Also return failure in case of timeout
654 : */
655 0 : if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
656 : ret = -EINVAL;
657 : goto exit;
658 : }
659 : }
660 :
661 0 : if (ucode) {
662 0 : ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
663 0 : ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
664 : }
665 :
666 : exit:
667 0 : drm_dev_exit(idx);
668 0 : return ret;
669 : }
670 :
671 : static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
672 : {
673 0 : struct psp_gfx_cmd_resp *cmd = psp->cmd;
674 :
675 0 : mutex_lock(&psp->mutex);
676 :
677 0 : memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
678 :
679 : return cmd;
680 : }
681 :
682 : static void release_psp_cmd_buf(struct psp_context *psp)
683 : {
684 0 : mutex_unlock(&psp->mutex);
685 : }
686 :
687 0 : static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
688 : struct psp_gfx_cmd_resp *cmd,
689 : uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
690 : {
691 0 : struct amdgpu_device *adev = psp->adev;
692 0 : uint32_t size = amdgpu_bo_size(tmr_bo);
693 0 : uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
694 :
695 0 : if (amdgpu_sriov_vf(psp->adev))
696 0 : cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
697 : else
698 0 : cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
699 0 : cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
700 0 : cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
701 0 : cmd->cmd.cmd_setup_tmr.buf_size = size;
702 0 : cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
703 0 : cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
704 0 : cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
705 0 : }
706 :
707 : static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
708 : uint64_t pri_buf_mc, uint32_t size)
709 : {
710 0 : cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
711 0 : cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
712 0 : cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
713 0 : cmd->cmd.cmd_load_toc.toc_size = size;
714 : }
715 :
716 : /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
717 0 : static int psp_load_toc(struct psp_context *psp,
718 : uint32_t *tmr_size)
719 : {
720 : int ret;
721 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
722 :
723 : /* Copy toc to psp firmware private buffer */
724 0 : psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
725 :
726 0 : psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
727 :
728 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
729 : psp->fence_buf_mc_addr);
730 0 : if (!ret)
731 0 : *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
732 :
733 0 : release_psp_cmd_buf(psp);
734 :
735 0 : return ret;
736 : }
737 :
738 : /* Set up Trusted Memory Region */
739 0 : static int psp_tmr_init(struct psp_context *psp)
740 : {
741 : int ret;
742 : int tmr_size;
743 : void *tmr_buf;
744 : void **pptr;
745 :
746 : /*
747 : * According to HW engineer, they prefer the TMR address be "naturally
748 : * aligned" , e.g. the start address be an integer divide of TMR size.
749 : *
750 : * Note: this memory need be reserved till the driver
751 : * uninitializes.
752 : */
753 0 : tmr_size = PSP_TMR_SIZE(psp->adev);
754 :
755 : /* For ASICs support RLC autoload, psp will parse the toc
756 : * and calculate the total size of TMR needed */
757 0 : if (!amdgpu_sriov_vf(psp->adev) &&
758 0 : psp->toc.start_addr &&
759 0 : psp->toc.size_bytes &&
760 0 : psp->fw_pri_buf) {
761 0 : ret = psp_load_toc(psp, &tmr_size);
762 0 : if (ret) {
763 0 : DRM_ERROR("Failed to load toc\n");
764 0 : return ret;
765 : }
766 : }
767 :
768 0 : pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
769 0 : ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
770 : AMDGPU_GEM_DOMAIN_VRAM,
771 0 : &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
772 :
773 0 : return ret;
774 : }
775 :
776 : static bool psp_skip_tmr(struct psp_context *psp)
777 : {
778 0 : switch (psp->adev->ip_versions[MP0_HWIP][0]) {
779 : case IP_VERSION(11, 0, 9):
780 : case IP_VERSION(11, 0, 7):
781 : case IP_VERSION(13, 0, 2):
782 : case IP_VERSION(13, 0, 10):
783 : return true;
784 : default:
785 : return false;
786 : }
787 : }
788 :
789 0 : static int psp_tmr_load(struct psp_context *psp)
790 : {
791 : int ret;
792 : struct psp_gfx_cmd_resp *cmd;
793 :
794 : /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
795 : * Already set up by host driver.
796 : */
797 0 : if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
798 : return 0;
799 :
800 0 : cmd = acquire_psp_cmd_buf(psp);
801 :
802 0 : psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
803 0 : DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
804 : amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
805 :
806 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
807 : psp->fence_buf_mc_addr);
808 :
809 0 : release_psp_cmd_buf(psp);
810 :
811 0 : return ret;
812 : }
813 :
814 : static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
815 : struct psp_gfx_cmd_resp *cmd)
816 : {
817 0 : if (amdgpu_sriov_vf(psp->adev))
818 0 : cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
819 : else
820 0 : cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
821 : }
822 :
823 0 : static int psp_tmr_unload(struct psp_context *psp)
824 : {
825 : int ret;
826 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
827 :
828 0 : psp_prep_tmr_unload_cmd_buf(psp, cmd);
829 0 : dev_info(psp->adev->dev, "free PSP TMR buffer\n");
830 :
831 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
832 : psp->fence_buf_mc_addr);
833 :
834 0 : release_psp_cmd_buf(psp);
835 :
836 0 : return ret;
837 : }
838 :
839 : static int psp_tmr_terminate(struct psp_context *psp)
840 : {
841 0 : return psp_tmr_unload(psp);
842 : }
843 :
844 0 : int psp_get_fw_attestation_records_addr(struct psp_context *psp,
845 : uint64_t *output_ptr)
846 : {
847 : int ret;
848 : struct psp_gfx_cmd_resp *cmd;
849 :
850 0 : if (!output_ptr)
851 : return -EINVAL;
852 :
853 0 : if (amdgpu_sriov_vf(psp->adev))
854 : return 0;
855 :
856 0 : cmd = acquire_psp_cmd_buf(psp);
857 :
858 0 : cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
859 :
860 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
861 : psp->fence_buf_mc_addr);
862 :
863 0 : if (!ret) {
864 0 : *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
865 0 : ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
866 : }
867 :
868 0 : release_psp_cmd_buf(psp);
869 :
870 0 : return ret;
871 : }
872 :
873 0 : static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
874 : {
875 0 : struct psp_context *psp = &adev->psp;
876 : struct psp_gfx_cmd_resp *cmd;
877 : int ret;
878 :
879 0 : if (amdgpu_sriov_vf(adev))
880 : return 0;
881 :
882 0 : cmd = acquire_psp_cmd_buf(psp);
883 :
884 0 : cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
885 0 : cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
886 :
887 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
888 0 : if (!ret) {
889 0 : *boot_cfg =
890 0 : (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
891 : }
892 :
893 0 : release_psp_cmd_buf(psp);
894 :
895 0 : return ret;
896 : }
897 :
898 0 : static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
899 : {
900 : int ret;
901 0 : struct psp_context *psp = &adev->psp;
902 : struct psp_gfx_cmd_resp *cmd;
903 :
904 0 : if (amdgpu_sriov_vf(adev))
905 : return 0;
906 :
907 0 : cmd = acquire_psp_cmd_buf(psp);
908 :
909 0 : cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
910 0 : cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
911 0 : cmd->cmd.boot_cfg.boot_config = boot_cfg;
912 0 : cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
913 :
914 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
915 :
916 0 : release_psp_cmd_buf(psp);
917 :
918 0 : return ret;
919 : }
920 :
921 0 : static int psp_rl_load(struct amdgpu_device *adev)
922 : {
923 : int ret;
924 0 : struct psp_context *psp = &adev->psp;
925 : struct psp_gfx_cmd_resp *cmd;
926 :
927 0 : if (!is_psp_fw_valid(psp->rl))
928 : return 0;
929 :
930 0 : cmd = acquire_psp_cmd_buf(psp);
931 :
932 0 : memset(psp->fw_pri_buf, 0, PSP_1_MEG);
933 0 : memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
934 :
935 0 : cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
936 0 : cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
937 0 : cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
938 0 : cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
939 0 : cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
940 :
941 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
942 :
943 0 : release_psp_cmd_buf(psp);
944 :
945 0 : return ret;
946 : }
947 :
948 0 : static int psp_asd_initialize(struct psp_context *psp)
949 : {
950 : int ret;
951 :
952 : /* If PSP version doesn't match ASD version, asd loading will be failed.
953 : * add workaround to bypass it for sriov now.
954 : * TODO: add version check to make it common
955 : */
956 0 : if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
957 : return 0;
958 :
959 0 : psp->asd_context.mem_context.shared_mc_addr = 0;
960 0 : psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
961 0 : psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
962 :
963 0 : ret = psp_ta_load(psp, &psp->asd_context);
964 0 : if (!ret)
965 0 : psp->asd_context.initialized = true;
966 :
967 : return ret;
968 : }
969 :
970 : static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
971 : uint32_t session_id)
972 : {
973 0 : cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
974 0 : cmd->cmd.cmd_unload_ta.session_id = session_id;
975 : }
976 :
977 0 : int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
978 : {
979 : int ret;
980 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
981 :
982 0 : psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
983 :
984 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
985 :
986 0 : release_psp_cmd_buf(psp);
987 :
988 0 : return ret;
989 : }
990 :
991 0 : static int psp_asd_terminate(struct psp_context *psp)
992 : {
993 : int ret;
994 :
995 0 : if (amdgpu_sriov_vf(psp->adev))
996 : return 0;
997 :
998 0 : if (!psp->asd_context.initialized)
999 : return 0;
1000 :
1001 0 : ret = psp_ta_unload(psp, &psp->asd_context);
1002 0 : if (!ret)
1003 0 : psp->asd_context.initialized = false;
1004 :
1005 : return ret;
1006 : }
1007 :
1008 : static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1009 : uint32_t id, uint32_t value)
1010 : {
1011 0 : cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1012 0 : cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1013 0 : cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1014 : }
1015 :
1016 0 : int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1017 : uint32_t value)
1018 : {
1019 : struct psp_gfx_cmd_resp *cmd;
1020 0 : int ret = 0;
1021 :
1022 0 : if (reg >= PSP_REG_LAST)
1023 : return -EINVAL;
1024 :
1025 0 : cmd = acquire_psp_cmd_buf(psp);
1026 :
1027 0 : psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1028 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1029 0 : if (ret)
1030 0 : DRM_ERROR("PSP failed to program reg id %d", reg);
1031 :
1032 0 : release_psp_cmd_buf(psp);
1033 :
1034 0 : return ret;
1035 : }
1036 :
1037 : static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1038 : uint64_t ta_bin_mc,
1039 : struct ta_context *context)
1040 : {
1041 0 : cmd->cmd_id = context->ta_load_type;
1042 0 : cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1043 0 : cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1044 0 : cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1045 :
1046 0 : cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1047 0 : lower_32_bits(context->mem_context.shared_mc_addr);
1048 0 : cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1049 0 : upper_32_bits(context->mem_context.shared_mc_addr);
1050 0 : cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1051 : }
1052 :
1053 0 : int psp_ta_init_shared_buf(struct psp_context *psp,
1054 : struct ta_mem_context *mem_ctx)
1055 : {
1056 : /*
1057 : * Allocate 16k memory aligned to 4k from Frame Buffer (local
1058 : * physical) for ta to host memory
1059 : */
1060 0 : return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1061 : PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1062 : &mem_ctx->shared_bo,
1063 0 : &mem_ctx->shared_mc_addr,
1064 : &mem_ctx->shared_buf);
1065 : }
1066 :
1067 : static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1068 : uint32_t ta_cmd_id,
1069 : struct ta_context *context)
1070 : {
1071 0 : cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1072 0 : cmd->cmd.cmd_invoke_cmd.session_id = context->session_id;
1073 0 : cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1074 :
1075 0 : cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1;
1076 0 : cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
1077 0 : cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
1078 0 : cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
1079 0 : lower_32_bits(context->mem_context.shared_mc_addr);
1080 0 : cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
1081 0 : upper_32_bits(context->mem_context.shared_mc_addr);
1082 : }
1083 :
1084 0 : int psp_ta_invoke_indirect(struct psp_context *psp,
1085 : uint32_t ta_cmd_id,
1086 : struct ta_context *context)
1087 : {
1088 : int ret;
1089 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1090 :
1091 0 : psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
1092 :
1093 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
1094 : psp->fence_buf_mc_addr);
1095 :
1096 0 : context->resp_status = cmd->resp.status;
1097 :
1098 0 : release_psp_cmd_buf(psp);
1099 :
1100 0 : return ret;
1101 : }
1102 :
1103 : static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1104 : uint32_t ta_cmd_id,
1105 : uint32_t session_id)
1106 : {
1107 0 : cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1108 0 : cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1109 0 : cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1110 : }
1111 :
1112 0 : int psp_ta_invoke(struct psp_context *psp,
1113 : uint32_t ta_cmd_id,
1114 : struct ta_context *context)
1115 : {
1116 : int ret;
1117 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1118 :
1119 0 : psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1120 :
1121 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
1122 : psp->fence_buf_mc_addr);
1123 :
1124 0 : context->resp_status = cmd->resp.status;
1125 :
1126 0 : release_psp_cmd_buf(psp);
1127 :
1128 0 : return ret;
1129 : }
1130 :
1131 0 : int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1132 : {
1133 : int ret;
1134 : struct psp_gfx_cmd_resp *cmd;
1135 :
1136 0 : cmd = acquire_psp_cmd_buf(psp);
1137 :
1138 0 : psp_copy_fw(psp, context->bin_desc.start_addr,
1139 : context->bin_desc.size_bytes);
1140 :
1141 0 : psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1142 :
1143 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
1144 : psp->fence_buf_mc_addr);
1145 :
1146 0 : context->resp_status = cmd->resp.status;
1147 :
1148 0 : if (!ret) {
1149 0 : context->session_id = cmd->resp.session_id;
1150 : }
1151 :
1152 0 : release_psp_cmd_buf(psp);
1153 :
1154 0 : return ret;
1155 : }
1156 :
1157 0 : int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1158 : {
1159 0 : return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1160 : }
1161 :
1162 0 : int psp_xgmi_terminate(struct psp_context *psp)
1163 : {
1164 : int ret;
1165 0 : struct amdgpu_device *adev = psp->adev;
1166 :
1167 : /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1168 0 : if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1169 0 : (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1170 0 : adev->gmc.xgmi.connected_to_cpu))
1171 : return 0;
1172 :
1173 0 : if (!psp->xgmi_context.context.initialized)
1174 : return 0;
1175 :
1176 0 : ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1177 :
1178 0 : psp->xgmi_context.context.initialized = false;
1179 :
1180 0 : return ret;
1181 : }
1182 :
1183 0 : int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1184 : {
1185 : struct ta_xgmi_shared_memory *xgmi_cmd;
1186 : int ret;
1187 :
1188 0 : if (!psp->ta_fw ||
1189 0 : !psp->xgmi_context.context.bin_desc.size_bytes ||
1190 0 : !psp->xgmi_context.context.bin_desc.start_addr)
1191 : return -ENOENT;
1192 :
1193 0 : if (!load_ta)
1194 : goto invoke;
1195 :
1196 0 : psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1197 0 : psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1198 :
1199 0 : if (!psp->xgmi_context.context.mem_context.shared_buf) {
1200 0 : ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1201 0 : if (ret)
1202 : return ret;
1203 : }
1204 :
1205 : /* Load XGMI TA */
1206 0 : ret = psp_ta_load(psp, &psp->xgmi_context.context);
1207 0 : if (!ret)
1208 0 : psp->xgmi_context.context.initialized = true;
1209 : else
1210 : return ret;
1211 :
1212 : invoke:
1213 : /* Initialize XGMI session */
1214 0 : xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1215 0 : memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1216 0 : xgmi_cmd->flag_extend_link_record = set_extended_data;
1217 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1218 :
1219 0 : ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1220 :
1221 0 : return ret;
1222 : }
1223 :
1224 0 : int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1225 : {
1226 : struct ta_xgmi_shared_memory *xgmi_cmd;
1227 : int ret;
1228 :
1229 0 : xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1230 0 : memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1231 :
1232 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1233 :
1234 : /* Invoke xgmi ta to get hive id */
1235 0 : ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1236 0 : if (ret)
1237 : return ret;
1238 :
1239 0 : *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1240 :
1241 0 : return 0;
1242 : }
1243 :
1244 0 : int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1245 : {
1246 : struct ta_xgmi_shared_memory *xgmi_cmd;
1247 : int ret;
1248 :
1249 0 : xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1250 0 : memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1251 :
1252 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1253 :
1254 : /* Invoke xgmi ta to get the node id */
1255 0 : ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1256 0 : if (ret)
1257 : return ret;
1258 :
1259 0 : *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1260 :
1261 0 : return 0;
1262 : }
1263 :
1264 : static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1265 : {
1266 0 : return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1267 0 : psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1268 : }
1269 :
1270 : /*
1271 : * Chips that support extended topology information require the driver to
1272 : * reflect topology information in the opposite direction. This is
1273 : * because the TA has already exceeded its link record limit and if the
1274 : * TA holds bi-directional information, the driver would have to do
1275 : * multiple fetches instead of just two.
1276 : */
1277 0 : static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1278 : struct psp_xgmi_node_info node_info)
1279 : {
1280 : struct amdgpu_device *mirror_adev;
1281 : struct amdgpu_hive_info *hive;
1282 0 : uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1283 0 : uint64_t dst_node_id = node_info.node_id;
1284 0 : uint8_t dst_num_hops = node_info.num_hops;
1285 0 : uint8_t dst_num_links = node_info.num_links;
1286 :
1287 0 : hive = amdgpu_get_xgmi_hive(psp->adev);
1288 0 : list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1289 : struct psp_xgmi_topology_info *mirror_top_info;
1290 : int j;
1291 :
1292 0 : if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1293 0 : continue;
1294 :
1295 : mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1296 0 : for (j = 0; j < mirror_top_info->num_nodes; j++) {
1297 0 : if (mirror_top_info->nodes[j].node_id != src_node_id)
1298 0 : continue;
1299 :
1300 0 : mirror_top_info->nodes[j].num_hops = dst_num_hops;
1301 : /*
1302 : * prevent 0 num_links value re-reflection since reflection
1303 : * criteria is based on num_hops (direct or indirect).
1304 : *
1305 : */
1306 0 : if (dst_num_links)
1307 0 : mirror_top_info->nodes[j].num_links = dst_num_links;
1308 :
1309 : break;
1310 : }
1311 :
1312 : break;
1313 : }
1314 :
1315 0 : amdgpu_put_xgmi_hive(hive);
1316 0 : }
1317 :
1318 0 : int psp_xgmi_get_topology_info(struct psp_context *psp,
1319 : int number_devices,
1320 : struct psp_xgmi_topology_info *topology,
1321 : bool get_extended_data)
1322 : {
1323 : struct ta_xgmi_shared_memory *xgmi_cmd;
1324 : struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1325 : struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1326 : int i;
1327 : int ret;
1328 :
1329 0 : if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1330 : return -EINVAL;
1331 :
1332 0 : xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1333 0 : memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1334 0 : xgmi_cmd->flag_extend_link_record = get_extended_data;
1335 :
1336 : /* Fill in the shared memory with topology information as input */
1337 0 : topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1338 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1339 0 : topology_info_input->num_nodes = number_devices;
1340 :
1341 0 : for (i = 0; i < topology_info_input->num_nodes; i++) {
1342 0 : topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1343 0 : topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1344 0 : topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1345 0 : topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1346 : }
1347 :
1348 : /* Invoke xgmi ta to get the topology information */
1349 0 : ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1350 0 : if (ret)
1351 : return ret;
1352 :
1353 : /* Read the output topology information from the shared memory */
1354 0 : topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1355 0 : topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1356 0 : for (i = 0; i < topology->num_nodes; i++) {
1357 : /* extended data will either be 0 or equal to non-extended data */
1358 0 : if (topology_info_output->nodes[i].num_hops)
1359 0 : topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1360 :
1361 : /* non-extended data gets everything here so no need to update */
1362 0 : if (!get_extended_data) {
1363 0 : topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1364 0 : topology->nodes[i].is_sharing_enabled =
1365 0 : topology_info_output->nodes[i].is_sharing_enabled;
1366 0 : topology->nodes[i].sdma_engine =
1367 0 : topology_info_output->nodes[i].sdma_engine;
1368 : }
1369 :
1370 : }
1371 :
1372 : /* Invoke xgmi ta again to get the link information */
1373 0 : if (psp_xgmi_peer_link_info_supported(psp)) {
1374 : struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1375 :
1376 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1377 :
1378 0 : ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1379 :
1380 0 : if (ret)
1381 : return ret;
1382 :
1383 : link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1384 0 : for (i = 0; i < topology->num_nodes; i++) {
1385 : /* accumulate num_links on extended data */
1386 0 : topology->nodes[i].num_links = get_extended_data ?
1387 0 : topology->nodes[i].num_links +
1388 0 : link_info_output->nodes[i].num_links :
1389 : link_info_output->nodes[i].num_links;
1390 :
1391 : /* reflect the topology information for bi-directionality */
1392 0 : if (psp->xgmi_context.supports_extended_data &&
1393 0 : get_extended_data && topology->nodes[i].num_hops)
1394 0 : psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1395 : }
1396 : }
1397 :
1398 : return 0;
1399 : }
1400 :
1401 0 : int psp_xgmi_set_topology_info(struct psp_context *psp,
1402 : int number_devices,
1403 : struct psp_xgmi_topology_info *topology)
1404 : {
1405 : struct ta_xgmi_shared_memory *xgmi_cmd;
1406 : struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1407 : int i;
1408 :
1409 0 : if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1410 : return -EINVAL;
1411 :
1412 0 : xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1413 0 : memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1414 :
1415 0 : topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1416 0 : xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1417 0 : topology_info_input->num_nodes = number_devices;
1418 :
1419 0 : for (i = 0; i < topology_info_input->num_nodes; i++) {
1420 0 : topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1421 0 : topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1422 0 : topology_info_input->nodes[i].is_sharing_enabled = 1;
1423 0 : topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1424 : }
1425 :
1426 : /* Invoke xgmi ta to set topology information */
1427 0 : return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1428 : }
1429 :
1430 : // ras begin
1431 0 : static void psp_ras_ta_check_status(struct psp_context *psp)
1432 : {
1433 0 : struct ta_ras_shared_memory *ras_cmd =
1434 : (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1435 :
1436 0 : switch (ras_cmd->ras_status) {
1437 : case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1438 0 : dev_warn(psp->adev->dev,
1439 : "RAS WARNING: cmd failed due to unsupported ip\n");
1440 : break;
1441 : case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1442 0 : dev_warn(psp->adev->dev,
1443 : "RAS WARNING: cmd failed due to unsupported error injection\n");
1444 : break;
1445 : case TA_RAS_STATUS__SUCCESS:
1446 : break;
1447 : case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1448 0 : if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1449 0 : dev_warn(psp->adev->dev,
1450 : "RAS WARNING: Inject error to critical region is not allowed\n");
1451 : break;
1452 : default:
1453 0 : dev_warn(psp->adev->dev,
1454 : "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1455 : break;
1456 : }
1457 0 : }
1458 :
1459 0 : int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1460 : {
1461 : struct ta_ras_shared_memory *ras_cmd;
1462 : int ret;
1463 :
1464 0 : ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1465 :
1466 : /*
1467 : * TODO: bypass the loading in sriov for now
1468 : */
1469 0 : if (amdgpu_sriov_vf(psp->adev))
1470 : return 0;
1471 :
1472 0 : ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1473 :
1474 0 : if (amdgpu_ras_intr_triggered())
1475 : return ret;
1476 :
1477 0 : if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1478 : {
1479 0 : DRM_WARN("RAS: Unsupported Interface");
1480 0 : return -EINVAL;
1481 : }
1482 :
1483 0 : if (!ret) {
1484 0 : if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1485 0 : dev_warn(psp->adev->dev, "ECC switch disabled\n");
1486 :
1487 0 : ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1488 : }
1489 0 : else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1490 0 : dev_warn(psp->adev->dev,
1491 : "RAS internal register access blocked\n");
1492 :
1493 0 : psp_ras_ta_check_status(psp);
1494 : }
1495 :
1496 : return ret;
1497 : }
1498 :
1499 0 : int psp_ras_enable_features(struct psp_context *psp,
1500 : union ta_ras_cmd_input *info, bool enable)
1501 : {
1502 : struct ta_ras_shared_memory *ras_cmd;
1503 : int ret;
1504 :
1505 0 : if (!psp->ras_context.context.initialized)
1506 : return -EINVAL;
1507 :
1508 0 : ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1509 0 : memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1510 :
1511 0 : if (enable)
1512 0 : ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1513 : else
1514 0 : ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1515 :
1516 0 : ras_cmd->ras_in_message = *info;
1517 :
1518 0 : ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1519 0 : if (ret)
1520 : return -EINVAL;
1521 :
1522 0 : return 0;
1523 : }
1524 :
1525 0 : int psp_ras_terminate(struct psp_context *psp)
1526 : {
1527 : int ret;
1528 :
1529 : /*
1530 : * TODO: bypass the terminate in sriov for now
1531 : */
1532 0 : if (amdgpu_sriov_vf(psp->adev))
1533 : return 0;
1534 :
1535 0 : if (!psp->ras_context.context.initialized)
1536 : return 0;
1537 :
1538 0 : ret = psp_ta_unload(psp, &psp->ras_context.context);
1539 :
1540 0 : psp->ras_context.context.initialized = false;
1541 :
1542 0 : return ret;
1543 : }
1544 :
1545 0 : static int psp_ras_initialize(struct psp_context *psp)
1546 : {
1547 : int ret;
1548 0 : uint32_t boot_cfg = 0xFF;
1549 0 : struct amdgpu_device *adev = psp->adev;
1550 : struct ta_ras_shared_memory *ras_cmd;
1551 :
1552 : /*
1553 : * TODO: bypass the initialize in sriov for now
1554 : */
1555 0 : if (amdgpu_sriov_vf(adev))
1556 : return 0;
1557 :
1558 0 : if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1559 0 : !adev->psp.ras_context.context.bin_desc.start_addr) {
1560 0 : dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1561 0 : return 0;
1562 : }
1563 :
1564 0 : if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1565 : /* query GECC enablement status from boot config
1566 : * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1567 : */
1568 0 : ret = psp_boot_config_get(adev, &boot_cfg);
1569 0 : if (ret)
1570 0 : dev_warn(adev->dev, "PSP get boot config failed\n");
1571 :
1572 0 : if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1573 0 : if (!boot_cfg) {
1574 0 : dev_info(adev->dev, "GECC is disabled\n");
1575 : } else {
1576 : /* disable GECC in next boot cycle if ras is
1577 : * disabled by module parameter amdgpu_ras_enable
1578 : * and/or amdgpu_ras_mask, or boot_config_get call
1579 : * is failed
1580 : */
1581 0 : ret = psp_boot_config_set(adev, 0);
1582 0 : if (ret)
1583 0 : dev_warn(adev->dev, "PSP set boot config failed\n");
1584 : else
1585 0 : dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1586 : "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1587 : }
1588 : } else {
1589 0 : if (1 == boot_cfg) {
1590 0 : dev_info(adev->dev, "GECC is enabled\n");
1591 : } else {
1592 : /* enable GECC in next boot cycle if it is disabled
1593 : * in boot config, or force enable GECC if failed to
1594 : * get boot configuration
1595 : */
1596 0 : ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1597 0 : if (ret)
1598 0 : dev_warn(adev->dev, "PSP set boot config failed\n");
1599 : else
1600 0 : dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1601 : }
1602 : }
1603 : }
1604 :
1605 0 : psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1606 0 : psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1607 :
1608 0 : if (!psp->ras_context.context.initialized) {
1609 0 : ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1610 0 : if (ret)
1611 : return ret;
1612 : }
1613 :
1614 0 : ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1615 0 : memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1616 :
1617 0 : if (amdgpu_ras_is_poison_mode_supported(adev))
1618 0 : ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1619 0 : if (!adev->gmc.xgmi.connected_to_cpu)
1620 0 : ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1621 :
1622 0 : ret = psp_ta_load(psp, &psp->ras_context.context);
1623 :
1624 0 : if (!ret && !ras_cmd->ras_status)
1625 0 : psp->ras_context.context.initialized = true;
1626 : else {
1627 0 : if (ras_cmd->ras_status)
1628 0 : dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1629 0 : amdgpu_ras_fini(psp->adev);
1630 : }
1631 :
1632 : return ret;
1633 : }
1634 :
1635 0 : int psp_ras_trigger_error(struct psp_context *psp,
1636 : struct ta_ras_trigger_error_input *info)
1637 : {
1638 : struct ta_ras_shared_memory *ras_cmd;
1639 : int ret;
1640 :
1641 0 : if (!psp->ras_context.context.initialized)
1642 : return -EINVAL;
1643 :
1644 0 : ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1645 0 : memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1646 :
1647 0 : ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1648 0 : ras_cmd->ras_in_message.trigger_error = *info;
1649 :
1650 0 : ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1651 0 : if (ret)
1652 : return -EINVAL;
1653 :
1654 : /* If err_event_athub occurs error inject was successful, however
1655 : return status from TA is no long reliable */
1656 0 : if (amdgpu_ras_intr_triggered())
1657 : return 0;
1658 :
1659 0 : if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1660 : return -EACCES;
1661 0 : else if (ras_cmd->ras_status)
1662 : return -EINVAL;
1663 :
1664 0 : return 0;
1665 : }
1666 : // ras end
1667 :
1668 : // HDCP start
1669 0 : static int psp_hdcp_initialize(struct psp_context *psp)
1670 : {
1671 : int ret;
1672 :
1673 : /*
1674 : * TODO: bypass the initialize in sriov for now
1675 : */
1676 0 : if (amdgpu_sriov_vf(psp->adev))
1677 : return 0;
1678 :
1679 0 : if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1680 0 : !psp->hdcp_context.context.bin_desc.start_addr) {
1681 0 : dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1682 0 : return 0;
1683 : }
1684 :
1685 0 : psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1686 0 : psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1687 :
1688 0 : if (!psp->hdcp_context.context.initialized) {
1689 0 : ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1690 0 : if (ret)
1691 : return ret;
1692 : }
1693 :
1694 0 : ret = psp_ta_load(psp, &psp->hdcp_context.context);
1695 0 : if (!ret) {
1696 0 : psp->hdcp_context.context.initialized = true;
1697 0 : mutex_init(&psp->hdcp_context.mutex);
1698 : }
1699 :
1700 : return ret;
1701 : }
1702 :
1703 0 : int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1704 : {
1705 : /*
1706 : * TODO: bypass the loading in sriov for now
1707 : */
1708 0 : if (amdgpu_sriov_vf(psp->adev))
1709 : return 0;
1710 :
1711 0 : return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1712 : }
1713 :
1714 0 : static int psp_hdcp_terminate(struct psp_context *psp)
1715 : {
1716 : int ret;
1717 :
1718 : /*
1719 : * TODO: bypass the terminate in sriov for now
1720 : */
1721 0 : if (amdgpu_sriov_vf(psp->adev))
1722 : return 0;
1723 :
1724 0 : if (!psp->hdcp_context.context.initialized)
1725 : return 0;
1726 :
1727 0 : ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1728 :
1729 0 : psp->hdcp_context.context.initialized = false;
1730 :
1731 0 : return ret;
1732 : }
1733 : // HDCP end
1734 :
1735 : // DTM start
1736 0 : static int psp_dtm_initialize(struct psp_context *psp)
1737 : {
1738 : int ret;
1739 :
1740 : /*
1741 : * TODO: bypass the initialize in sriov for now
1742 : */
1743 0 : if (amdgpu_sriov_vf(psp->adev))
1744 : return 0;
1745 :
1746 0 : if (!psp->dtm_context.context.bin_desc.size_bytes ||
1747 0 : !psp->dtm_context.context.bin_desc.start_addr) {
1748 0 : dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1749 0 : return 0;
1750 : }
1751 :
1752 0 : psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1753 0 : psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1754 :
1755 0 : if (!psp->dtm_context.context.initialized) {
1756 0 : ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1757 0 : if (ret)
1758 : return ret;
1759 : }
1760 :
1761 0 : ret = psp_ta_load(psp, &psp->dtm_context.context);
1762 0 : if (!ret) {
1763 0 : psp->dtm_context.context.initialized = true;
1764 0 : mutex_init(&psp->dtm_context.mutex);
1765 : }
1766 :
1767 : return ret;
1768 : }
1769 :
1770 0 : int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1771 : {
1772 : /*
1773 : * TODO: bypass the loading in sriov for now
1774 : */
1775 0 : if (amdgpu_sriov_vf(psp->adev))
1776 : return 0;
1777 :
1778 0 : return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1779 : }
1780 :
1781 0 : static int psp_dtm_terminate(struct psp_context *psp)
1782 : {
1783 : int ret;
1784 :
1785 : /*
1786 : * TODO: bypass the terminate in sriov for now
1787 : */
1788 0 : if (amdgpu_sriov_vf(psp->adev))
1789 : return 0;
1790 :
1791 0 : if (!psp->dtm_context.context.initialized)
1792 : return 0;
1793 :
1794 0 : ret = psp_ta_unload(psp, &psp->dtm_context.context);
1795 :
1796 0 : psp->dtm_context.context.initialized = false;
1797 :
1798 0 : return ret;
1799 : }
1800 : // DTM end
1801 :
1802 : // RAP start
1803 0 : static int psp_rap_initialize(struct psp_context *psp)
1804 : {
1805 : int ret;
1806 0 : enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1807 :
1808 : /*
1809 : * TODO: bypass the initialize in sriov for now
1810 : */
1811 0 : if (amdgpu_sriov_vf(psp->adev))
1812 : return 0;
1813 :
1814 0 : if (!psp->rap_context.context.bin_desc.size_bytes ||
1815 0 : !psp->rap_context.context.bin_desc.start_addr) {
1816 0 : dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1817 0 : return 0;
1818 : }
1819 :
1820 0 : psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1821 0 : psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1822 :
1823 0 : if (!psp->rap_context.context.initialized) {
1824 0 : ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1825 0 : if (ret)
1826 : return ret;
1827 : }
1828 :
1829 0 : ret = psp_ta_load(psp, &psp->rap_context.context);
1830 0 : if (!ret) {
1831 0 : psp->rap_context.context.initialized = true;
1832 0 : mutex_init(&psp->rap_context.mutex);
1833 : } else
1834 : return ret;
1835 :
1836 0 : ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1837 0 : if (ret || status != TA_RAP_STATUS__SUCCESS) {
1838 0 : psp_rap_terminate(psp);
1839 : /* free rap shared memory */
1840 0 : psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1841 :
1842 0 : dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1843 : ret, status);
1844 :
1845 0 : return ret;
1846 : }
1847 :
1848 : return 0;
1849 : }
1850 :
1851 : static int psp_rap_terminate(struct psp_context *psp)
1852 : {
1853 : int ret;
1854 :
1855 0 : if (!psp->rap_context.context.initialized)
1856 : return 0;
1857 :
1858 0 : ret = psp_ta_unload(psp, &psp->rap_context.context);
1859 :
1860 0 : psp->rap_context.context.initialized = false;
1861 :
1862 : return ret;
1863 : }
1864 :
1865 0 : int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1866 : {
1867 : struct ta_rap_shared_memory *rap_cmd;
1868 0 : int ret = 0;
1869 :
1870 0 : if (!psp->rap_context.context.initialized)
1871 : return 0;
1872 :
1873 0 : if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1874 : ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1875 : return -EINVAL;
1876 :
1877 0 : mutex_lock(&psp->rap_context.mutex);
1878 :
1879 0 : rap_cmd = (struct ta_rap_shared_memory *)
1880 : psp->rap_context.context.mem_context.shared_buf;
1881 0 : memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1882 :
1883 0 : rap_cmd->cmd_id = ta_cmd_id;
1884 0 : rap_cmd->validation_method_id = METHOD_A;
1885 :
1886 0 : ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1887 0 : if (ret)
1888 : goto out_unlock;
1889 :
1890 0 : if (status)
1891 0 : *status = rap_cmd->rap_status;
1892 :
1893 : out_unlock:
1894 0 : mutex_unlock(&psp->rap_context.mutex);
1895 :
1896 0 : return ret;
1897 : }
1898 : // RAP end
1899 :
1900 : /* securedisplay start */
1901 0 : static int psp_securedisplay_initialize(struct psp_context *psp)
1902 : {
1903 : int ret;
1904 : struct securedisplay_cmd *securedisplay_cmd;
1905 :
1906 : /*
1907 : * TODO: bypass the initialize in sriov for now
1908 : */
1909 0 : if (amdgpu_sriov_vf(psp->adev))
1910 : return 0;
1911 :
1912 0 : if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1913 0 : !psp->securedisplay_context.context.bin_desc.start_addr) {
1914 0 : dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1915 0 : return 0;
1916 : }
1917 :
1918 0 : psp->securedisplay_context.context.mem_context.shared_mem_size =
1919 : PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1920 0 : psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1921 :
1922 0 : if (!psp->securedisplay_context.context.initialized) {
1923 0 : ret = psp_ta_init_shared_buf(psp,
1924 : &psp->securedisplay_context.context.mem_context);
1925 0 : if (ret)
1926 : return ret;
1927 : }
1928 :
1929 0 : ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1930 0 : if (!ret) {
1931 0 : psp->securedisplay_context.context.initialized = true;
1932 0 : mutex_init(&psp->securedisplay_context.mutex);
1933 : } else
1934 : return ret;
1935 :
1936 0 : psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1937 : TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1938 :
1939 0 : ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1940 0 : if (ret) {
1941 0 : psp_securedisplay_terminate(psp);
1942 : /* free securedisplay shared memory */
1943 0 : psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1944 0 : dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1945 0 : return -EINVAL;
1946 : }
1947 :
1948 0 : if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1949 0 : psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1950 0 : dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1951 : securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1952 : }
1953 :
1954 : return 0;
1955 : }
1956 :
1957 0 : static int psp_securedisplay_terminate(struct psp_context *psp)
1958 : {
1959 : int ret;
1960 :
1961 : /*
1962 : * TODO:bypass the terminate in sriov for now
1963 : */
1964 0 : if (amdgpu_sriov_vf(psp->adev))
1965 : return 0;
1966 :
1967 0 : if (!psp->securedisplay_context.context.initialized)
1968 : return 0;
1969 :
1970 0 : ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1971 :
1972 0 : psp->securedisplay_context.context.initialized = false;
1973 :
1974 0 : return ret;
1975 : }
1976 :
1977 0 : int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1978 : {
1979 : int ret;
1980 :
1981 0 : if (!psp->securedisplay_context.context.initialized)
1982 : return -EINVAL;
1983 :
1984 0 : if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1985 : ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1986 : return -EINVAL;
1987 :
1988 0 : mutex_lock(&psp->securedisplay_context.mutex);
1989 :
1990 0 : ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1991 :
1992 0 : mutex_unlock(&psp->securedisplay_context.mutex);
1993 :
1994 0 : return ret;
1995 : }
1996 : /* SECUREDISPLAY end */
1997 :
1998 0 : static int psp_hw_start(struct psp_context *psp)
1999 : {
2000 0 : struct amdgpu_device *adev = psp->adev;
2001 : int ret;
2002 :
2003 0 : if (!amdgpu_sriov_vf(adev)) {
2004 0 : if ((is_psp_fw_valid(psp->kdb)) &&
2005 0 : (psp->funcs->bootloader_load_kdb != NULL)) {
2006 0 : ret = psp_bootloader_load_kdb(psp);
2007 0 : if (ret) {
2008 0 : DRM_ERROR("PSP load kdb failed!\n");
2009 0 : return ret;
2010 : }
2011 : }
2012 :
2013 0 : if ((is_psp_fw_valid(psp->spl)) &&
2014 0 : (psp->funcs->bootloader_load_spl != NULL)) {
2015 0 : ret = psp_bootloader_load_spl(psp);
2016 0 : if (ret) {
2017 0 : DRM_ERROR("PSP load spl failed!\n");
2018 0 : return ret;
2019 : }
2020 : }
2021 :
2022 0 : if ((is_psp_fw_valid(psp->sys)) &&
2023 0 : (psp->funcs->bootloader_load_sysdrv != NULL)) {
2024 0 : ret = psp_bootloader_load_sysdrv(psp);
2025 0 : if (ret) {
2026 0 : DRM_ERROR("PSP load sys drv failed!\n");
2027 0 : return ret;
2028 : }
2029 : }
2030 :
2031 0 : if ((is_psp_fw_valid(psp->soc_drv)) &&
2032 0 : (psp->funcs->bootloader_load_soc_drv != NULL)) {
2033 0 : ret = psp_bootloader_load_soc_drv(psp);
2034 0 : if (ret) {
2035 0 : DRM_ERROR("PSP load soc drv failed!\n");
2036 0 : return ret;
2037 : }
2038 : }
2039 :
2040 0 : if ((is_psp_fw_valid(psp->intf_drv)) &&
2041 0 : (psp->funcs->bootloader_load_intf_drv != NULL)) {
2042 0 : ret = psp_bootloader_load_intf_drv(psp);
2043 0 : if (ret) {
2044 0 : DRM_ERROR("PSP load intf drv failed!\n");
2045 0 : return ret;
2046 : }
2047 : }
2048 :
2049 0 : if ((is_psp_fw_valid(psp->dbg_drv)) &&
2050 0 : (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2051 0 : ret = psp_bootloader_load_dbg_drv(psp);
2052 0 : if (ret) {
2053 0 : DRM_ERROR("PSP load dbg drv failed!\n");
2054 0 : return ret;
2055 : }
2056 : }
2057 :
2058 0 : if ((is_psp_fw_valid(psp->sos)) &&
2059 0 : (psp->funcs->bootloader_load_sos != NULL)) {
2060 0 : ret = psp_bootloader_load_sos(psp);
2061 0 : if (ret) {
2062 0 : DRM_ERROR("PSP load sos failed!\n");
2063 0 : return ret;
2064 : }
2065 : }
2066 : }
2067 :
2068 0 : ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2069 0 : if (ret) {
2070 0 : DRM_ERROR("PSP create ring failed!\n");
2071 0 : return ret;
2072 : }
2073 :
2074 0 : if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2075 : goto skip_pin_bo;
2076 :
2077 0 : ret = psp_tmr_init(psp);
2078 0 : if (ret) {
2079 0 : DRM_ERROR("PSP tmr init failed!\n");
2080 0 : return ret;
2081 : }
2082 :
2083 : skip_pin_bo:
2084 : /*
2085 : * For ASICs with DF Cstate management centralized
2086 : * to PMFW, TMR setup should be performed after PMFW
2087 : * loaded and before other non-psp firmware loaded.
2088 : */
2089 0 : if (psp->pmfw_centralized_cstate_management) {
2090 0 : ret = psp_load_smu_fw(psp);
2091 0 : if (ret)
2092 : return ret;
2093 : }
2094 :
2095 0 : ret = psp_tmr_load(psp);
2096 0 : if (ret) {
2097 0 : DRM_ERROR("PSP load tmr failed!\n");
2098 0 : return ret;
2099 : }
2100 :
2101 : return 0;
2102 : }
2103 :
2104 0 : static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2105 : enum psp_gfx_fw_type *type)
2106 : {
2107 0 : switch (ucode->ucode_id) {
2108 : case AMDGPU_UCODE_ID_CAP:
2109 0 : *type = GFX_FW_TYPE_CAP;
2110 : break;
2111 : case AMDGPU_UCODE_ID_SDMA0:
2112 0 : *type = GFX_FW_TYPE_SDMA0;
2113 : break;
2114 : case AMDGPU_UCODE_ID_SDMA1:
2115 0 : *type = GFX_FW_TYPE_SDMA1;
2116 : break;
2117 : case AMDGPU_UCODE_ID_SDMA2:
2118 0 : *type = GFX_FW_TYPE_SDMA2;
2119 : break;
2120 : case AMDGPU_UCODE_ID_SDMA3:
2121 0 : *type = GFX_FW_TYPE_SDMA3;
2122 : break;
2123 : case AMDGPU_UCODE_ID_SDMA4:
2124 0 : *type = GFX_FW_TYPE_SDMA4;
2125 : break;
2126 : case AMDGPU_UCODE_ID_SDMA5:
2127 0 : *type = GFX_FW_TYPE_SDMA5;
2128 : break;
2129 : case AMDGPU_UCODE_ID_SDMA6:
2130 0 : *type = GFX_FW_TYPE_SDMA6;
2131 : break;
2132 : case AMDGPU_UCODE_ID_SDMA7:
2133 0 : *type = GFX_FW_TYPE_SDMA7;
2134 : break;
2135 : case AMDGPU_UCODE_ID_CP_MES:
2136 0 : *type = GFX_FW_TYPE_CP_MES;
2137 : break;
2138 : case AMDGPU_UCODE_ID_CP_MES_DATA:
2139 0 : *type = GFX_FW_TYPE_MES_STACK;
2140 : break;
2141 : case AMDGPU_UCODE_ID_CP_MES1:
2142 0 : *type = GFX_FW_TYPE_CP_MES_KIQ;
2143 : break;
2144 : case AMDGPU_UCODE_ID_CP_MES1_DATA:
2145 0 : *type = GFX_FW_TYPE_MES_KIQ_STACK;
2146 : break;
2147 : case AMDGPU_UCODE_ID_CP_CE:
2148 0 : *type = GFX_FW_TYPE_CP_CE;
2149 : break;
2150 : case AMDGPU_UCODE_ID_CP_PFP:
2151 0 : *type = GFX_FW_TYPE_CP_PFP;
2152 : break;
2153 : case AMDGPU_UCODE_ID_CP_ME:
2154 0 : *type = GFX_FW_TYPE_CP_ME;
2155 : break;
2156 : case AMDGPU_UCODE_ID_CP_MEC1:
2157 0 : *type = GFX_FW_TYPE_CP_MEC;
2158 : break;
2159 : case AMDGPU_UCODE_ID_CP_MEC1_JT:
2160 0 : *type = GFX_FW_TYPE_CP_MEC_ME1;
2161 : break;
2162 : case AMDGPU_UCODE_ID_CP_MEC2:
2163 0 : *type = GFX_FW_TYPE_CP_MEC;
2164 : break;
2165 : case AMDGPU_UCODE_ID_CP_MEC2_JT:
2166 0 : *type = GFX_FW_TYPE_CP_MEC_ME2;
2167 : break;
2168 : case AMDGPU_UCODE_ID_RLC_P:
2169 0 : *type = GFX_FW_TYPE_RLC_P;
2170 : break;
2171 : case AMDGPU_UCODE_ID_RLC_V:
2172 0 : *type = GFX_FW_TYPE_RLC_V;
2173 : break;
2174 : case AMDGPU_UCODE_ID_RLC_G:
2175 0 : *type = GFX_FW_TYPE_RLC_G;
2176 : break;
2177 : case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2178 0 : *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2179 : break;
2180 : case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2181 0 : *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2182 : break;
2183 : case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2184 0 : *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2185 : break;
2186 : case AMDGPU_UCODE_ID_RLC_IRAM:
2187 0 : *type = GFX_FW_TYPE_RLC_IRAM;
2188 : break;
2189 : case AMDGPU_UCODE_ID_RLC_DRAM:
2190 0 : *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2191 : break;
2192 : case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2193 0 : *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2194 : break;
2195 : case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2196 0 : *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2197 : break;
2198 : case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2199 0 : *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2200 : break;
2201 : case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2202 0 : *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2203 : break;
2204 : case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2205 0 : *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2206 : break;
2207 : case AMDGPU_UCODE_ID_SMC:
2208 0 : *type = GFX_FW_TYPE_SMU;
2209 : break;
2210 : case AMDGPU_UCODE_ID_PPTABLE:
2211 0 : *type = GFX_FW_TYPE_PPTABLE;
2212 : break;
2213 : case AMDGPU_UCODE_ID_UVD:
2214 0 : *type = GFX_FW_TYPE_UVD;
2215 : break;
2216 : case AMDGPU_UCODE_ID_UVD1:
2217 0 : *type = GFX_FW_TYPE_UVD1;
2218 : break;
2219 : case AMDGPU_UCODE_ID_VCE:
2220 0 : *type = GFX_FW_TYPE_VCE;
2221 : break;
2222 : case AMDGPU_UCODE_ID_VCN:
2223 0 : *type = GFX_FW_TYPE_VCN;
2224 : break;
2225 : case AMDGPU_UCODE_ID_VCN1:
2226 0 : *type = GFX_FW_TYPE_VCN1;
2227 : break;
2228 : case AMDGPU_UCODE_ID_DMCU_ERAM:
2229 0 : *type = GFX_FW_TYPE_DMCU_ERAM;
2230 : break;
2231 : case AMDGPU_UCODE_ID_DMCU_INTV:
2232 0 : *type = GFX_FW_TYPE_DMCU_ISR;
2233 : break;
2234 : case AMDGPU_UCODE_ID_VCN0_RAM:
2235 0 : *type = GFX_FW_TYPE_VCN0_RAM;
2236 : break;
2237 : case AMDGPU_UCODE_ID_VCN1_RAM:
2238 0 : *type = GFX_FW_TYPE_VCN1_RAM;
2239 : break;
2240 : case AMDGPU_UCODE_ID_DMCUB:
2241 0 : *type = GFX_FW_TYPE_DMUB;
2242 : break;
2243 : case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2244 0 : *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2245 : break;
2246 : case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2247 0 : *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2248 : break;
2249 : case AMDGPU_UCODE_ID_IMU_I:
2250 0 : *type = GFX_FW_TYPE_IMU_I;
2251 : break;
2252 : case AMDGPU_UCODE_ID_IMU_D:
2253 0 : *type = GFX_FW_TYPE_IMU_D;
2254 : break;
2255 : case AMDGPU_UCODE_ID_CP_RS64_PFP:
2256 0 : *type = GFX_FW_TYPE_RS64_PFP;
2257 : break;
2258 : case AMDGPU_UCODE_ID_CP_RS64_ME:
2259 0 : *type = GFX_FW_TYPE_RS64_ME;
2260 : break;
2261 : case AMDGPU_UCODE_ID_CP_RS64_MEC:
2262 0 : *type = GFX_FW_TYPE_RS64_MEC;
2263 : break;
2264 : case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2265 0 : *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2266 : break;
2267 : case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2268 0 : *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2269 : break;
2270 : case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2271 0 : *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2272 : break;
2273 : case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2274 0 : *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2275 : break;
2276 : case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2277 0 : *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2278 : break;
2279 : case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2280 0 : *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2281 : break;
2282 : case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2283 0 : *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2284 : break;
2285 : case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2286 0 : *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2287 : break;
2288 : case AMDGPU_UCODE_ID_MAXIMUM:
2289 : default:
2290 : return -EINVAL;
2291 : }
2292 :
2293 : return 0;
2294 : }
2295 :
2296 0 : static void psp_print_fw_hdr(struct psp_context *psp,
2297 : struct amdgpu_firmware_info *ucode)
2298 : {
2299 0 : struct amdgpu_device *adev = psp->adev;
2300 : struct common_firmware_header *hdr;
2301 :
2302 0 : switch (ucode->ucode_id) {
2303 : case AMDGPU_UCODE_ID_SDMA0:
2304 : case AMDGPU_UCODE_ID_SDMA1:
2305 : case AMDGPU_UCODE_ID_SDMA2:
2306 : case AMDGPU_UCODE_ID_SDMA3:
2307 : case AMDGPU_UCODE_ID_SDMA4:
2308 : case AMDGPU_UCODE_ID_SDMA5:
2309 : case AMDGPU_UCODE_ID_SDMA6:
2310 : case AMDGPU_UCODE_ID_SDMA7:
2311 0 : hdr = (struct common_firmware_header *)
2312 0 : adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2313 0 : amdgpu_ucode_print_sdma_hdr(hdr);
2314 : break;
2315 : case AMDGPU_UCODE_ID_CP_CE:
2316 0 : hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2317 0 : amdgpu_ucode_print_gfx_hdr(hdr);
2318 : break;
2319 : case AMDGPU_UCODE_ID_CP_PFP:
2320 0 : hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2321 0 : amdgpu_ucode_print_gfx_hdr(hdr);
2322 : break;
2323 : case AMDGPU_UCODE_ID_CP_ME:
2324 0 : hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2325 0 : amdgpu_ucode_print_gfx_hdr(hdr);
2326 : break;
2327 : case AMDGPU_UCODE_ID_CP_MEC1:
2328 0 : hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2329 0 : amdgpu_ucode_print_gfx_hdr(hdr);
2330 : break;
2331 : case AMDGPU_UCODE_ID_RLC_G:
2332 0 : hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2333 0 : amdgpu_ucode_print_rlc_hdr(hdr);
2334 : break;
2335 : case AMDGPU_UCODE_ID_SMC:
2336 0 : hdr = (struct common_firmware_header *)adev->pm.fw->data;
2337 0 : amdgpu_ucode_print_smc_hdr(hdr);
2338 : break;
2339 : default:
2340 : break;
2341 : }
2342 0 : }
2343 :
2344 0 : static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2345 : struct psp_gfx_cmd_resp *cmd)
2346 : {
2347 : int ret;
2348 0 : uint64_t fw_mem_mc_addr = ucode->mc_addr;
2349 :
2350 0 : cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2351 0 : cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2352 0 : cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2353 0 : cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2354 :
2355 0 : ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2356 0 : if (ret)
2357 0 : DRM_ERROR("Unknown firmware type\n");
2358 :
2359 0 : return ret;
2360 : }
2361 :
2362 0 : static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2363 : struct amdgpu_firmware_info *ucode)
2364 : {
2365 0 : int ret = 0;
2366 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2367 :
2368 0 : ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2369 0 : if (!ret) {
2370 0 : ret = psp_cmd_submit_buf(psp, ucode, cmd,
2371 : psp->fence_buf_mc_addr);
2372 : }
2373 :
2374 0 : release_psp_cmd_buf(psp);
2375 :
2376 0 : return ret;
2377 : }
2378 :
2379 0 : static int psp_load_smu_fw(struct psp_context *psp)
2380 : {
2381 : int ret;
2382 0 : struct amdgpu_device *adev = psp->adev;
2383 0 : struct amdgpu_firmware_info *ucode =
2384 : &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2385 0 : struct amdgpu_ras *ras = psp->ras_context.ras;
2386 :
2387 : /*
2388 : * Skip SMU FW reloading in case of using BACO for runpm only,
2389 : * as SMU is always alive.
2390 : */
2391 0 : if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2392 : return 0;
2393 :
2394 0 : if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2395 : return 0;
2396 :
2397 0 : if ((amdgpu_in_reset(adev) &&
2398 0 : ras && adev->ras_enabled &&
2399 0 : (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2400 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2401 0 : ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2402 0 : if (ret) {
2403 0 : DRM_WARN("Failed to set MP1 state prepare for reload\n");
2404 : }
2405 : }
2406 :
2407 0 : ret = psp_execute_non_psp_fw_load(psp, ucode);
2408 :
2409 0 : if (ret)
2410 0 : DRM_ERROR("PSP load smu failed!\n");
2411 :
2412 : return ret;
2413 : }
2414 :
2415 0 : static bool fw_load_skip_check(struct psp_context *psp,
2416 : struct amdgpu_firmware_info *ucode)
2417 : {
2418 0 : if (!ucode->fw || !ucode->ucode_size)
2419 : return true;
2420 :
2421 0 : if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2422 0 : (psp_smu_reload_quirk(psp) ||
2423 0 : psp->autoload_supported ||
2424 : psp->pmfw_centralized_cstate_management))
2425 : return true;
2426 :
2427 0 : if (amdgpu_sriov_vf(psp->adev) &&
2428 0 : amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2429 : return true;
2430 :
2431 0 : if (psp->autoload_supported &&
2432 0 : (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2433 : ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2434 : /* skip mec JT when autoload is enabled */
2435 : return true;
2436 :
2437 0 : return false;
2438 : }
2439 :
2440 0 : int psp_load_fw_list(struct psp_context *psp,
2441 : struct amdgpu_firmware_info **ucode_list, int ucode_count)
2442 : {
2443 0 : int ret = 0, i;
2444 : struct amdgpu_firmware_info *ucode;
2445 :
2446 0 : for (i = 0; i < ucode_count; ++i) {
2447 0 : ucode = ucode_list[i];
2448 0 : psp_print_fw_hdr(psp, ucode);
2449 0 : ret = psp_execute_non_psp_fw_load(psp, ucode);
2450 0 : if (ret)
2451 : return ret;
2452 : }
2453 : return ret;
2454 : }
2455 :
2456 0 : static int psp_load_non_psp_fw(struct psp_context *psp)
2457 : {
2458 : int i, ret;
2459 : struct amdgpu_firmware_info *ucode;
2460 0 : struct amdgpu_device *adev = psp->adev;
2461 :
2462 0 : if (psp->autoload_supported &&
2463 0 : !psp->pmfw_centralized_cstate_management) {
2464 0 : ret = psp_load_smu_fw(psp);
2465 0 : if (ret)
2466 : return ret;
2467 : }
2468 :
2469 0 : for (i = 0; i < adev->firmware.max_ucodes; i++) {
2470 0 : ucode = &adev->firmware.ucode[i];
2471 :
2472 0 : if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2473 0 : !fw_load_skip_check(psp, ucode)) {
2474 0 : ret = psp_load_smu_fw(psp);
2475 0 : if (ret)
2476 : return ret;
2477 0 : continue;
2478 : }
2479 :
2480 0 : if (fw_load_skip_check(psp, ucode))
2481 0 : continue;
2482 :
2483 0 : if (psp->autoload_supported &&
2484 0 : (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2485 0 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2486 0 : adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2487 0 : (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2488 0 : ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2489 : ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2490 : /* PSP only receive one SDMA fw for sienna_cichlid,
2491 : * as all four sdma fw are same */
2492 0 : continue;
2493 :
2494 0 : psp_print_fw_hdr(psp, ucode);
2495 :
2496 0 : ret = psp_execute_non_psp_fw_load(psp, ucode);
2497 0 : if (ret)
2498 : return ret;
2499 :
2500 : /* Start rlc autoload after psp recieved all the gfx firmware */
2501 0 : if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2502 0 : adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2503 0 : ret = psp_rlc_autoload_start(psp);
2504 0 : if (ret) {
2505 0 : DRM_ERROR("Failed to start rlc autoload\n");
2506 0 : return ret;
2507 : }
2508 : }
2509 : }
2510 :
2511 : return 0;
2512 : }
2513 :
2514 0 : static int psp_load_fw(struct amdgpu_device *adev)
2515 : {
2516 : int ret;
2517 0 : struct psp_context *psp = &adev->psp;
2518 :
2519 0 : if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2520 : /* should not destroy ring, only stop */
2521 0 : psp_ring_stop(psp, PSP_RING_TYPE__KM);
2522 : } else {
2523 0 : memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2524 :
2525 0 : ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2526 0 : if (ret) {
2527 0 : DRM_ERROR("PSP ring init failed!\n");
2528 0 : goto failed;
2529 : }
2530 : }
2531 :
2532 0 : ret = psp_hw_start(psp);
2533 0 : if (ret)
2534 : goto failed;
2535 :
2536 0 : ret = psp_load_non_psp_fw(psp);
2537 0 : if (ret)
2538 : goto failed1;
2539 :
2540 0 : ret = psp_asd_initialize(psp);
2541 0 : if (ret) {
2542 0 : DRM_ERROR("PSP load asd failed!\n");
2543 0 : goto failed1;
2544 : }
2545 :
2546 0 : ret = psp_rl_load(adev);
2547 0 : if (ret) {
2548 0 : DRM_ERROR("PSP load RL failed!\n");
2549 0 : goto failed1;
2550 : }
2551 :
2552 0 : if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2553 0 : if (adev->gmc.xgmi.num_physical_nodes > 1) {
2554 0 : ret = psp_xgmi_initialize(psp, false, true);
2555 : /* Warning the XGMI seesion initialize failure
2556 : * Instead of stop driver initialization
2557 : */
2558 0 : if (ret)
2559 0 : dev_err(psp->adev->dev,
2560 : "XGMI: Failed to initialize XGMI session\n");
2561 : }
2562 : }
2563 :
2564 0 : if (psp->ta_fw) {
2565 0 : ret = psp_ras_initialize(psp);
2566 0 : if (ret)
2567 0 : dev_err(psp->adev->dev,
2568 : "RAS: Failed to initialize RAS\n");
2569 :
2570 0 : ret = psp_hdcp_initialize(psp);
2571 0 : if (ret)
2572 0 : dev_err(psp->adev->dev,
2573 : "HDCP: Failed to initialize HDCP\n");
2574 :
2575 0 : ret = psp_dtm_initialize(psp);
2576 0 : if (ret)
2577 0 : dev_err(psp->adev->dev,
2578 : "DTM: Failed to initialize DTM\n");
2579 :
2580 0 : ret = psp_rap_initialize(psp);
2581 0 : if (ret)
2582 0 : dev_err(psp->adev->dev,
2583 : "RAP: Failed to initialize RAP\n");
2584 :
2585 0 : ret = psp_securedisplay_initialize(psp);
2586 0 : if (ret)
2587 0 : dev_err(psp->adev->dev,
2588 : "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2589 : }
2590 :
2591 : return 0;
2592 :
2593 : failed1:
2594 0 : psp_free_shared_bufs(psp);
2595 : failed:
2596 : /*
2597 : * all cleanup jobs (xgmi terminate, ras terminate,
2598 : * ring destroy, cmd/fence/fw buffers destory,
2599 : * psp->cmd destory) are delayed to psp_hw_fini
2600 : */
2601 0 : psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2602 0 : return ret;
2603 : }
2604 :
2605 0 : static int psp_hw_init(void *handle)
2606 : {
2607 : int ret;
2608 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2609 :
2610 0 : mutex_lock(&adev->firmware.mutex);
2611 : /*
2612 : * This sequence is just used on hw_init only once, no need on
2613 : * resume.
2614 : */
2615 0 : ret = amdgpu_ucode_init_bo(adev);
2616 0 : if (ret)
2617 : goto failed;
2618 :
2619 0 : ret = psp_load_fw(adev);
2620 0 : if (ret) {
2621 0 : DRM_ERROR("PSP firmware loading failed\n");
2622 0 : goto failed;
2623 : }
2624 :
2625 0 : mutex_unlock(&adev->firmware.mutex);
2626 0 : return 0;
2627 :
2628 : failed:
2629 0 : adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2630 0 : mutex_unlock(&adev->firmware.mutex);
2631 0 : return -EINVAL;
2632 : }
2633 :
2634 0 : static int psp_hw_fini(void *handle)
2635 : {
2636 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2637 0 : struct psp_context *psp = &adev->psp;
2638 :
2639 0 : if (psp->ta_fw) {
2640 0 : psp_ras_terminate(psp);
2641 0 : psp_securedisplay_terminate(psp);
2642 0 : psp_rap_terminate(psp);
2643 0 : psp_dtm_terminate(psp);
2644 0 : psp_hdcp_terminate(psp);
2645 :
2646 0 : if (adev->gmc.xgmi.num_physical_nodes > 1)
2647 0 : psp_xgmi_terminate(psp);
2648 : }
2649 :
2650 0 : psp_asd_terminate(psp);
2651 0 : psp_tmr_terminate(psp);
2652 :
2653 0 : psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2654 :
2655 0 : psp_free_shared_bufs(psp);
2656 :
2657 0 : return 0;
2658 : }
2659 :
2660 0 : static int psp_suspend(void *handle)
2661 : {
2662 0 : int ret = 0;
2663 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2664 0 : struct psp_context *psp = &adev->psp;
2665 :
2666 0 : if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2667 0 : psp->xgmi_context.context.initialized) {
2668 0 : ret = psp_xgmi_terminate(psp);
2669 0 : if (ret) {
2670 0 : DRM_ERROR("Failed to terminate xgmi ta\n");
2671 0 : goto out;
2672 : }
2673 : }
2674 :
2675 0 : if (psp->ta_fw) {
2676 0 : ret = psp_ras_terminate(psp);
2677 0 : if (ret) {
2678 0 : DRM_ERROR("Failed to terminate ras ta\n");
2679 0 : goto out;
2680 : }
2681 0 : ret = psp_hdcp_terminate(psp);
2682 0 : if (ret) {
2683 0 : DRM_ERROR("Failed to terminate hdcp ta\n");
2684 0 : goto out;
2685 : }
2686 0 : ret = psp_dtm_terminate(psp);
2687 0 : if (ret) {
2688 0 : DRM_ERROR("Failed to terminate dtm ta\n");
2689 0 : goto out;
2690 : }
2691 0 : ret = psp_rap_terminate(psp);
2692 0 : if (ret) {
2693 0 : DRM_ERROR("Failed to terminate rap ta\n");
2694 0 : goto out;
2695 : }
2696 0 : ret = psp_securedisplay_terminate(psp);
2697 0 : if (ret) {
2698 0 : DRM_ERROR("Failed to terminate securedisplay ta\n");
2699 0 : goto out;
2700 : }
2701 : }
2702 :
2703 0 : ret = psp_asd_terminate(psp);
2704 0 : if (ret) {
2705 0 : DRM_ERROR("Failed to terminate asd\n");
2706 0 : goto out;
2707 : }
2708 :
2709 0 : ret = psp_tmr_terminate(psp);
2710 0 : if (ret) {
2711 0 : DRM_ERROR("Failed to terminate tmr\n");
2712 0 : goto out;
2713 : }
2714 :
2715 0 : ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2716 0 : if (ret) {
2717 0 : DRM_ERROR("PSP ring stop failed\n");
2718 : }
2719 :
2720 : out:
2721 0 : psp_free_shared_bufs(psp);
2722 :
2723 0 : return ret;
2724 : }
2725 :
2726 0 : static int psp_resume(void *handle)
2727 : {
2728 : int ret;
2729 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2730 0 : struct psp_context *psp = &adev->psp;
2731 :
2732 0 : DRM_INFO("PSP is resuming...\n");
2733 :
2734 0 : if (psp->mem_train_ctx.enable_mem_training) {
2735 0 : ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2736 0 : if (ret) {
2737 0 : DRM_ERROR("Failed to process memory training!\n");
2738 0 : return ret;
2739 : }
2740 : }
2741 :
2742 0 : mutex_lock(&adev->firmware.mutex);
2743 :
2744 0 : ret = psp_hw_start(psp);
2745 0 : if (ret)
2746 : goto failed;
2747 :
2748 0 : ret = psp_load_non_psp_fw(psp);
2749 0 : if (ret)
2750 : goto failed;
2751 :
2752 0 : ret = psp_asd_initialize(psp);
2753 0 : if (ret) {
2754 0 : DRM_ERROR("PSP load asd failed!\n");
2755 0 : goto failed;
2756 : }
2757 :
2758 0 : ret = psp_rl_load(adev);
2759 0 : if (ret) {
2760 0 : dev_err(adev->dev, "PSP load RL failed!\n");
2761 0 : goto failed;
2762 : }
2763 :
2764 0 : if (adev->gmc.xgmi.num_physical_nodes > 1) {
2765 0 : ret = psp_xgmi_initialize(psp, false, true);
2766 : /* Warning the XGMI seesion initialize failure
2767 : * Instead of stop driver initialization
2768 : */
2769 0 : if (ret)
2770 0 : dev_err(psp->adev->dev,
2771 : "XGMI: Failed to initialize XGMI session\n");
2772 : }
2773 :
2774 0 : if (psp->ta_fw) {
2775 0 : ret = psp_ras_initialize(psp);
2776 0 : if (ret)
2777 0 : dev_err(psp->adev->dev,
2778 : "RAS: Failed to initialize RAS\n");
2779 :
2780 0 : ret = psp_hdcp_initialize(psp);
2781 0 : if (ret)
2782 0 : dev_err(psp->adev->dev,
2783 : "HDCP: Failed to initialize HDCP\n");
2784 :
2785 0 : ret = psp_dtm_initialize(psp);
2786 0 : if (ret)
2787 0 : dev_err(psp->adev->dev,
2788 : "DTM: Failed to initialize DTM\n");
2789 :
2790 0 : ret = psp_rap_initialize(psp);
2791 0 : if (ret)
2792 0 : dev_err(psp->adev->dev,
2793 : "RAP: Failed to initialize RAP\n");
2794 :
2795 0 : ret = psp_securedisplay_initialize(psp);
2796 0 : if (ret)
2797 0 : dev_err(psp->adev->dev,
2798 : "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2799 : }
2800 :
2801 0 : mutex_unlock(&adev->firmware.mutex);
2802 :
2803 0 : return 0;
2804 :
2805 : failed:
2806 0 : DRM_ERROR("PSP resume failed\n");
2807 0 : mutex_unlock(&adev->firmware.mutex);
2808 0 : return ret;
2809 : }
2810 :
2811 0 : int psp_gpu_reset(struct amdgpu_device *adev)
2812 : {
2813 : int ret;
2814 :
2815 0 : if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2816 : return 0;
2817 :
2818 0 : mutex_lock(&adev->psp.mutex);
2819 0 : ret = psp_mode1_reset(&adev->psp);
2820 0 : mutex_unlock(&adev->psp.mutex);
2821 :
2822 0 : return ret;
2823 : }
2824 :
2825 0 : int psp_rlc_autoload_start(struct psp_context *psp)
2826 : {
2827 : int ret;
2828 0 : struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2829 :
2830 0 : cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2831 :
2832 0 : ret = psp_cmd_submit_buf(psp, NULL, cmd,
2833 : psp->fence_buf_mc_addr);
2834 :
2835 0 : release_psp_cmd_buf(psp);
2836 :
2837 0 : return ret;
2838 : }
2839 :
2840 0 : int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2841 : uint64_t cmd_gpu_addr, int cmd_size)
2842 : {
2843 0 : struct amdgpu_firmware_info ucode = {0};
2844 :
2845 0 : ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2846 : AMDGPU_UCODE_ID_VCN0_RAM;
2847 0 : ucode.mc_addr = cmd_gpu_addr;
2848 0 : ucode.ucode_size = cmd_size;
2849 :
2850 0 : return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2851 : }
2852 :
2853 0 : int psp_ring_cmd_submit(struct psp_context *psp,
2854 : uint64_t cmd_buf_mc_addr,
2855 : uint64_t fence_mc_addr,
2856 : int index)
2857 : {
2858 0 : unsigned int psp_write_ptr_reg = 0;
2859 : struct psp_gfx_rb_frame *write_frame;
2860 0 : struct psp_ring *ring = &psp->km_ring;
2861 0 : struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2862 0 : struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2863 0 : ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2864 0 : struct amdgpu_device *adev = psp->adev;
2865 0 : uint32_t ring_size_dw = ring->ring_size / 4;
2866 0 : uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2867 :
2868 : /* KM (GPCOM) prepare write pointer */
2869 0 : psp_write_ptr_reg = psp_ring_get_wptr(psp);
2870 :
2871 : /* Update KM RB frame pointer to new frame */
2872 : /* write_frame ptr increments by size of rb_frame in bytes */
2873 : /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2874 0 : if ((psp_write_ptr_reg % ring_size_dw) == 0)
2875 : write_frame = ring_buffer_start;
2876 : else
2877 0 : write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2878 : /* Check invalid write_frame ptr address */
2879 0 : if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2880 0 : DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2881 : ring_buffer_start, ring_buffer_end, write_frame);
2882 0 : DRM_ERROR("write_frame is pointing to address out of bounds\n");
2883 0 : return -EINVAL;
2884 : }
2885 :
2886 : /* Initialize KM RB frame */
2887 0 : memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2888 :
2889 : /* Update KM RB frame */
2890 0 : write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2891 0 : write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2892 0 : write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2893 0 : write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2894 0 : write_frame->fence_value = index;
2895 0 : amdgpu_device_flush_hdp(adev, NULL);
2896 :
2897 : /* Update the write Pointer in DWORDs */
2898 0 : psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2899 0 : psp_ring_set_wptr(psp, psp_write_ptr_reg);
2900 0 : return 0;
2901 : }
2902 :
2903 0 : int psp_init_asd_microcode(struct psp_context *psp,
2904 : const char *chip_name)
2905 : {
2906 0 : struct amdgpu_device *adev = psp->adev;
2907 : char fw_name[PSP_FW_NAME_LEN];
2908 : const struct psp_firmware_header_v1_0 *asd_hdr;
2909 0 : int err = 0;
2910 :
2911 0 : if (!chip_name) {
2912 0 : dev_err(adev->dev, "invalid chip name for asd microcode\n");
2913 0 : return -EINVAL;
2914 : }
2915 :
2916 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2917 0 : err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2918 0 : if (err)
2919 : goto out;
2920 :
2921 0 : err = amdgpu_ucode_validate(adev->psp.asd_fw);
2922 0 : if (err)
2923 : goto out;
2924 :
2925 0 : asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2926 0 : adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2927 0 : adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2928 0 : adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2929 0 : adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2930 0 : le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2931 0 : return 0;
2932 : out:
2933 0 : dev_err(adev->dev, "fail to initialize asd microcode\n");
2934 0 : release_firmware(adev->psp.asd_fw);
2935 0 : adev->psp.asd_fw = NULL;
2936 0 : return err;
2937 : }
2938 :
2939 0 : int psp_init_toc_microcode(struct psp_context *psp,
2940 : const char *chip_name)
2941 : {
2942 0 : struct amdgpu_device *adev = psp->adev;
2943 : char fw_name[PSP_FW_NAME_LEN];
2944 : const struct psp_firmware_header_v1_0 *toc_hdr;
2945 0 : int err = 0;
2946 :
2947 0 : if (!chip_name) {
2948 0 : dev_err(adev->dev, "invalid chip name for toc microcode\n");
2949 0 : return -EINVAL;
2950 : }
2951 :
2952 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2953 0 : err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2954 0 : if (err)
2955 : goto out;
2956 :
2957 0 : err = amdgpu_ucode_validate(adev->psp.toc_fw);
2958 0 : if (err)
2959 : goto out;
2960 :
2961 0 : toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2962 0 : adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2963 0 : adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2964 0 : adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2965 0 : adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2966 0 : le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2967 0 : return 0;
2968 : out:
2969 0 : dev_err(adev->dev, "fail to request/validate toc microcode\n");
2970 0 : release_firmware(adev->psp.toc_fw);
2971 0 : adev->psp.toc_fw = NULL;
2972 0 : return err;
2973 : }
2974 :
2975 0 : static int parse_sos_bin_descriptor(struct psp_context *psp,
2976 : const struct psp_fw_bin_desc *desc,
2977 : const struct psp_firmware_header_v2_0 *sos_hdr)
2978 : {
2979 0 : uint8_t *ucode_start_addr = NULL;
2980 :
2981 0 : if (!psp || !desc || !sos_hdr)
2982 : return -EINVAL;
2983 :
2984 0 : ucode_start_addr = (uint8_t *)sos_hdr +
2985 0 : le32_to_cpu(desc->offset_bytes) +
2986 0 : le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2987 :
2988 0 : switch (desc->fw_type) {
2989 : case PSP_FW_TYPE_PSP_SOS:
2990 0 : psp->sos.fw_version = le32_to_cpu(desc->fw_version);
2991 0 : psp->sos.feature_version = le32_to_cpu(desc->fw_version);
2992 0 : psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
2993 0 : psp->sos.start_addr = ucode_start_addr;
2994 0 : break;
2995 : case PSP_FW_TYPE_PSP_SYS_DRV:
2996 0 : psp->sys.fw_version = le32_to_cpu(desc->fw_version);
2997 0 : psp->sys.feature_version = le32_to_cpu(desc->fw_version);
2998 0 : psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
2999 0 : psp->sys.start_addr = ucode_start_addr;
3000 0 : break;
3001 : case PSP_FW_TYPE_PSP_KDB:
3002 0 : psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3003 0 : psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3004 0 : psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3005 0 : psp->kdb.start_addr = ucode_start_addr;
3006 0 : break;
3007 : case PSP_FW_TYPE_PSP_TOC:
3008 0 : psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3009 0 : psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3010 0 : psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3011 0 : psp->toc.start_addr = ucode_start_addr;
3012 0 : break;
3013 : case PSP_FW_TYPE_PSP_SPL:
3014 0 : psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3015 0 : psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3016 0 : psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3017 0 : psp->spl.start_addr = ucode_start_addr;
3018 0 : break;
3019 : case PSP_FW_TYPE_PSP_RL:
3020 0 : psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3021 0 : psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3022 0 : psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3023 0 : psp->rl.start_addr = ucode_start_addr;
3024 0 : break;
3025 : case PSP_FW_TYPE_PSP_SOC_DRV:
3026 0 : psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3027 0 : psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3028 0 : psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3029 0 : psp->soc_drv.start_addr = ucode_start_addr;
3030 0 : break;
3031 : case PSP_FW_TYPE_PSP_INTF_DRV:
3032 0 : psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3033 0 : psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3034 0 : psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3035 0 : psp->intf_drv.start_addr = ucode_start_addr;
3036 0 : break;
3037 : case PSP_FW_TYPE_PSP_DBG_DRV:
3038 0 : psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3039 0 : psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3040 0 : psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3041 0 : psp->dbg_drv.start_addr = ucode_start_addr;
3042 0 : break;
3043 : default:
3044 0 : dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3045 0 : break;
3046 : }
3047 :
3048 : return 0;
3049 : }
3050 :
3051 0 : static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3052 : {
3053 : const struct psp_firmware_header_v1_0 *sos_hdr;
3054 : const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3055 : uint8_t *ucode_array_start_addr;
3056 :
3057 0 : sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3058 0 : ucode_array_start_addr = (uint8_t *)sos_hdr +
3059 0 : le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3060 :
3061 0 : if (adev->gmc.xgmi.connected_to_cpu ||
3062 0 : (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3063 0 : adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3064 0 : adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3065 :
3066 0 : adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3067 0 : adev->psp.sys.start_addr = ucode_array_start_addr;
3068 :
3069 0 : adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3070 0 : adev->psp.sos.start_addr = ucode_array_start_addr +
3071 0 : le32_to_cpu(sos_hdr->sos.offset_bytes);
3072 : } else {
3073 : /* Load alternate PSP SOS FW */
3074 0 : sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3075 :
3076 0 : adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3077 0 : adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3078 :
3079 0 : adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3080 0 : adev->psp.sys.start_addr = ucode_array_start_addr +
3081 0 : le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3082 :
3083 0 : adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3084 0 : adev->psp.sos.start_addr = ucode_array_start_addr +
3085 0 : le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3086 : }
3087 :
3088 0 : if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3089 0 : dev_warn(adev->dev, "PSP SOS FW not available");
3090 0 : return -EINVAL;
3091 : }
3092 :
3093 : return 0;
3094 : }
3095 :
3096 0 : int psp_init_sos_microcode(struct psp_context *psp,
3097 : const char *chip_name)
3098 : {
3099 0 : struct amdgpu_device *adev = psp->adev;
3100 : char fw_name[PSP_FW_NAME_LEN];
3101 : const struct psp_firmware_header_v1_0 *sos_hdr;
3102 : const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3103 : const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3104 : const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3105 : const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3106 0 : int err = 0;
3107 : uint8_t *ucode_array_start_addr;
3108 0 : int fw_index = 0;
3109 :
3110 0 : if (!chip_name) {
3111 0 : dev_err(adev->dev, "invalid chip name for sos microcode\n");
3112 0 : return -EINVAL;
3113 : }
3114 :
3115 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3116 0 : err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3117 0 : if (err)
3118 : goto out;
3119 :
3120 0 : err = amdgpu_ucode_validate(adev->psp.sos_fw);
3121 0 : if (err)
3122 : goto out;
3123 :
3124 0 : sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3125 0 : ucode_array_start_addr = (uint8_t *)sos_hdr +
3126 0 : le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3127 0 : amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3128 :
3129 0 : switch (sos_hdr->header.header_version_major) {
3130 : case 1:
3131 0 : err = psp_init_sos_base_fw(adev);
3132 0 : if (err)
3133 : goto out;
3134 :
3135 0 : if (sos_hdr->header.header_version_minor == 1) {
3136 0 : sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3137 0 : adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3138 0 : adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3139 0 : le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3140 0 : adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3141 0 : adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3142 0 : le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3143 : }
3144 0 : if (sos_hdr->header.header_version_minor == 2) {
3145 0 : sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3146 0 : adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3147 0 : adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3148 0 : le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3149 : }
3150 0 : if (sos_hdr->header.header_version_minor == 3) {
3151 0 : sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3152 0 : adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3153 0 : adev->psp.toc.start_addr = ucode_array_start_addr +
3154 0 : le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3155 0 : adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3156 0 : adev->psp.kdb.start_addr = ucode_array_start_addr +
3157 0 : le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3158 0 : adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3159 0 : adev->psp.spl.start_addr = ucode_array_start_addr +
3160 0 : le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3161 0 : adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3162 0 : adev->psp.rl.start_addr = ucode_array_start_addr +
3163 0 : le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3164 : }
3165 : break;
3166 : case 2:
3167 0 : sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3168 :
3169 0 : if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3170 0 : dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3171 0 : err = -EINVAL;
3172 0 : goto out;
3173 : }
3174 :
3175 0 : for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3176 0 : err = parse_sos_bin_descriptor(psp,
3177 : &sos_hdr_v2_0->psp_fw_bin[fw_index],
3178 : sos_hdr_v2_0);
3179 0 : if (err)
3180 : goto out;
3181 : }
3182 : break;
3183 : default:
3184 0 : dev_err(adev->dev,
3185 : "unsupported psp sos firmware\n");
3186 0 : err = -EINVAL;
3187 0 : goto out;
3188 : }
3189 :
3190 : return 0;
3191 : out:
3192 0 : dev_err(adev->dev,
3193 : "failed to init sos firmware\n");
3194 0 : release_firmware(adev->psp.sos_fw);
3195 0 : adev->psp.sos_fw = NULL;
3196 :
3197 0 : return err;
3198 : }
3199 :
3200 0 : static int parse_ta_bin_descriptor(struct psp_context *psp,
3201 : const struct psp_fw_bin_desc *desc,
3202 : const struct ta_firmware_header_v2_0 *ta_hdr)
3203 : {
3204 0 : uint8_t *ucode_start_addr = NULL;
3205 :
3206 0 : if (!psp || !desc || !ta_hdr)
3207 : return -EINVAL;
3208 :
3209 0 : ucode_start_addr = (uint8_t *)ta_hdr +
3210 0 : le32_to_cpu(desc->offset_bytes) +
3211 0 : le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3212 :
3213 0 : switch (desc->fw_type) {
3214 : case TA_FW_TYPE_PSP_ASD:
3215 0 : psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3216 0 : psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3217 0 : psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3218 0 : psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3219 0 : break;
3220 : case TA_FW_TYPE_PSP_XGMI:
3221 0 : psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3222 0 : psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3223 0 : psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3224 0 : break;
3225 : case TA_FW_TYPE_PSP_RAS:
3226 0 : psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3227 0 : psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3228 0 : psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3229 0 : break;
3230 : case TA_FW_TYPE_PSP_HDCP:
3231 0 : psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3232 0 : psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3233 0 : psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3234 0 : break;
3235 : case TA_FW_TYPE_PSP_DTM:
3236 0 : psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3237 0 : psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3238 0 : psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3239 0 : break;
3240 : case TA_FW_TYPE_PSP_RAP:
3241 0 : psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3242 0 : psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3243 0 : psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3244 0 : break;
3245 : case TA_FW_TYPE_PSP_SECUREDISPLAY:
3246 0 : psp->securedisplay_context.context.bin_desc.fw_version =
3247 0 : le32_to_cpu(desc->fw_version);
3248 0 : psp->securedisplay_context.context.bin_desc.size_bytes =
3249 0 : le32_to_cpu(desc->size_bytes);
3250 0 : psp->securedisplay_context.context.bin_desc.start_addr =
3251 : ucode_start_addr;
3252 0 : break;
3253 : default:
3254 0 : dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3255 0 : break;
3256 : }
3257 :
3258 : return 0;
3259 : }
3260 :
3261 0 : int psp_init_ta_microcode(struct psp_context *psp,
3262 : const char *chip_name)
3263 : {
3264 0 : struct amdgpu_device *adev = psp->adev;
3265 : char fw_name[PSP_FW_NAME_LEN];
3266 : const struct ta_firmware_header_v2_0 *ta_hdr;
3267 0 : int err = 0;
3268 0 : int ta_index = 0;
3269 :
3270 0 : if (!chip_name) {
3271 0 : dev_err(adev->dev, "invalid chip name for ta microcode\n");
3272 0 : return -EINVAL;
3273 : }
3274 :
3275 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3276 0 : err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3277 0 : if (err)
3278 : goto out;
3279 :
3280 0 : err = amdgpu_ucode_validate(adev->psp.ta_fw);
3281 0 : if (err)
3282 : goto out;
3283 :
3284 0 : ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3285 :
3286 0 : if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3287 0 : dev_err(adev->dev, "unsupported TA header version\n");
3288 0 : err = -EINVAL;
3289 0 : goto out;
3290 : }
3291 :
3292 0 : if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3293 0 : dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3294 0 : err = -EINVAL;
3295 0 : goto out;
3296 : }
3297 :
3298 0 : for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3299 0 : err = parse_ta_bin_descriptor(psp,
3300 : &ta_hdr->ta_fw_bin[ta_index],
3301 : ta_hdr);
3302 0 : if (err)
3303 : goto out;
3304 : }
3305 :
3306 : return 0;
3307 : out:
3308 0 : dev_err(adev->dev, "fail to initialize ta microcode\n");
3309 0 : release_firmware(adev->psp.ta_fw);
3310 0 : adev->psp.ta_fw = NULL;
3311 0 : return err;
3312 : }
3313 :
3314 0 : int psp_init_cap_microcode(struct psp_context *psp,
3315 : const char *chip_name)
3316 : {
3317 0 : struct amdgpu_device *adev = psp->adev;
3318 : char fw_name[PSP_FW_NAME_LEN];
3319 : const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3320 0 : struct amdgpu_firmware_info *info = NULL;
3321 0 : int err = 0;
3322 :
3323 0 : if (!chip_name) {
3324 0 : dev_err(adev->dev, "invalid chip name for cap microcode\n");
3325 0 : return -EINVAL;
3326 : }
3327 :
3328 0 : if (!amdgpu_sriov_vf(adev)) {
3329 0 : dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3330 0 : return -EINVAL;
3331 : }
3332 :
3333 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3334 0 : err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3335 0 : if (err) {
3336 0 : dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3337 0 : err = 0;
3338 0 : goto out;
3339 : }
3340 :
3341 0 : err = amdgpu_ucode_validate(adev->psp.cap_fw);
3342 0 : if (err) {
3343 0 : dev_err(adev->dev, "fail to initialize cap microcode\n");
3344 0 : goto out;
3345 : }
3346 :
3347 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3348 0 : info->ucode_id = AMDGPU_UCODE_ID_CAP;
3349 0 : info->fw = adev->psp.cap_fw;
3350 0 : cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3351 : adev->psp.cap_fw->data;
3352 0 : adev->firmware.fw_size += ALIGN(
3353 : le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3354 0 : adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3355 0 : adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3356 0 : adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3357 :
3358 0 : return 0;
3359 :
3360 : out:
3361 0 : release_firmware(adev->psp.cap_fw);
3362 0 : adev->psp.cap_fw = NULL;
3363 0 : return err;
3364 : }
3365 :
3366 0 : static int psp_set_clockgating_state(void *handle,
3367 : enum amd_clockgating_state state)
3368 : {
3369 0 : return 0;
3370 : }
3371 :
3372 0 : static int psp_set_powergating_state(void *handle,
3373 : enum amd_powergating_state state)
3374 : {
3375 0 : return 0;
3376 : }
3377 :
3378 0 : static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3379 : struct device_attribute *attr,
3380 : char *buf)
3381 : {
3382 0 : struct drm_device *ddev = dev_get_drvdata(dev);
3383 0 : struct amdgpu_device *adev = drm_to_adev(ddev);
3384 : uint32_t fw_ver;
3385 : int ret;
3386 :
3387 0 : if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3388 0 : DRM_INFO("PSP block is not ready yet.");
3389 0 : return -EBUSY;
3390 : }
3391 :
3392 0 : mutex_lock(&adev->psp.mutex);
3393 0 : ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3394 0 : mutex_unlock(&adev->psp.mutex);
3395 :
3396 0 : if (ret) {
3397 0 : DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3398 0 : return ret;
3399 : }
3400 :
3401 0 : return sysfs_emit(buf, "%x\n", fw_ver);
3402 : }
3403 :
3404 0 : static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3405 : struct device_attribute *attr,
3406 : const char *buf,
3407 : size_t count)
3408 : {
3409 0 : struct drm_device *ddev = dev_get_drvdata(dev);
3410 0 : struct amdgpu_device *adev = drm_to_adev(ddev);
3411 : int ret, idx;
3412 : char fw_name[100];
3413 : const struct firmware *usbc_pd_fw;
3414 0 : struct amdgpu_bo *fw_buf_bo = NULL;
3415 : uint64_t fw_pri_mc_addr;
3416 : void *fw_pri_cpu_addr;
3417 :
3418 0 : if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3419 0 : DRM_INFO("PSP block is not ready yet.");
3420 0 : return -EBUSY;
3421 : }
3422 :
3423 0 : if (!drm_dev_enter(ddev, &idx))
3424 : return -ENODEV;
3425 :
3426 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3427 0 : ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3428 0 : if (ret)
3429 : goto fail;
3430 :
3431 : /* LFB address which is aligned to 1MB boundary per PSP request */
3432 0 : ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3433 : AMDGPU_GEM_DOMAIN_VRAM,
3434 : &fw_buf_bo,
3435 : &fw_pri_mc_addr,
3436 : &fw_pri_cpu_addr);
3437 0 : if (ret)
3438 : goto rel_buf;
3439 :
3440 0 : memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3441 :
3442 0 : mutex_lock(&adev->psp.mutex);
3443 0 : ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3444 0 : mutex_unlock(&adev->psp.mutex);
3445 :
3446 0 : amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3447 :
3448 : rel_buf:
3449 0 : release_firmware(usbc_pd_fw);
3450 : fail:
3451 0 : if (ret) {
3452 0 : DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3453 0 : count = ret;
3454 : }
3455 :
3456 0 : drm_dev_exit(idx);
3457 0 : return count;
3458 : }
3459 :
3460 0 : void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3461 : {
3462 : int idx;
3463 :
3464 0 : if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3465 0 : return;
3466 :
3467 0 : memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3468 0 : memcpy(psp->fw_pri_buf, start_addr, bin_size);
3469 :
3470 0 : drm_dev_exit(idx);
3471 : }
3472 :
3473 : static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3474 : psp_usbc_pd_fw_sysfs_read,
3475 : psp_usbc_pd_fw_sysfs_write);
3476 :
3477 0 : int is_psp_fw_valid(struct psp_bin_desc bin)
3478 : {
3479 0 : return bin.size_bytes;
3480 : }
3481 :
3482 0 : static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3483 : struct bin_attribute *bin_attr,
3484 : char *buffer, loff_t pos, size_t count)
3485 : {
3486 0 : struct device *dev = kobj_to_dev(kobj);
3487 0 : struct drm_device *ddev = dev_get_drvdata(dev);
3488 0 : struct amdgpu_device *adev = drm_to_adev(ddev);
3489 :
3490 0 : adev->psp.vbflash_done = false;
3491 :
3492 : /* Safeguard against memory drain */
3493 0 : if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3494 0 : dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3495 0 : kvfree(adev->psp.vbflash_tmp_buf);
3496 0 : adev->psp.vbflash_tmp_buf = NULL;
3497 0 : adev->psp.vbflash_image_size = 0;
3498 0 : return -ENOMEM;
3499 : }
3500 :
3501 : /* TODO Just allocate max for now and optimize to realloc later if needed */
3502 0 : if (!adev->psp.vbflash_tmp_buf) {
3503 0 : adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3504 0 : if (!adev->psp.vbflash_tmp_buf)
3505 : return -ENOMEM;
3506 : }
3507 :
3508 0 : mutex_lock(&adev->psp.mutex);
3509 0 : memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3510 0 : adev->psp.vbflash_image_size += count;
3511 0 : mutex_unlock(&adev->psp.mutex);
3512 :
3513 0 : dev_info(adev->dev, "VBIOS flash write PSP done");
3514 :
3515 0 : return count;
3516 : }
3517 :
3518 0 : static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3519 : struct bin_attribute *bin_attr, char *buffer,
3520 : loff_t pos, size_t count)
3521 : {
3522 0 : struct device *dev = kobj_to_dev(kobj);
3523 0 : struct drm_device *ddev = dev_get_drvdata(dev);
3524 0 : struct amdgpu_device *adev = drm_to_adev(ddev);
3525 0 : struct amdgpu_bo *fw_buf_bo = NULL;
3526 : uint64_t fw_pri_mc_addr;
3527 : void *fw_pri_cpu_addr;
3528 : int ret;
3529 :
3530 0 : dev_info(adev->dev, "VBIOS flash to PSP started");
3531 :
3532 0 : ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3533 : AMDGPU_GPU_PAGE_SIZE,
3534 : AMDGPU_GEM_DOMAIN_VRAM,
3535 : &fw_buf_bo,
3536 : &fw_pri_mc_addr,
3537 : &fw_pri_cpu_addr);
3538 0 : if (ret)
3539 : goto rel_buf;
3540 :
3541 0 : memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3542 :
3543 0 : mutex_lock(&adev->psp.mutex);
3544 0 : ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3545 0 : mutex_unlock(&adev->psp.mutex);
3546 :
3547 0 : amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3548 :
3549 : rel_buf:
3550 0 : kvfree(adev->psp.vbflash_tmp_buf);
3551 0 : adev->psp.vbflash_tmp_buf = NULL;
3552 0 : adev->psp.vbflash_image_size = 0;
3553 :
3554 0 : if (ret) {
3555 0 : dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3556 0 : return ret;
3557 : }
3558 :
3559 0 : dev_info(adev->dev, "VBIOS flash to PSP done");
3560 0 : return 0;
3561 : }
3562 :
3563 0 : static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3564 : struct device_attribute *attr,
3565 : char *buf)
3566 : {
3567 0 : struct drm_device *ddev = dev_get_drvdata(dev);
3568 0 : struct amdgpu_device *adev = drm_to_adev(ddev);
3569 : uint32_t vbflash_status;
3570 :
3571 0 : vbflash_status = psp_vbflash_status(&adev->psp);
3572 0 : if (!adev->psp.vbflash_done)
3573 : vbflash_status = 0;
3574 0 : else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3575 0 : vbflash_status = 1;
3576 :
3577 0 : return sysfs_emit(buf, "0x%x\n", vbflash_status);
3578 : }
3579 :
3580 : static const struct bin_attribute psp_vbflash_bin_attr = {
3581 : .attr = {.name = "psp_vbflash", .mode = 0664},
3582 : .size = 0,
3583 : .write = amdgpu_psp_vbflash_write,
3584 : .read = amdgpu_psp_vbflash_read,
3585 : };
3586 :
3587 : static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3588 :
3589 0 : int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3590 : {
3591 0 : int ret = 0;
3592 0 : struct psp_context *psp = &adev->psp;
3593 :
3594 0 : if (amdgpu_sriov_vf(adev))
3595 : return -EINVAL;
3596 :
3597 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
3598 : case IP_VERSION(13, 0, 0):
3599 : case IP_VERSION(13, 0, 7):
3600 0 : if (!psp->adev) {
3601 0 : psp->adev = adev;
3602 0 : psp_v13_0_set_psp_funcs(psp);
3603 : }
3604 0 : ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3605 0 : if (ret)
3606 0 : dev_err(adev->dev, "Failed to create device file psp_vbflash");
3607 0 : ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3608 0 : if (ret)
3609 0 : dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3610 : return ret;
3611 : default:
3612 : return 0;
3613 : }
3614 : }
3615 :
3616 : const struct amd_ip_funcs psp_ip_funcs = {
3617 : .name = "psp",
3618 : .early_init = psp_early_init,
3619 : .late_init = NULL,
3620 : .sw_init = psp_sw_init,
3621 : .sw_fini = psp_sw_fini,
3622 : .hw_init = psp_hw_init,
3623 : .hw_fini = psp_hw_fini,
3624 : .suspend = psp_suspend,
3625 : .resume = psp_resume,
3626 : .is_idle = NULL,
3627 : .check_soft_reset = NULL,
3628 : .wait_for_idle = NULL,
3629 : .soft_reset = NULL,
3630 : .set_clockgating_state = psp_set_clockgating_state,
3631 : .set_powergating_state = psp_set_powergating_state,
3632 : };
3633 :
3634 0 : static int psp_sysfs_init(struct amdgpu_device *adev)
3635 : {
3636 0 : int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3637 :
3638 0 : if (ret)
3639 0 : DRM_ERROR("Failed to create USBC PD FW control file!");
3640 :
3641 0 : return ret;
3642 : }
3643 :
3644 0 : void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3645 : {
3646 0 : sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3647 0 : device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3648 0 : }
3649 :
3650 : static void psp_sysfs_fini(struct amdgpu_device *adev)
3651 : {
3652 0 : device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3653 : }
3654 :
3655 : const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3656 : {
3657 : .type = AMD_IP_BLOCK_TYPE_PSP,
3658 : .major = 3,
3659 : .minor = 1,
3660 : .rev = 0,
3661 : .funcs = &psp_ip_funcs,
3662 : };
3663 :
3664 : const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3665 : {
3666 : .type = AMD_IP_BLOCK_TYPE_PSP,
3667 : .major = 10,
3668 : .minor = 0,
3669 : .rev = 0,
3670 : .funcs = &psp_ip_funcs,
3671 : };
3672 :
3673 : const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3674 : {
3675 : .type = AMD_IP_BLOCK_TYPE_PSP,
3676 : .major = 11,
3677 : .minor = 0,
3678 : .rev = 0,
3679 : .funcs = &psp_ip_funcs,
3680 : };
3681 :
3682 : const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3683 : .type = AMD_IP_BLOCK_TYPE_PSP,
3684 : .major = 11,
3685 : .minor = 0,
3686 : .rev = 8,
3687 : .funcs = &psp_ip_funcs,
3688 : };
3689 :
3690 : const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3691 : {
3692 : .type = AMD_IP_BLOCK_TYPE_PSP,
3693 : .major = 12,
3694 : .minor = 0,
3695 : .rev = 0,
3696 : .funcs = &psp_ip_funcs,
3697 : };
3698 :
3699 : const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3700 : .type = AMD_IP_BLOCK_TYPE_PSP,
3701 : .major = 13,
3702 : .minor = 0,
3703 : .rev = 0,
3704 : .funcs = &psp_ip_funcs,
3705 : };
3706 :
3707 : const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3708 : .type = AMD_IP_BLOCK_TYPE_PSP,
3709 : .major = 13,
3710 : .minor = 0,
3711 : .rev = 4,
3712 : .funcs = &psp_ip_funcs,
3713 : };
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