Line data    Source code

       1             : /*
       2             :  * Copyright 2019 Advanced Micro Devices, Inc.
       3             :  *
       4             :  * Permission is hereby granted, free of charge, to any person obtaining a
       5             :  * copy of this software and associated documentation files (the "Software"),
       6             :  * to deal in the Software without restriction, including without limitation
       7             :  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
       8             :  * and/or sell copies of the Software, and to permit persons to whom the
       9             :  * Software is furnished to do so, subject to the following conditions:
      10             :  *
      11             :  * The above copyright notice and this permission notice shall be included in
      12             :  * all copies or substantial portions of the Software.
      13             :  *
      14             :  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
      15             :  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
      16             :  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
      17             :  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
      18             :  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
      19             :  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
      20             :  * OTHER DEALINGS IN THE SOFTWARE.
      21             :  *
      22             :  */
      23             : 
      24             : #include "amdgpu.h"
      25             : #include "athub_v2_0.h"
      26             : 
      27             : #include "athub/athub_2_0_0_offset.h"
      28             : #include "athub/athub_2_0_0_sh_mask.h"
      29             : #include "athub/athub_2_0_0_default.h"
      30             : 
      31             : #include "soc15_common.h"
      32             : 
      33             : static void
      34           0 : athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
      35             :                                             bool enable)
      36             : {
      37             :         uint32_t def, data;
      38             : 
      39           0 :         if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
      40             :                 return;
      41             : 
      42           0 :         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
      43             : 
      44           0 :         if (enable)
      45           0 :                 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
      46             :         else
      47           0 :                 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
      48             : 
      49           0 :         if (def != data)
      50           0 :                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
      51             : }
      52             : 
      53             : static void
      54           0 : athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
      55             :                                            bool enable)
      56             : {
      57             :         uint32_t def, data;
      58             : 
      59           0 :         if (!((adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
      60             :                (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)))
      61             :                 return;
      62             : 
      63           0 :         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
      64             : 
      65           0 :         if (enable)
      66           0 :                 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
      67             :         else
      68           0 :                 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
      69             : 
      70           0 :         if (def != data)
      71           0 :                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
      72             : }
      73             : 
      74           0 : int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
      75             :                                enum amd_clockgating_state state)
      76             : {
      77           0 :         if (amdgpu_sriov_vf(adev))
      78             :                 return 0;
      79             : 
      80           0 :         switch (adev->ip_versions[ATHUB_HWIP][0]) {
      81             :         case IP_VERSION(1, 3, 1):
      82             :         case IP_VERSION(2, 0, 0):
      83             :         case IP_VERSION(2, 0, 2):
      84           0 :                 athub_v2_0_update_medium_grain_clock_gating(adev,
      85             :                                 state == AMD_CG_STATE_GATE);
      86           0 :                 athub_v2_0_update_medium_grain_light_sleep(adev,
      87             :                                 state == AMD_CG_STATE_GATE);
      88           0 :                 break;
      89             :         default:
      90             :                 break;
      91             :         }
      92             : 
      93             :         return 0;
      94             : }
      95             : 
      96           0 : void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
      97             : {
      98             :         int data;
      99             : 
     100             :         /* AMD_CG_SUPPORT_ATHUB_MGCG */
     101           0 :         data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
     102           0 :         if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
     103           0 :                 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
     104             : 
     105             :         /* AMD_CG_SUPPORT_ATHUB_LS */
     106           0 :         if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
     107           0 :                 *flags |= AMD_CG_SUPPORT_ATHUB_LS;
     108           0 : }