Line data Source code
1 : /*
2 : * Copyright 2014 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <drm/drm_fourcc.h>
25 : #include <drm/drm_vblank.h>
26 :
27 : #include "amdgpu.h"
28 : #include "amdgpu_pm.h"
29 : #include "amdgpu_i2c.h"
30 : #include "vid.h"
31 : #include "atom.h"
32 : #include "amdgpu_atombios.h"
33 : #include "atombios_crtc.h"
34 : #include "atombios_encoders.h"
35 : #include "amdgpu_pll.h"
36 : #include "amdgpu_connectors.h"
37 : #include "amdgpu_display.h"
38 : #include "dce_v11_0.h"
39 :
40 : #include "dce/dce_11_0_d.h"
41 : #include "dce/dce_11_0_sh_mask.h"
42 : #include "dce/dce_11_0_enum.h"
43 : #include "oss/oss_3_0_d.h"
44 : #include "oss/oss_3_0_sh_mask.h"
45 : #include "gmc/gmc_8_1_d.h"
46 : #include "gmc/gmc_8_1_sh_mask.h"
47 :
48 : #include "ivsrcid/ivsrcid_vislands30.h"
49 :
50 : static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
51 : static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
52 :
53 : static const u32 crtc_offsets[] =
54 : {
55 : CRTC0_REGISTER_OFFSET,
56 : CRTC1_REGISTER_OFFSET,
57 : CRTC2_REGISTER_OFFSET,
58 : CRTC3_REGISTER_OFFSET,
59 : CRTC4_REGISTER_OFFSET,
60 : CRTC5_REGISTER_OFFSET,
61 : CRTC6_REGISTER_OFFSET
62 : };
63 :
64 : static const u32 hpd_offsets[] =
65 : {
66 : HPD0_REGISTER_OFFSET,
67 : HPD1_REGISTER_OFFSET,
68 : HPD2_REGISTER_OFFSET,
69 : HPD3_REGISTER_OFFSET,
70 : HPD4_REGISTER_OFFSET,
71 : HPD5_REGISTER_OFFSET
72 : };
73 :
74 : static const uint32_t dig_offsets[] = {
75 : DIG0_REGISTER_OFFSET,
76 : DIG1_REGISTER_OFFSET,
77 : DIG2_REGISTER_OFFSET,
78 : DIG3_REGISTER_OFFSET,
79 : DIG4_REGISTER_OFFSET,
80 : DIG5_REGISTER_OFFSET,
81 : DIG6_REGISTER_OFFSET,
82 : DIG7_REGISTER_OFFSET,
83 : DIG8_REGISTER_OFFSET
84 : };
85 :
86 : static const struct {
87 : uint32_t reg;
88 : uint32_t vblank;
89 : uint32_t vline;
90 : uint32_t hpd;
91 :
92 : } interrupt_status_offsets[] = { {
93 : .reg = mmDISP_INTERRUPT_STATUS,
94 : .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 : .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96 : .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97 : }, {
98 : .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99 : .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 : .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101 : .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102 : }, {
103 : .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104 : .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 : .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106 : .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107 : }, {
108 : .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109 : .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 : .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111 : .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112 : }, {
113 : .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114 : .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 : .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116 : .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117 : }, {
118 : .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119 : .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120 : .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121 : .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122 : } };
123 :
124 : static const u32 cz_golden_settings_a11[] =
125 : {
126 : mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
127 : mmFBC_MISC, 0x1f311fff, 0x14300000,
128 : };
129 :
130 : static const u32 cz_mgcg_cgcg_init[] =
131 : {
132 : mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 : mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134 : };
135 :
136 : static const u32 stoney_golden_settings_a11[] =
137 : {
138 : mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
139 : mmFBC_MISC, 0x1f311fff, 0x14302000,
140 : };
141 :
142 : static const u32 polaris11_golden_settings_a11[] =
143 : {
144 : mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
145 : mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
146 : mmFBC_DEBUG1, 0xffffffff, 0x00000008,
147 : mmFBC_MISC, 0x9f313fff, 0x14302008,
148 : mmHDMI_CONTROL, 0x313f031f, 0x00000011,
149 : };
150 :
151 : static const u32 polaris10_golden_settings_a11[] =
152 : {
153 : mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
154 : mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
155 : mmFBC_MISC, 0x9f313fff, 0x14302008,
156 : mmHDMI_CONTROL, 0x313f031f, 0x00000011,
157 : };
158 :
159 0 : static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
160 : {
161 0 : switch (adev->asic_type) {
162 : case CHIP_CARRIZO:
163 0 : amdgpu_device_program_register_sequence(adev,
164 : cz_mgcg_cgcg_init,
165 : ARRAY_SIZE(cz_mgcg_cgcg_init));
166 0 : amdgpu_device_program_register_sequence(adev,
167 : cz_golden_settings_a11,
168 : ARRAY_SIZE(cz_golden_settings_a11));
169 0 : break;
170 : case CHIP_STONEY:
171 0 : amdgpu_device_program_register_sequence(adev,
172 : stoney_golden_settings_a11,
173 : ARRAY_SIZE(stoney_golden_settings_a11));
174 0 : break;
175 : case CHIP_POLARIS11:
176 : case CHIP_POLARIS12:
177 0 : amdgpu_device_program_register_sequence(adev,
178 : polaris11_golden_settings_a11,
179 : ARRAY_SIZE(polaris11_golden_settings_a11));
180 0 : break;
181 : case CHIP_POLARIS10:
182 : case CHIP_VEGAM:
183 0 : amdgpu_device_program_register_sequence(adev,
184 : polaris10_golden_settings_a11,
185 : ARRAY_SIZE(polaris10_golden_settings_a11));
186 0 : break;
187 : default:
188 : break;
189 : }
190 0 : }
191 :
192 0 : static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
193 : u32 block_offset, u32 reg)
194 : {
195 : unsigned long flags;
196 : u32 r;
197 :
198 0 : spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
199 0 : WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
200 0 : r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
201 0 : spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
202 :
203 0 : return r;
204 : }
205 :
206 0 : static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
207 : u32 block_offset, u32 reg, u32 v)
208 : {
209 : unsigned long flags;
210 :
211 0 : spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
212 0 : WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
213 0 : WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
214 0 : spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
215 0 : }
216 :
217 0 : static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
218 : {
219 0 : if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
220 : return 0;
221 : else
222 0 : return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
223 : }
224 :
225 : static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
226 : {
227 : unsigned i;
228 :
229 : /* Enable pflip interrupts */
230 0 : for (i = 0; i < adev->mode_info.num_crtc; i++)
231 0 : amdgpu_irq_get(adev, &adev->pageflip_irq, i);
232 : }
233 :
234 : static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
235 : {
236 : unsigned i;
237 :
238 : /* Disable pflip interrupts */
239 0 : for (i = 0; i < adev->mode_info.num_crtc; i++)
240 0 : amdgpu_irq_put(adev, &adev->pageflip_irq, i);
241 : }
242 :
243 : /**
244 : * dce_v11_0_page_flip - pageflip callback.
245 : *
246 : * @adev: amdgpu_device pointer
247 : * @crtc_id: crtc to cleanup pageflip on
248 : * @crtc_base: new address of the crtc (GPU MC address)
249 : * @async: asynchronous flip
250 : *
251 : * Triggers the actual pageflip by updating the primary
252 : * surface base address.
253 : */
254 0 : static void dce_v11_0_page_flip(struct amdgpu_device *adev,
255 : int crtc_id, u64 crtc_base, bool async)
256 : {
257 0 : struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
258 0 : struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
259 : u32 tmp;
260 :
261 : /* flip immediate for async, default is vsync */
262 0 : tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
263 0 : tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
264 : GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
265 0 : WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
266 : /* update pitch */
267 0 : WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
268 : fb->pitches[0] / fb->format->cpp[0]);
269 : /* update the scanout addresses */
270 0 : WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
271 : upper_32_bits(crtc_base));
272 : /* writing to the low address triggers the update */
273 0 : WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
274 : lower_32_bits(crtc_base));
275 : /* post the write */
276 0 : RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
277 0 : }
278 :
279 0 : static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
280 : u32 *vbl, u32 *position)
281 : {
282 0 : if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
283 : return -EINVAL;
284 :
285 0 : *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
286 0 : *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
287 :
288 0 : return 0;
289 : }
290 :
291 : /**
292 : * dce_v11_0_hpd_sense - hpd sense callback.
293 : *
294 : * @adev: amdgpu_device pointer
295 : * @hpd: hpd (hotplug detect) pin
296 : *
297 : * Checks if a digital monitor is connected (evergreen+).
298 : * Returns true if connected, false if not connected.
299 : */
300 0 : static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
301 : enum amdgpu_hpd_id hpd)
302 : {
303 0 : bool connected = false;
304 :
305 0 : if (hpd >= adev->mode_info.num_hpd)
306 : return connected;
307 :
308 0 : if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
309 : DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
310 0 : connected = true;
311 :
312 : return connected;
313 : }
314 :
315 : /**
316 : * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
317 : *
318 : * @adev: amdgpu_device pointer
319 : * @hpd: hpd (hotplug detect) pin
320 : *
321 : * Set the polarity of the hpd pin (evergreen+).
322 : */
323 0 : static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
324 : enum amdgpu_hpd_id hpd)
325 : {
326 : u32 tmp;
327 0 : bool connected = dce_v11_0_hpd_sense(adev, hpd);
328 :
329 0 : if (hpd >= adev->mode_info.num_hpd)
330 : return;
331 :
332 0 : tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
333 0 : if (connected)
334 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
335 : else
336 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
337 0 : WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
338 : }
339 :
340 : /**
341 : * dce_v11_0_hpd_init - hpd setup callback.
342 : *
343 : * @adev: amdgpu_device pointer
344 : *
345 : * Setup the hpd pins used by the card (evergreen+).
346 : * Enable the pin, set the polarity, and enable the hpd interrupts.
347 : */
348 0 : static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
349 : {
350 0 : struct drm_device *dev = adev_to_drm(adev);
351 : struct drm_connector *connector;
352 : struct drm_connector_list_iter iter;
353 : u32 tmp;
354 :
355 0 : drm_connector_list_iter_begin(dev, &iter);
356 0 : drm_for_each_connector_iter(connector, &iter) {
357 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
358 :
359 0 : if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
360 0 : continue;
361 :
362 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
363 : connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
364 : /* don't try to enable hpd on eDP or LVDS avoid breaking the
365 : * aux dp channel on imac and help (but not completely fix)
366 : * https://bugzilla.redhat.com/show_bug.cgi?id=726143
367 : * also avoid interrupt storms during dpms.
368 : */
369 0 : tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
370 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
371 0 : WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
372 0 : continue;
373 : }
374 :
375 0 : tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
376 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
377 0 : WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
378 :
379 0 : tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
380 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
381 : DC_HPD_CONNECT_INT_DELAY,
382 : AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
383 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
384 : DC_HPD_DISCONNECT_INT_DELAY,
385 : AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
386 0 : WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
387 :
388 0 : dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
389 0 : amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
390 : }
391 0 : drm_connector_list_iter_end(&iter);
392 0 : }
393 :
394 : /**
395 : * dce_v11_0_hpd_fini - hpd tear down callback.
396 : *
397 : * @adev: amdgpu_device pointer
398 : *
399 : * Tear down the hpd pins used by the card (evergreen+).
400 : * Disable the hpd interrupts.
401 : */
402 0 : static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
403 : {
404 0 : struct drm_device *dev = adev_to_drm(adev);
405 : struct drm_connector *connector;
406 : struct drm_connector_list_iter iter;
407 : u32 tmp;
408 :
409 0 : drm_connector_list_iter_begin(dev, &iter);
410 0 : drm_for_each_connector_iter(connector, &iter) {
411 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
412 :
413 0 : if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
414 0 : continue;
415 :
416 0 : tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
417 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
418 0 : WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
419 :
420 0 : amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
421 : }
422 0 : drm_connector_list_iter_end(&iter);
423 0 : }
424 :
425 0 : static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
426 : {
427 0 : return mmDC_GPIO_HPD_A;
428 : }
429 :
430 0 : static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
431 : {
432 0 : u32 crtc_hung = 0;
433 : u32 crtc_status[6];
434 : u32 i, j, tmp;
435 :
436 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
437 0 : tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
438 0 : if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
439 0 : crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
440 0 : crtc_hung |= (1 << i);
441 : }
442 : }
443 :
444 0 : for (j = 0; j < 10; j++) {
445 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
446 0 : if (crtc_hung & (1 << i)) {
447 0 : tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
448 0 : if (tmp != crtc_status[i])
449 0 : crtc_hung &= ~(1 << i);
450 : }
451 : }
452 0 : if (crtc_hung == 0)
453 : return false;
454 0 : udelay(100);
455 : }
456 :
457 : return true;
458 : }
459 :
460 0 : static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
461 : bool render)
462 : {
463 : u32 tmp;
464 :
465 : /* Lockout access through VGA aperture*/
466 0 : tmp = RREG32(mmVGA_HDP_CONTROL);
467 0 : if (render)
468 0 : tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
469 : else
470 0 : tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
471 0 : WREG32(mmVGA_HDP_CONTROL, tmp);
472 :
473 : /* disable VGA render */
474 0 : tmp = RREG32(mmVGA_RENDER_CONTROL);
475 0 : if (render)
476 0 : tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
477 : else
478 0 : tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
479 0 : WREG32(mmVGA_RENDER_CONTROL, tmp);
480 0 : }
481 :
482 : static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
483 : {
484 0 : int num_crtc = 0;
485 :
486 : switch (adev->asic_type) {
487 : case CHIP_CARRIZO:
488 : num_crtc = 3;
489 : break;
490 : case CHIP_STONEY:
491 : num_crtc = 2;
492 : break;
493 : case CHIP_POLARIS10:
494 : case CHIP_VEGAM:
495 : num_crtc = 6;
496 : break;
497 : case CHIP_POLARIS11:
498 : case CHIP_POLARIS12:
499 : num_crtc = 5;
500 : break;
501 : default:
502 : num_crtc = 0;
503 : }
504 : return num_crtc;
505 : }
506 :
507 0 : void dce_v11_0_disable_dce(struct amdgpu_device *adev)
508 : {
509 : /*Disable VGA render and enabled crtc, if has DCE engine*/
510 0 : if (amdgpu_atombios_has_dce_engine_info(adev)) {
511 : u32 tmp;
512 : int crtc_enabled, i;
513 :
514 0 : dce_v11_0_set_vga_render_state(adev, false);
515 :
516 : /*Disable crtc*/
517 0 : for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
518 0 : crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
519 : CRTC_CONTROL, CRTC_MASTER_EN);
520 0 : if (crtc_enabled) {
521 0 : WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
522 0 : tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
523 0 : tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
524 0 : WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
525 0 : WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
526 : }
527 : }
528 : }
529 0 : }
530 :
531 0 : static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
532 : {
533 0 : struct drm_device *dev = encoder->dev;
534 0 : struct amdgpu_device *adev = drm_to_adev(dev);
535 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
536 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
537 0 : struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
538 0 : int bpc = 0;
539 0 : u32 tmp = 0;
540 0 : enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
541 :
542 0 : if (connector) {
543 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
544 0 : bpc = amdgpu_connector_get_monitor_bpc(connector);
545 0 : dither = amdgpu_connector->dither;
546 : }
547 :
548 : /* LVDS/eDP FMT is set up by atom */
549 0 : if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
550 : return;
551 :
552 : /* not needed for analog */
553 0 : if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
554 : (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
555 : return;
556 :
557 0 : if (bpc == 0)
558 : return;
559 :
560 0 : switch (bpc) {
561 : case 6:
562 0 : if (dither == AMDGPU_FMT_DITHER_ENABLE) {
563 : /* XXX sort out optimal dither settings */
564 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
565 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
566 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
567 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
568 : } else {
569 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
570 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
571 : }
572 : break;
573 : case 8:
574 0 : if (dither == AMDGPU_FMT_DITHER_ENABLE) {
575 : /* XXX sort out optimal dither settings */
576 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
577 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
578 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
579 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
580 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
581 : } else {
582 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
583 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
584 : }
585 : break;
586 : case 10:
587 0 : if (dither == AMDGPU_FMT_DITHER_ENABLE) {
588 : /* XXX sort out optimal dither settings */
589 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
590 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
591 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
592 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
593 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
594 : } else {
595 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
596 0 : tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
597 : }
598 : break;
599 : default:
600 : /* not needed */
601 : break;
602 : }
603 :
604 0 : WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
605 : }
606 :
607 :
608 : /* display watermark setup */
609 : /**
610 : * dce_v11_0_line_buffer_adjust - Set up the line buffer
611 : *
612 : * @adev: amdgpu_device pointer
613 : * @amdgpu_crtc: the selected display controller
614 : * @mode: the current display mode on the selected display
615 : * controller
616 : *
617 : * Setup up the line buffer allocation for
618 : * the selected display controller (CIK).
619 : * Returns the line buffer size in pixels.
620 : */
621 0 : static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
622 : struct amdgpu_crtc *amdgpu_crtc,
623 : struct drm_display_mode *mode)
624 : {
625 : u32 tmp, buffer_alloc, i, mem_cfg;
626 0 : u32 pipe_offset = amdgpu_crtc->crtc_id;
627 : /*
628 : * Line Buffer Setup
629 : * There are 6 line buffers, one for each display controllers.
630 : * There are 3 partitions per LB. Select the number of partitions
631 : * to enable based on the display width. For display widths larger
632 : * than 4096, you need use to use 2 display controllers and combine
633 : * them using the stereo blender.
634 : */
635 0 : if (amdgpu_crtc->base.enabled && mode) {
636 0 : if (mode->crtc_hdisplay < 1920) {
637 : mem_cfg = 1;
638 : buffer_alloc = 2;
639 0 : } else if (mode->crtc_hdisplay < 2560) {
640 : mem_cfg = 2;
641 : buffer_alloc = 2;
642 0 : } else if (mode->crtc_hdisplay < 4096) {
643 0 : mem_cfg = 0;
644 0 : buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
645 : } else {
646 0 : DRM_DEBUG_KMS("Mode too big for LB!\n");
647 0 : mem_cfg = 0;
648 0 : buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
649 : }
650 : } else {
651 : mem_cfg = 1;
652 : buffer_alloc = 0;
653 : }
654 :
655 0 : tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
656 0 : tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
657 0 : WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
658 :
659 0 : tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
660 0 : tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
661 0 : WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
662 :
663 0 : for (i = 0; i < adev->usec_timeout; i++) {
664 0 : tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
665 0 : if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
666 : break;
667 0 : udelay(1);
668 : }
669 :
670 0 : if (amdgpu_crtc->base.enabled && mode) {
671 0 : switch (mem_cfg) {
672 : case 0:
673 : default:
674 : return 4096 * 2;
675 : case 1:
676 0 : return 1920 * 2;
677 : case 2:
678 0 : return 2560 * 2;
679 : }
680 : }
681 :
682 : /* controller not enabled, so no lb used */
683 : return 0;
684 : }
685 :
686 : /**
687 : * cik_get_number_of_dram_channels - get the number of dram channels
688 : *
689 : * @adev: amdgpu_device pointer
690 : *
691 : * Look up the number of video ram channels (CIK).
692 : * Used for display watermark bandwidth calculations
693 : * Returns the number of dram channels
694 : */
695 0 : static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
696 : {
697 0 : u32 tmp = RREG32(mmMC_SHARED_CHMAP);
698 :
699 0 : switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
700 : case 0:
701 : default:
702 : return 1;
703 : case 1:
704 : return 2;
705 : case 2:
706 : return 4;
707 : case 3:
708 : return 8;
709 : case 4:
710 : return 3;
711 : case 5:
712 : return 6;
713 : case 6:
714 : return 10;
715 : case 7:
716 : return 12;
717 : case 8:
718 : return 16;
719 : }
720 : }
721 :
722 : struct dce10_wm_params {
723 : u32 dram_channels; /* number of dram channels */
724 : u32 yclk; /* bandwidth per dram data pin in kHz */
725 : u32 sclk; /* engine clock in kHz */
726 : u32 disp_clk; /* display clock in kHz */
727 : u32 src_width; /* viewport width */
728 : u32 active_time; /* active display time in ns */
729 : u32 blank_time; /* blank time in ns */
730 : bool interlaced; /* mode is interlaced */
731 : fixed20_12 vsc; /* vertical scale ratio */
732 : u32 num_heads; /* number of active crtcs */
733 : u32 bytes_per_pixel; /* bytes per pixel display + overlay */
734 : u32 lb_size; /* line buffer allocated to pipe */
735 : u32 vtaps; /* vertical scaler taps */
736 : };
737 :
738 : /**
739 : * dce_v11_0_dram_bandwidth - get the dram bandwidth
740 : *
741 : * @wm: watermark calculation data
742 : *
743 : * Calculate the raw dram bandwidth (CIK).
744 : * Used for display watermark bandwidth calculations
745 : * Returns the dram bandwidth in MBytes/s
746 : */
747 : static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
748 : {
749 : /* Calculate raw DRAM Bandwidth */
750 : fixed20_12 dram_efficiency; /* 0.7 */
751 : fixed20_12 yclk, dram_channels, bandwidth;
752 : fixed20_12 a;
753 :
754 0 : a.full = dfixed_const(1000);
755 0 : yclk.full = dfixed_const(wm->yclk);
756 0 : yclk.full = dfixed_div(yclk, a);
757 0 : dram_channels.full = dfixed_const(wm->dram_channels * 4);
758 0 : a.full = dfixed_const(10);
759 0 : dram_efficiency.full = dfixed_const(7);
760 0 : dram_efficiency.full = dfixed_div(dram_efficiency, a);
761 0 : bandwidth.full = dfixed_mul(dram_channels, yclk);
762 0 : bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
763 :
764 0 : return dfixed_trunc(bandwidth);
765 : }
766 :
767 : /**
768 : * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
769 : *
770 : * @wm: watermark calculation data
771 : *
772 : * Calculate the dram bandwidth used for display (CIK).
773 : * Used for display watermark bandwidth calculations
774 : * Returns the dram bandwidth for display in MBytes/s
775 : */
776 : static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
777 : {
778 : /* Calculate DRAM Bandwidth and the part allocated to display. */
779 : fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
780 : fixed20_12 yclk, dram_channels, bandwidth;
781 : fixed20_12 a;
782 :
783 0 : a.full = dfixed_const(1000);
784 0 : yclk.full = dfixed_const(wm->yclk);
785 0 : yclk.full = dfixed_div(yclk, a);
786 0 : dram_channels.full = dfixed_const(wm->dram_channels * 4);
787 0 : a.full = dfixed_const(10);
788 0 : disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
789 0 : disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
790 0 : bandwidth.full = dfixed_mul(dram_channels, yclk);
791 0 : bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
792 :
793 0 : return dfixed_trunc(bandwidth);
794 : }
795 :
796 : /**
797 : * dce_v11_0_data_return_bandwidth - get the data return bandwidth
798 : *
799 : * @wm: watermark calculation data
800 : *
801 : * Calculate the data return bandwidth used for display (CIK).
802 : * Used for display watermark bandwidth calculations
803 : * Returns the data return bandwidth in MBytes/s
804 : */
805 : static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
806 : {
807 : /* Calculate the display Data return Bandwidth */
808 : fixed20_12 return_efficiency; /* 0.8 */
809 : fixed20_12 sclk, bandwidth;
810 : fixed20_12 a;
811 :
812 0 : a.full = dfixed_const(1000);
813 0 : sclk.full = dfixed_const(wm->sclk);
814 0 : sclk.full = dfixed_div(sclk, a);
815 0 : a.full = dfixed_const(10);
816 0 : return_efficiency.full = dfixed_const(8);
817 0 : return_efficiency.full = dfixed_div(return_efficiency, a);
818 0 : a.full = dfixed_const(32);
819 0 : bandwidth.full = dfixed_mul(a, sclk);
820 0 : bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
821 :
822 0 : return dfixed_trunc(bandwidth);
823 : }
824 :
825 : /**
826 : * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
827 : *
828 : * @wm: watermark calculation data
829 : *
830 : * Calculate the dmif bandwidth used for display (CIK).
831 : * Used for display watermark bandwidth calculations
832 : * Returns the dmif bandwidth in MBytes/s
833 : */
834 : static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
835 : {
836 : /* Calculate the DMIF Request Bandwidth */
837 : fixed20_12 disp_clk_request_efficiency; /* 0.8 */
838 : fixed20_12 disp_clk, bandwidth;
839 : fixed20_12 a, b;
840 :
841 0 : a.full = dfixed_const(1000);
842 0 : disp_clk.full = dfixed_const(wm->disp_clk);
843 0 : disp_clk.full = dfixed_div(disp_clk, a);
844 0 : a.full = dfixed_const(32);
845 0 : b.full = dfixed_mul(a, disp_clk);
846 :
847 0 : a.full = dfixed_const(10);
848 0 : disp_clk_request_efficiency.full = dfixed_const(8);
849 0 : disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
850 :
851 0 : bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
852 :
853 0 : return dfixed_trunc(bandwidth);
854 : }
855 :
856 : /**
857 : * dce_v11_0_available_bandwidth - get the min available bandwidth
858 : *
859 : * @wm: watermark calculation data
860 : *
861 : * Calculate the min available bandwidth used for display (CIK).
862 : * Used for display watermark bandwidth calculations
863 : * Returns the min available bandwidth in MBytes/s
864 : */
865 0 : static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
866 : {
867 : /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
868 0 : u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
869 0 : u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
870 0 : u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
871 :
872 0 : return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
873 : }
874 :
875 : /**
876 : * dce_v11_0_average_bandwidth - get the average available bandwidth
877 : *
878 : * @wm: watermark calculation data
879 : *
880 : * Calculate the average available bandwidth used for display (CIK).
881 : * Used for display watermark bandwidth calculations
882 : * Returns the average available bandwidth in MBytes/s
883 : */
884 0 : static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
885 : {
886 : /* Calculate the display mode Average Bandwidth
887 : * DisplayMode should contain the source and destination dimensions,
888 : * timing, etc.
889 : */
890 : fixed20_12 bpp;
891 : fixed20_12 line_time;
892 : fixed20_12 src_width;
893 : fixed20_12 bandwidth;
894 : fixed20_12 a;
895 :
896 0 : a.full = dfixed_const(1000);
897 0 : line_time.full = dfixed_const(wm->active_time + wm->blank_time);
898 0 : line_time.full = dfixed_div(line_time, a);
899 0 : bpp.full = dfixed_const(wm->bytes_per_pixel);
900 0 : src_width.full = dfixed_const(wm->src_width);
901 0 : bandwidth.full = dfixed_mul(src_width, bpp);
902 0 : bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
903 0 : bandwidth.full = dfixed_div(bandwidth, line_time);
904 :
905 0 : return dfixed_trunc(bandwidth);
906 : }
907 :
908 : /**
909 : * dce_v11_0_latency_watermark - get the latency watermark
910 : *
911 : * @wm: watermark calculation data
912 : *
913 : * Calculate the latency watermark (CIK).
914 : * Used for display watermark bandwidth calculations
915 : * Returns the latency watermark in ns
916 : */
917 0 : static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
918 : {
919 : /* First calculate the latency in ns */
920 0 : u32 mc_latency = 2000; /* 2000 ns. */
921 0 : u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
922 0 : u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
923 0 : u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
924 0 : u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
925 0 : u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
926 0 : (wm->num_heads * cursor_line_pair_return_time);
927 0 : u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
928 : u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
929 0 : u32 tmp, dmif_size = 12288;
930 : fixed20_12 a, b, c;
931 :
932 0 : if (wm->num_heads == 0)
933 : return 0;
934 :
935 0 : a.full = dfixed_const(2);
936 0 : b.full = dfixed_const(1);
937 0 : if ((wm->vsc.full > a.full) ||
938 0 : ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
939 0 : (wm->vtaps >= 5) ||
940 0 : ((wm->vsc.full >= a.full) && wm->interlaced))
941 : max_src_lines_per_dst_line = 4;
942 : else
943 0 : max_src_lines_per_dst_line = 2;
944 :
945 0 : a.full = dfixed_const(available_bandwidth);
946 0 : b.full = dfixed_const(wm->num_heads);
947 0 : a.full = dfixed_div(a, b);
948 0 : tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
949 0 : tmp = min(dfixed_trunc(a), tmp);
950 :
951 0 : lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
952 :
953 0 : a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
954 0 : b.full = dfixed_const(1000);
955 0 : c.full = dfixed_const(lb_fill_bw);
956 0 : b.full = dfixed_div(c, b);
957 0 : a.full = dfixed_div(a, b);
958 0 : line_fill_time = dfixed_trunc(a);
959 :
960 0 : if (line_fill_time < wm->active_time)
961 : return latency;
962 : else
963 0 : return latency + (line_fill_time - wm->active_time);
964 :
965 : }
966 :
967 : /**
968 : * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
969 : * average and available dram bandwidth
970 : *
971 : * @wm: watermark calculation data
972 : *
973 : * Check if the display average bandwidth fits in the display
974 : * dram bandwidth (CIK).
975 : * Used for display watermark bandwidth calculations
976 : * Returns true if the display fits, false if not.
977 : */
978 0 : static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
979 : {
980 0 : if (dce_v11_0_average_bandwidth(wm) <=
981 0 : (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
982 : return true;
983 : else
984 0 : return false;
985 : }
986 :
987 : /**
988 : * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
989 : * average and available bandwidth
990 : *
991 : * @wm: watermark calculation data
992 : *
993 : * Check if the display average bandwidth fits in the display
994 : * available bandwidth (CIK).
995 : * Used for display watermark bandwidth calculations
996 : * Returns true if the display fits, false if not.
997 : */
998 0 : static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
999 : {
1000 0 : if (dce_v11_0_average_bandwidth(wm) <=
1001 0 : (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1002 : return true;
1003 : else
1004 0 : return false;
1005 : }
1006 :
1007 : /**
1008 : * dce_v11_0_check_latency_hiding - check latency hiding
1009 : *
1010 : * @wm: watermark calculation data
1011 : *
1012 : * Check latency hiding (CIK).
1013 : * Used for display watermark bandwidth calculations
1014 : * Returns true if the display fits, false if not.
1015 : */
1016 0 : static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1017 : {
1018 0 : u32 lb_partitions = wm->lb_size / wm->src_width;
1019 0 : u32 line_time = wm->active_time + wm->blank_time;
1020 : u32 latency_tolerant_lines;
1021 : u32 latency_hiding;
1022 : fixed20_12 a;
1023 :
1024 0 : a.full = dfixed_const(1);
1025 0 : if (wm->vsc.full > a.full)
1026 : latency_tolerant_lines = 1;
1027 : else {
1028 0 : if (lb_partitions <= (wm->vtaps + 1))
1029 : latency_tolerant_lines = 1;
1030 : else
1031 0 : latency_tolerant_lines = 2;
1032 : }
1033 :
1034 0 : latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1035 :
1036 0 : if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1037 : return true;
1038 : else
1039 0 : return false;
1040 : }
1041 :
1042 : /**
1043 : * dce_v11_0_program_watermarks - program display watermarks
1044 : *
1045 : * @adev: amdgpu_device pointer
1046 : * @amdgpu_crtc: the selected display controller
1047 : * @lb_size: line buffer size
1048 : * @num_heads: number of display controllers in use
1049 : *
1050 : * Calculate and program the display watermarks for the
1051 : * selected display controller (CIK).
1052 : */
1053 0 : static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1054 : struct amdgpu_crtc *amdgpu_crtc,
1055 : u32 lb_size, u32 num_heads)
1056 : {
1057 0 : struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1058 : struct dce10_wm_params wm_low, wm_high;
1059 : u32 active_time;
1060 0 : u32 line_time = 0;
1061 0 : u32 latency_watermark_a = 0, latency_watermark_b = 0;
1062 0 : u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1063 :
1064 0 : if (amdgpu_crtc->base.enabled && num_heads && mode) {
1065 0 : active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1066 0 : (u32)mode->clock);
1067 0 : line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1068 : (u32)mode->clock);
1069 0 : line_time = min(line_time, (u32)65535);
1070 :
1071 : /* watermark for high clocks */
1072 0 : if (adev->pm.dpm_enabled) {
1073 0 : wm_high.yclk =
1074 0 : amdgpu_dpm_get_mclk(adev, false) * 10;
1075 0 : wm_high.sclk =
1076 0 : amdgpu_dpm_get_sclk(adev, false) * 10;
1077 : } else {
1078 0 : wm_high.yclk = adev->pm.current_mclk * 10;
1079 0 : wm_high.sclk = adev->pm.current_sclk * 10;
1080 : }
1081 :
1082 0 : wm_high.disp_clk = mode->clock;
1083 0 : wm_high.src_width = mode->crtc_hdisplay;
1084 0 : wm_high.active_time = active_time;
1085 0 : wm_high.blank_time = line_time - wm_high.active_time;
1086 0 : wm_high.interlaced = false;
1087 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1088 0 : wm_high.interlaced = true;
1089 0 : wm_high.vsc = amdgpu_crtc->vsc;
1090 0 : wm_high.vtaps = 1;
1091 0 : if (amdgpu_crtc->rmx_type != RMX_OFF)
1092 0 : wm_high.vtaps = 2;
1093 0 : wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1094 0 : wm_high.lb_size = lb_size;
1095 0 : wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1096 0 : wm_high.num_heads = num_heads;
1097 :
1098 : /* set for high clocks */
1099 0 : latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1100 :
1101 : /* possibly force display priority to high */
1102 : /* should really do this at mode validation time... */
1103 0 : if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1104 0 : !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1105 0 : !dce_v11_0_check_latency_hiding(&wm_high) ||
1106 0 : (adev->mode_info.disp_priority == 2)) {
1107 0 : DRM_DEBUG_KMS("force priority to high\n");
1108 : }
1109 :
1110 : /* watermark for low clocks */
1111 0 : if (adev->pm.dpm_enabled) {
1112 0 : wm_low.yclk =
1113 0 : amdgpu_dpm_get_mclk(adev, true) * 10;
1114 0 : wm_low.sclk =
1115 0 : amdgpu_dpm_get_sclk(adev, true) * 10;
1116 : } else {
1117 0 : wm_low.yclk = adev->pm.current_mclk * 10;
1118 0 : wm_low.sclk = adev->pm.current_sclk * 10;
1119 : }
1120 :
1121 0 : wm_low.disp_clk = mode->clock;
1122 0 : wm_low.src_width = mode->crtc_hdisplay;
1123 0 : wm_low.active_time = active_time;
1124 0 : wm_low.blank_time = line_time - wm_low.active_time;
1125 0 : wm_low.interlaced = false;
1126 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1127 0 : wm_low.interlaced = true;
1128 0 : wm_low.vsc = amdgpu_crtc->vsc;
1129 0 : wm_low.vtaps = 1;
1130 0 : if (amdgpu_crtc->rmx_type != RMX_OFF)
1131 0 : wm_low.vtaps = 2;
1132 0 : wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1133 0 : wm_low.lb_size = lb_size;
1134 0 : wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1135 0 : wm_low.num_heads = num_heads;
1136 :
1137 : /* set for low clocks */
1138 0 : latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1139 :
1140 : /* possibly force display priority to high */
1141 : /* should really do this at mode validation time... */
1142 0 : if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1143 0 : !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1144 0 : !dce_v11_0_check_latency_hiding(&wm_low) ||
1145 0 : (adev->mode_info.disp_priority == 2)) {
1146 0 : DRM_DEBUG_KMS("force priority to high\n");
1147 : }
1148 0 : lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1149 : }
1150 :
1151 : /* select wm A */
1152 0 : wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1153 0 : tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1154 0 : WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1155 0 : tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1156 0 : tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1157 0 : tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1158 0 : WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1159 : /* select wm B */
1160 0 : tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1161 0 : WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1162 0 : tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1163 0 : tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1164 0 : tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1165 0 : WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1166 : /* restore original selection */
1167 0 : WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1168 :
1169 : /* save values for DPM */
1170 0 : amdgpu_crtc->line_time = line_time;
1171 0 : amdgpu_crtc->wm_high = latency_watermark_a;
1172 0 : amdgpu_crtc->wm_low = latency_watermark_b;
1173 : /* Save number of lines the linebuffer leads before the scanout */
1174 0 : amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1175 0 : }
1176 :
1177 : /**
1178 : * dce_v11_0_bandwidth_update - program display watermarks
1179 : *
1180 : * @adev: amdgpu_device pointer
1181 : *
1182 : * Calculate and program the display watermarks and line
1183 : * buffer allocation (CIK).
1184 : */
1185 0 : static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1186 : {
1187 0 : struct drm_display_mode *mode = NULL;
1188 0 : u32 num_heads = 0, lb_size;
1189 : int i;
1190 :
1191 0 : amdgpu_display_update_priority(adev);
1192 :
1193 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
1194 0 : if (adev->mode_info.crtcs[i]->base.enabled)
1195 0 : num_heads++;
1196 : }
1197 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
1198 0 : mode = &adev->mode_info.crtcs[i]->base.mode;
1199 0 : lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1200 0 : dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1201 : lb_size, num_heads);
1202 : }
1203 0 : }
1204 :
1205 : static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1206 : {
1207 : int i;
1208 : u32 offset, tmp;
1209 :
1210 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1211 0 : offset = adev->mode_info.audio.pin[i].offset;
1212 0 : tmp = RREG32_AUDIO_ENDPT(offset,
1213 : ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1214 0 : if (((tmp &
1215 0 : AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1216 : AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1217 0 : adev->mode_info.audio.pin[i].connected = false;
1218 : else
1219 0 : adev->mode_info.audio.pin[i].connected = true;
1220 : }
1221 : }
1222 :
1223 0 : static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1224 : {
1225 : int i;
1226 :
1227 : dce_v11_0_audio_get_connected_pins(adev);
1228 :
1229 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1230 0 : if (adev->mode_info.audio.pin[i].connected)
1231 0 : return &adev->mode_info.audio.pin[i];
1232 : }
1233 0 : DRM_ERROR("No connected audio pins found!\n");
1234 0 : return NULL;
1235 : }
1236 :
1237 0 : static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1238 : {
1239 0 : struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1240 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1241 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1242 : u32 tmp;
1243 :
1244 0 : if (!dig || !dig->afmt || !dig->afmt->pin)
1245 : return;
1246 :
1247 0 : tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1248 0 : tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1249 0 : WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1250 : }
1251 :
1252 0 : static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1253 : struct drm_display_mode *mode)
1254 : {
1255 0 : struct drm_device *dev = encoder->dev;
1256 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1257 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1258 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1259 : struct drm_connector *connector;
1260 : struct drm_connector_list_iter iter;
1261 0 : struct amdgpu_connector *amdgpu_connector = NULL;
1262 : u32 tmp;
1263 0 : int interlace = 0;
1264 :
1265 0 : if (!dig || !dig->afmt || !dig->afmt->pin)
1266 0 : return;
1267 :
1268 0 : drm_connector_list_iter_begin(dev, &iter);
1269 0 : drm_for_each_connector_iter(connector, &iter) {
1270 0 : if (connector->encoder == encoder) {
1271 : amdgpu_connector = to_amdgpu_connector(connector);
1272 : break;
1273 : }
1274 : }
1275 0 : drm_connector_list_iter_end(&iter);
1276 :
1277 0 : if (!amdgpu_connector) {
1278 0 : DRM_ERROR("Couldn't find encoder's connector\n");
1279 : return;
1280 : }
1281 :
1282 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1283 0 : interlace = 1;
1284 0 : if (connector->latency_present[interlace]) {
1285 0 : tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1286 : VIDEO_LIPSYNC, connector->video_latency[interlace]);
1287 0 : tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1288 : AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1289 : } else {
1290 : tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1291 : VIDEO_LIPSYNC, 0);
1292 : tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1293 : AUDIO_LIPSYNC, 0);
1294 : }
1295 0 : WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1296 : ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1297 : }
1298 :
1299 0 : static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1300 : {
1301 0 : struct drm_device *dev = encoder->dev;
1302 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1303 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1304 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1305 : struct drm_connector *connector;
1306 : struct drm_connector_list_iter iter;
1307 0 : struct amdgpu_connector *amdgpu_connector = NULL;
1308 : u32 tmp;
1309 0 : u8 *sadb = NULL;
1310 : int sad_count;
1311 :
1312 0 : if (!dig || !dig->afmt || !dig->afmt->pin)
1313 0 : return;
1314 :
1315 0 : drm_connector_list_iter_begin(dev, &iter);
1316 0 : drm_for_each_connector_iter(connector, &iter) {
1317 0 : if (connector->encoder == encoder) {
1318 : amdgpu_connector = to_amdgpu_connector(connector);
1319 : break;
1320 : }
1321 : }
1322 0 : drm_connector_list_iter_end(&iter);
1323 :
1324 0 : if (!amdgpu_connector) {
1325 0 : DRM_ERROR("Couldn't find encoder's connector\n");
1326 0 : return;
1327 : }
1328 :
1329 0 : sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1330 0 : if (sad_count < 0) {
1331 0 : DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1332 0 : sad_count = 0;
1333 : }
1334 :
1335 : /* program the speaker allocation */
1336 0 : tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1337 : ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1338 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1339 : DP_CONNECTION, 0);
1340 : /* set HDMI mode */
1341 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1342 : HDMI_CONNECTION, 1);
1343 0 : if (sad_count)
1344 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1345 : SPEAKER_ALLOCATION, sadb[0]);
1346 : else
1347 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1348 : SPEAKER_ALLOCATION, 5); /* stereo */
1349 0 : WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1350 : ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1351 :
1352 0 : kfree(sadb);
1353 : }
1354 :
1355 0 : static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1356 : {
1357 0 : struct drm_device *dev = encoder->dev;
1358 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1359 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1360 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1361 : struct drm_connector *connector;
1362 : struct drm_connector_list_iter iter;
1363 0 : struct amdgpu_connector *amdgpu_connector = NULL;
1364 : struct cea_sad *sads;
1365 : int i, sad_count;
1366 :
1367 : static const u16 eld_reg_to_type[][2] = {
1368 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1369 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1370 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1371 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1372 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1373 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1374 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1375 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1376 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1377 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1378 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1379 : { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1380 : };
1381 :
1382 0 : if (!dig || !dig->afmt || !dig->afmt->pin)
1383 0 : return;
1384 :
1385 0 : drm_connector_list_iter_begin(dev, &iter);
1386 0 : drm_for_each_connector_iter(connector, &iter) {
1387 0 : if (connector->encoder == encoder) {
1388 : amdgpu_connector = to_amdgpu_connector(connector);
1389 : break;
1390 : }
1391 : }
1392 0 : drm_connector_list_iter_end(&iter);
1393 :
1394 0 : if (!amdgpu_connector) {
1395 0 : DRM_ERROR("Couldn't find encoder's connector\n");
1396 0 : return;
1397 : }
1398 :
1399 0 : sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1400 0 : if (sad_count < 0)
1401 0 : DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1402 0 : if (sad_count <= 0)
1403 : return;
1404 0 : BUG_ON(!sads);
1405 :
1406 0 : for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1407 : u32 tmp = 0;
1408 : u8 stereo_freqs = 0;
1409 : int max_channels = -1;
1410 : int j;
1411 :
1412 0 : for (j = 0; j < sad_count; j++) {
1413 0 : struct cea_sad *sad = &sads[j];
1414 :
1415 0 : if (sad->format == eld_reg_to_type[i][1]) {
1416 0 : if (sad->channels > max_channels) {
1417 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1418 : MAX_CHANNELS, sad->channels);
1419 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1420 : DESCRIPTOR_BYTE_2, sad->byte2);
1421 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1422 : SUPPORTED_FREQUENCIES, sad->freq);
1423 0 : max_channels = sad->channels;
1424 : }
1425 :
1426 0 : if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1427 0 : stereo_freqs |= sad->freq;
1428 : else
1429 : break;
1430 : }
1431 : }
1432 :
1433 0 : tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1434 : SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1435 0 : WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1436 : }
1437 :
1438 0 : kfree(sads);
1439 : }
1440 :
1441 : static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1442 : struct amdgpu_audio_pin *pin,
1443 : bool enable)
1444 : {
1445 0 : if (!pin)
1446 : return;
1447 :
1448 0 : WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1449 : enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1450 : }
1451 :
1452 : static const u32 pin_offsets[] =
1453 : {
1454 : AUD0_REGISTER_OFFSET,
1455 : AUD1_REGISTER_OFFSET,
1456 : AUD2_REGISTER_OFFSET,
1457 : AUD3_REGISTER_OFFSET,
1458 : AUD4_REGISTER_OFFSET,
1459 : AUD5_REGISTER_OFFSET,
1460 : AUD6_REGISTER_OFFSET,
1461 : AUD7_REGISTER_OFFSET,
1462 : };
1463 :
1464 0 : static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1465 : {
1466 : int i;
1467 :
1468 0 : if (!amdgpu_audio)
1469 : return 0;
1470 :
1471 0 : adev->mode_info.audio.enabled = true;
1472 :
1473 0 : switch (adev->asic_type) {
1474 : case CHIP_CARRIZO:
1475 : case CHIP_STONEY:
1476 0 : adev->mode_info.audio.num_pins = 7;
1477 0 : break;
1478 : case CHIP_POLARIS10:
1479 : case CHIP_VEGAM:
1480 0 : adev->mode_info.audio.num_pins = 8;
1481 0 : break;
1482 : case CHIP_POLARIS11:
1483 : case CHIP_POLARIS12:
1484 0 : adev->mode_info.audio.num_pins = 6;
1485 0 : break;
1486 : default:
1487 : return -EINVAL;
1488 : }
1489 :
1490 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1491 0 : adev->mode_info.audio.pin[i].channels = -1;
1492 0 : adev->mode_info.audio.pin[i].rate = -1;
1493 0 : adev->mode_info.audio.pin[i].bits_per_sample = -1;
1494 0 : adev->mode_info.audio.pin[i].status_bits = 0;
1495 0 : adev->mode_info.audio.pin[i].category_code = 0;
1496 0 : adev->mode_info.audio.pin[i].connected = false;
1497 0 : adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1498 0 : adev->mode_info.audio.pin[i].id = i;
1499 : /* disable audio. it will be set up later */
1500 : /* XXX remove once we switch to ip funcs */
1501 0 : dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1502 : }
1503 :
1504 : return 0;
1505 : }
1506 :
1507 0 : static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1508 : {
1509 : int i;
1510 :
1511 0 : if (!amdgpu_audio)
1512 : return;
1513 :
1514 0 : if (!adev->mode_info.audio.enabled)
1515 : return;
1516 :
1517 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1518 0 : dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1519 :
1520 0 : adev->mode_info.audio.enabled = false;
1521 : }
1522 :
1523 : /*
1524 : * update the N and CTS parameters for a given pixel clock rate
1525 : */
1526 0 : static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1527 : {
1528 0 : struct drm_device *dev = encoder->dev;
1529 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1530 0 : struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1531 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1532 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1533 : u32 tmp;
1534 :
1535 0 : tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1536 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1537 0 : WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1538 0 : tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1539 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1540 0 : WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1541 :
1542 0 : tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1543 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1544 0 : WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1545 0 : tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1546 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1547 0 : WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1548 :
1549 0 : tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1550 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1551 0 : WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1552 0 : tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1553 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1554 0 : WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1555 :
1556 0 : }
1557 :
1558 : /*
1559 : * build a HDMI Video Info Frame
1560 : */
1561 0 : static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1562 : void *buffer, size_t size)
1563 : {
1564 0 : struct drm_device *dev = encoder->dev;
1565 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1566 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1567 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568 0 : uint8_t *frame = buffer + 3;
1569 0 : uint8_t *header = buffer;
1570 :
1571 0 : WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1572 : frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1573 0 : WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1574 : frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1575 0 : WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1576 : frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1577 0 : WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1578 : frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1579 0 : }
1580 :
1581 0 : static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1582 : {
1583 0 : struct drm_device *dev = encoder->dev;
1584 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1585 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1586 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1587 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1588 0 : u32 dto_phase = 24 * 1000;
1589 0 : u32 dto_modulo = clock;
1590 : u32 tmp;
1591 :
1592 0 : if (!dig || !dig->afmt)
1593 : return;
1594 :
1595 : /* XXX two dtos; generally use dto0 for hdmi */
1596 : /* Express [24MHz / target pixel clock] as an exact rational
1597 : * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1598 : * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1599 : */
1600 0 : tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1601 0 : tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1602 : amdgpu_crtc->crtc_id);
1603 0 : WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1604 0 : WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1605 0 : WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1606 : }
1607 :
1608 : /*
1609 : * update the info frames with the data from the current display mode
1610 : */
1611 0 : static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1612 : struct drm_display_mode *mode)
1613 : {
1614 0 : struct drm_device *dev = encoder->dev;
1615 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1616 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1617 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1618 0 : struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1619 : u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1620 : struct hdmi_avi_infoframe frame;
1621 : ssize_t err;
1622 : u32 tmp;
1623 0 : int bpc = 8;
1624 :
1625 0 : if (!dig || !dig->afmt)
1626 0 : return;
1627 :
1628 : /* Silent, r600_hdmi_enable will raise WARN for us */
1629 0 : if (!dig->afmt->enabled)
1630 : return;
1631 :
1632 : /* hdmi deep color mode general control packets setup, if bpc > 8 */
1633 0 : if (encoder->crtc) {
1634 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1635 0 : bpc = amdgpu_crtc->bpc;
1636 : }
1637 :
1638 : /* disable audio prior to setting up hw */
1639 0 : dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1640 0 : dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1641 :
1642 0 : dce_v11_0_audio_set_dto(encoder, mode->clock);
1643 :
1644 0 : tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1645 0 : tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1646 0 : WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1647 :
1648 0 : WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1649 :
1650 0 : tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1651 0 : switch (bpc) {
1652 : case 0:
1653 : case 6:
1654 : case 8:
1655 : case 16:
1656 : default:
1657 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1658 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1659 0 : DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1660 : connector->name, bpc);
1661 0 : break;
1662 : case 10:
1663 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1664 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1665 0 : DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1666 : connector->name);
1667 0 : break;
1668 : case 12:
1669 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1670 0 : tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1671 0 : DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1672 : connector->name);
1673 0 : break;
1674 : }
1675 0 : WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1676 :
1677 0 : tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1678 0 : tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1679 0 : tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1680 0 : tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1681 0 : WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1682 :
1683 0 : tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1684 : /* enable audio info frames (frames won't be set until audio is enabled) */
1685 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1686 : /* required for audio info values to be updated */
1687 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1688 0 : WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1689 :
1690 0 : tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1691 : /* required for audio info values to be updated */
1692 0 : tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1693 0 : WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1694 :
1695 0 : tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1696 : /* anything other than 0 */
1697 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1698 0 : WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1699 :
1700 0 : WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1701 :
1702 0 : tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1703 : /* set the default audio delay */
1704 0 : tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1705 : /* should be suffient for all audio modes and small enough for all hblanks */
1706 0 : tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1707 0 : WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1708 :
1709 0 : tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1710 : /* allow 60958 channel status fields to be updated */
1711 0 : tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1712 0 : WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1713 :
1714 0 : tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1715 0 : if (bpc > 8)
1716 : /* clear SW CTS value */
1717 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1718 : else
1719 : /* select SW CTS value */
1720 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1721 : /* allow hw to sent ACR packets when required */
1722 0 : tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1723 0 : WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1724 :
1725 0 : dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1726 :
1727 0 : tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1728 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1729 0 : WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1730 :
1731 0 : tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1732 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1733 0 : WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1734 :
1735 0 : tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1736 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1737 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1738 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1739 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1740 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1741 0 : tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1742 0 : WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1743 :
1744 0 : dce_v11_0_audio_write_speaker_allocation(encoder);
1745 :
1746 0 : WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1747 : (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1748 :
1749 0 : dce_v11_0_afmt_audio_select_pin(encoder);
1750 0 : dce_v11_0_audio_write_sad_regs(encoder);
1751 0 : dce_v11_0_audio_write_latency_fields(encoder, mode);
1752 :
1753 0 : err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1754 0 : if (err < 0) {
1755 0 : DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1756 0 : return;
1757 : }
1758 :
1759 0 : err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1760 0 : if (err < 0) {
1761 0 : DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1762 0 : return;
1763 : }
1764 :
1765 0 : dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1766 :
1767 0 : tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1768 : /* enable AVI info frames */
1769 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1770 : /* required for audio info values to be updated */
1771 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1772 0 : WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1773 :
1774 0 : tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1775 0 : tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1776 0 : WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1777 :
1778 0 : tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1779 : /* send audio packets */
1780 0 : tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1781 0 : WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1782 :
1783 0 : WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1784 0 : WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1785 0 : WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1786 0 : WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1787 :
1788 : /* enable audio after to setting up hw */
1789 0 : dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1790 : }
1791 :
1792 0 : static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1793 : {
1794 0 : struct drm_device *dev = encoder->dev;
1795 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1796 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1797 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1798 :
1799 0 : if (!dig || !dig->afmt)
1800 : return;
1801 :
1802 : /* Silent, r600_hdmi_enable will raise WARN for us */
1803 0 : if (enable && dig->afmt->enabled)
1804 : return;
1805 0 : if (!enable && !dig->afmt->enabled)
1806 : return;
1807 :
1808 0 : if (!enable && dig->afmt->pin) {
1809 0 : dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1810 0 : dig->afmt->pin = NULL;
1811 : }
1812 :
1813 0 : dig->afmt->enabled = enable;
1814 :
1815 0 : DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1816 : enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1817 : }
1818 :
1819 0 : static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1820 : {
1821 : int i;
1822 :
1823 0 : for (i = 0; i < adev->mode_info.num_dig; i++)
1824 0 : adev->mode_info.afmt[i] = NULL;
1825 :
1826 : /* DCE11 has audio blocks tied to DIG encoders */
1827 0 : for (i = 0; i < adev->mode_info.num_dig; i++) {
1828 0 : adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1829 0 : if (adev->mode_info.afmt[i]) {
1830 0 : adev->mode_info.afmt[i]->offset = dig_offsets[i];
1831 0 : adev->mode_info.afmt[i]->id = i;
1832 : } else {
1833 : int j;
1834 0 : for (j = 0; j < i; j++) {
1835 0 : kfree(adev->mode_info.afmt[j]);
1836 0 : adev->mode_info.afmt[j] = NULL;
1837 : }
1838 : return -ENOMEM;
1839 : }
1840 : }
1841 : return 0;
1842 : }
1843 :
1844 : static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1845 : {
1846 : int i;
1847 :
1848 0 : for (i = 0; i < adev->mode_info.num_dig; i++) {
1849 0 : kfree(adev->mode_info.afmt[i]);
1850 0 : adev->mode_info.afmt[i] = NULL;
1851 : }
1852 : }
1853 :
1854 : static const u32 vga_control_regs[6] =
1855 : {
1856 : mmD1VGA_CONTROL,
1857 : mmD2VGA_CONTROL,
1858 : mmD3VGA_CONTROL,
1859 : mmD4VGA_CONTROL,
1860 : mmD5VGA_CONTROL,
1861 : mmD6VGA_CONTROL,
1862 : };
1863 :
1864 0 : static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1865 : {
1866 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1867 0 : struct drm_device *dev = crtc->dev;
1868 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1869 : u32 vga_control;
1870 :
1871 0 : vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1872 0 : if (enable)
1873 0 : WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1874 : else
1875 0 : WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1876 0 : }
1877 :
1878 0 : static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1879 : {
1880 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1881 0 : struct drm_device *dev = crtc->dev;
1882 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1883 :
1884 0 : if (enable)
1885 0 : WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1886 : else
1887 0 : WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1888 0 : }
1889 :
1890 0 : static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1891 : struct drm_framebuffer *fb,
1892 : int x, int y, int atomic)
1893 : {
1894 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1895 0 : struct drm_device *dev = crtc->dev;
1896 0 : struct amdgpu_device *adev = drm_to_adev(dev);
1897 : struct drm_framebuffer *target_fb;
1898 : struct drm_gem_object *obj;
1899 : struct amdgpu_bo *abo;
1900 : uint64_t fb_location, tiling_flags;
1901 : uint32_t fb_format, fb_pitch_pixels;
1902 0 : u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1903 : u32 pipe_config;
1904 : u32 tmp, viewport_w, viewport_h;
1905 : int r;
1906 0 : bool bypass_lut = false;
1907 :
1908 : /* no fb bound */
1909 0 : if (!atomic && !crtc->primary->fb) {
1910 0 : DRM_DEBUG_KMS("No FB bound\n");
1911 0 : return 0;
1912 : }
1913 :
1914 0 : if (atomic)
1915 : target_fb = fb;
1916 : else
1917 0 : target_fb = crtc->primary->fb;
1918 :
1919 : /* If atomic, assume fb object is pinned & idle & fenced and
1920 : * just update base pointers
1921 : */
1922 0 : obj = target_fb->obj[0];
1923 0 : abo = gem_to_amdgpu_bo(obj);
1924 0 : r = amdgpu_bo_reserve(abo, false);
1925 0 : if (unlikely(r != 0))
1926 : return r;
1927 :
1928 0 : if (!atomic) {
1929 0 : r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1930 0 : if (unlikely(r != 0)) {
1931 0 : amdgpu_bo_unreserve(abo);
1932 0 : return -EINVAL;
1933 : }
1934 : }
1935 0 : fb_location = amdgpu_bo_gpu_offset(abo);
1936 :
1937 0 : amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1938 0 : amdgpu_bo_unreserve(abo);
1939 :
1940 0 : pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1941 :
1942 0 : switch (target_fb->format->format) {
1943 : case DRM_FORMAT_C8:
1944 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1945 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1946 : break;
1947 : case DRM_FORMAT_XRGB4444:
1948 : case DRM_FORMAT_ARGB4444:
1949 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1950 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1951 : #ifdef __BIG_ENDIAN
1952 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 : ENDIAN_8IN16);
1954 : #endif
1955 0 : break;
1956 : case DRM_FORMAT_XRGB1555:
1957 : case DRM_FORMAT_ARGB1555:
1958 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1959 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1960 : #ifdef __BIG_ENDIAN
1961 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1962 : ENDIAN_8IN16);
1963 : #endif
1964 0 : break;
1965 : case DRM_FORMAT_BGRX5551:
1966 : case DRM_FORMAT_BGRA5551:
1967 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1968 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1969 : #ifdef __BIG_ENDIAN
1970 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1971 : ENDIAN_8IN16);
1972 : #endif
1973 0 : break;
1974 : case DRM_FORMAT_RGB565:
1975 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1976 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1977 : #ifdef __BIG_ENDIAN
1978 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1979 : ENDIAN_8IN16);
1980 : #endif
1981 0 : break;
1982 : case DRM_FORMAT_XRGB8888:
1983 : case DRM_FORMAT_ARGB8888:
1984 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1985 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1986 : #ifdef __BIG_ENDIAN
1987 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1988 : ENDIAN_8IN32);
1989 : #endif
1990 0 : break;
1991 : case DRM_FORMAT_XRGB2101010:
1992 : case DRM_FORMAT_ARGB2101010:
1993 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1994 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1995 : #ifdef __BIG_ENDIAN
1996 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1997 : ENDIAN_8IN32);
1998 : #endif
1999 : /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2000 0 : bypass_lut = true;
2001 0 : break;
2002 : case DRM_FORMAT_BGRX1010102:
2003 : case DRM_FORMAT_BGRA1010102:
2004 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2005 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2006 : #ifdef __BIG_ENDIAN
2007 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2008 : ENDIAN_8IN32);
2009 : #endif
2010 : /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2011 0 : bypass_lut = true;
2012 0 : break;
2013 : case DRM_FORMAT_XBGR8888:
2014 : case DRM_FORMAT_ABGR8888:
2015 0 : fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2016 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2017 0 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2018 0 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2019 : #ifdef __BIG_ENDIAN
2020 : fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2021 : ENDIAN_8IN32);
2022 : #endif
2023 0 : break;
2024 : default:
2025 0 : DRM_ERROR("Unsupported screen format %p4cc\n",
2026 : &target_fb->format->format);
2027 0 : return -EINVAL;
2028 : }
2029 :
2030 0 : if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2031 : unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2032 :
2033 0 : bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2034 0 : bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2035 0 : mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2036 0 : tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2037 0 : num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2038 :
2039 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2040 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2041 : ARRAY_2D_TILED_THIN1);
2042 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2043 : tile_split);
2044 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2045 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2046 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2047 : mtaspect);
2048 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2049 : ADDR_SURF_MICRO_TILING_DISPLAY);
2050 0 : } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2051 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2052 : ARRAY_1D_TILED_THIN1);
2053 : }
2054 :
2055 0 : fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2056 : pipe_config);
2057 :
2058 0 : dce_v11_0_vga_enable(crtc, false);
2059 :
2060 : /* Make sure surface address is updated at vertical blank rather than
2061 : * horizontal blank
2062 : */
2063 0 : tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2064 0 : tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2065 : GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2066 0 : WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2067 :
2068 0 : WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2069 : upper_32_bits(fb_location));
2070 0 : WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2071 : upper_32_bits(fb_location));
2072 0 : WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2073 : (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2074 0 : WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2075 : (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2076 0 : WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2077 0 : WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2078 :
2079 : /*
2080 : * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2081 : * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2082 : * retain the full precision throughout the pipeline.
2083 : */
2084 0 : tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2085 0 : if (bypass_lut)
2086 0 : tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2087 : else
2088 0 : tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2089 0 : WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2090 :
2091 0 : if (bypass_lut)
2092 0 : DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2093 :
2094 0 : WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2095 0 : WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2096 0 : WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2097 0 : WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2098 0 : WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2099 0 : WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2100 :
2101 0 : fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2102 0 : WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2103 :
2104 0 : dce_v11_0_grph_enable(crtc, true);
2105 :
2106 0 : WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2107 : target_fb->height);
2108 :
2109 0 : x &= ~3;
2110 0 : y &= ~1;
2111 0 : WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2112 : (x << 16) | y);
2113 0 : viewport_w = crtc->mode.hdisplay;
2114 0 : viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2115 0 : WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2116 : (viewport_w << 16) | viewport_h);
2117 :
2118 : /* set pageflip to happen anywhere in vblank interval */
2119 0 : WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2120 :
2121 0 : if (!atomic && fb && fb != crtc->primary->fb) {
2122 0 : abo = gem_to_amdgpu_bo(fb->obj[0]);
2123 0 : r = amdgpu_bo_reserve(abo, true);
2124 0 : if (unlikely(r != 0))
2125 : return r;
2126 0 : amdgpu_bo_unpin(abo);
2127 : amdgpu_bo_unreserve(abo);
2128 : }
2129 :
2130 : /* Bytes per pixel may have changed */
2131 0 : dce_v11_0_bandwidth_update(adev);
2132 :
2133 0 : return 0;
2134 : }
2135 :
2136 0 : static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2137 : struct drm_display_mode *mode)
2138 : {
2139 0 : struct drm_device *dev = crtc->dev;
2140 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2141 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142 : u32 tmp;
2143 :
2144 0 : tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2145 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2146 0 : tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2147 : else
2148 0 : tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2149 0 : WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2150 0 : }
2151 :
2152 0 : static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2153 : {
2154 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2155 0 : struct drm_device *dev = crtc->dev;
2156 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2157 : u16 *r, *g, *b;
2158 : int i;
2159 : u32 tmp;
2160 :
2161 0 : DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2162 :
2163 0 : tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2164 0 : tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2165 0 : WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2166 :
2167 0 : tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2168 0 : tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2169 0 : WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170 :
2171 0 : tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2172 0 : tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2173 0 : WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174 :
2175 0 : WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2176 :
2177 0 : WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2178 0 : WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2179 0 : WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2180 :
2181 0 : WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2182 0 : WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2183 0 : WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2184 :
2185 0 : WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2186 0 : WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2187 :
2188 0 : WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2189 0 : r = crtc->gamma_store;
2190 0 : g = r + crtc->gamma_size;
2191 0 : b = g + crtc->gamma_size;
2192 0 : for (i = 0; i < 256; i++) {
2193 0 : WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2194 : ((*r++ & 0xffc0) << 14) |
2195 : ((*g++ & 0xffc0) << 4) |
2196 : (*b++ >> 6));
2197 : }
2198 :
2199 0 : tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2200 0 : tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2201 0 : tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2202 0 : tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2203 0 : WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2204 :
2205 0 : tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2206 0 : tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2207 0 : WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2208 :
2209 0 : tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2210 0 : tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2211 0 : WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2212 :
2213 0 : tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2214 0 : tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2215 0 : WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2216 :
2217 : /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2218 0 : WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2219 : /* XXX this only needs to be programmed once per crtc at startup,
2220 : * not sure where the best place for it is
2221 : */
2222 0 : tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2223 0 : tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2224 0 : WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2225 0 : }
2226 :
2227 0 : static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2228 : {
2229 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2230 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2231 :
2232 0 : switch (amdgpu_encoder->encoder_id) {
2233 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2234 0 : if (dig->linkb)
2235 : return 1;
2236 : else
2237 0 : return 0;
2238 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2239 0 : if (dig->linkb)
2240 : return 3;
2241 : else
2242 0 : return 2;
2243 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2244 0 : if (dig->linkb)
2245 : return 5;
2246 : else
2247 0 : return 4;
2248 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2249 : return 6;
2250 : default:
2251 0 : DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2252 0 : return 0;
2253 : }
2254 : }
2255 :
2256 : /**
2257 : * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2258 : *
2259 : * @crtc: drm crtc
2260 : *
2261 : * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2262 : * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2263 : * monitors a dedicated PPLL must be used. If a particular board has
2264 : * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2265 : * as there is no need to program the PLL itself. If we are not able to
2266 : * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2267 : * avoid messing up an existing monitor.
2268 : *
2269 : * Asic specific PLL information
2270 : *
2271 : * DCE 10.x
2272 : * Tonga
2273 : * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2274 : * CI
2275 : * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2276 : *
2277 : */
2278 0 : static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2279 : {
2280 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2281 0 : struct drm_device *dev = crtc->dev;
2282 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2283 : u32 pll_in_use;
2284 : int pll;
2285 :
2286 0 : if ((adev->asic_type == CHIP_POLARIS10) ||
2287 : (adev->asic_type == CHIP_POLARIS11) ||
2288 0 : (adev->asic_type == CHIP_POLARIS12) ||
2289 : (adev->asic_type == CHIP_VEGAM)) {
2290 0 : struct amdgpu_encoder *amdgpu_encoder =
2291 0 : to_amdgpu_encoder(amdgpu_crtc->encoder);
2292 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2293 :
2294 0 : if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2295 : return ATOM_DP_DTO;
2296 :
2297 0 : switch (amdgpu_encoder->encoder_id) {
2298 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2299 0 : if (dig->linkb)
2300 : return ATOM_COMBOPHY_PLL1;
2301 : else
2302 0 : return ATOM_COMBOPHY_PLL0;
2303 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2304 0 : if (dig->linkb)
2305 : return ATOM_COMBOPHY_PLL3;
2306 : else
2307 0 : return ATOM_COMBOPHY_PLL2;
2308 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2309 0 : if (dig->linkb)
2310 : return ATOM_COMBOPHY_PLL5;
2311 : else
2312 0 : return ATOM_COMBOPHY_PLL4;
2313 : default:
2314 0 : DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2315 0 : return ATOM_PPLL_INVALID;
2316 : }
2317 : }
2318 :
2319 0 : if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2320 0 : if (adev->clock.dp_extclk)
2321 : /* skip PPLL programming if using ext clock */
2322 : return ATOM_PPLL_INVALID;
2323 : else {
2324 : /* use the same PPLL for all DP monitors */
2325 0 : pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2326 0 : if (pll != ATOM_PPLL_INVALID)
2327 0 : return pll;
2328 : }
2329 : } else {
2330 : /* use the same PPLL for all monitors with the same clock */
2331 0 : pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2332 0 : if (pll != ATOM_PPLL_INVALID)
2333 0 : return pll;
2334 : }
2335 :
2336 : /* XXX need to determine what plls are available on each DCE11 part */
2337 0 : pll_in_use = amdgpu_pll_get_use_mask(crtc);
2338 0 : if (adev->flags & AMD_IS_APU) {
2339 0 : if (!(pll_in_use & (1 << ATOM_PPLL1)))
2340 : return ATOM_PPLL1;
2341 0 : if (!(pll_in_use & (1 << ATOM_PPLL0)))
2342 : return ATOM_PPLL0;
2343 0 : DRM_ERROR("unable to allocate a PPLL\n");
2344 0 : return ATOM_PPLL_INVALID;
2345 : } else {
2346 0 : if (!(pll_in_use & (1 << ATOM_PPLL2)))
2347 : return ATOM_PPLL2;
2348 0 : if (!(pll_in_use & (1 << ATOM_PPLL1)))
2349 : return ATOM_PPLL1;
2350 0 : if (!(pll_in_use & (1 << ATOM_PPLL0)))
2351 : return ATOM_PPLL0;
2352 0 : DRM_ERROR("unable to allocate a PPLL\n");
2353 0 : return ATOM_PPLL_INVALID;
2354 : }
2355 : return ATOM_PPLL_INVALID;
2356 : }
2357 :
2358 0 : static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2359 : {
2360 0 : struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2361 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2362 : uint32_t cur_lock;
2363 :
2364 0 : cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2365 0 : if (lock)
2366 0 : cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2367 : else
2368 0 : cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2369 0 : WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2370 0 : }
2371 :
2372 0 : static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2373 : {
2374 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2375 0 : struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2376 : u32 tmp;
2377 :
2378 0 : tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2379 0 : tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2380 0 : WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2381 0 : }
2382 :
2383 0 : static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2384 : {
2385 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386 0 : struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2387 : u32 tmp;
2388 :
2389 0 : WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2390 : upper_32_bits(amdgpu_crtc->cursor_addr));
2391 0 : WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2392 : lower_32_bits(amdgpu_crtc->cursor_addr));
2393 :
2394 0 : tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2395 0 : tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2396 0 : tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2397 0 : WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2398 0 : }
2399 :
2400 0 : static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2401 : int x, int y)
2402 : {
2403 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2404 0 : struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2405 0 : int xorigin = 0, yorigin = 0;
2406 :
2407 0 : amdgpu_crtc->cursor_x = x;
2408 0 : amdgpu_crtc->cursor_y = y;
2409 :
2410 : /* avivo cursor are offset into the total surface */
2411 0 : x += crtc->x;
2412 0 : y += crtc->y;
2413 0 : DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2414 :
2415 0 : if (x < 0) {
2416 0 : xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2417 0 : x = 0;
2418 : }
2419 0 : if (y < 0) {
2420 0 : yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2421 0 : y = 0;
2422 : }
2423 :
2424 0 : WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2425 0 : WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2426 0 : WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2427 : ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2428 :
2429 0 : return 0;
2430 : }
2431 :
2432 0 : static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2433 : int x, int y)
2434 : {
2435 : int ret;
2436 :
2437 0 : dce_v11_0_lock_cursor(crtc, true);
2438 0 : ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2439 0 : dce_v11_0_lock_cursor(crtc, false);
2440 :
2441 0 : return ret;
2442 : }
2443 :
2444 0 : static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2445 : struct drm_file *file_priv,
2446 : uint32_t handle,
2447 : uint32_t width,
2448 : uint32_t height,
2449 : int32_t hot_x,
2450 : int32_t hot_y)
2451 : {
2452 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2453 : struct drm_gem_object *obj;
2454 : struct amdgpu_bo *aobj;
2455 : int ret;
2456 :
2457 0 : if (!handle) {
2458 : /* turn off cursor */
2459 0 : dce_v11_0_hide_cursor(crtc);
2460 0 : obj = NULL;
2461 0 : goto unpin;
2462 : }
2463 :
2464 0 : if ((width > amdgpu_crtc->max_cursor_width) ||
2465 0 : (height > amdgpu_crtc->max_cursor_height)) {
2466 0 : DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2467 0 : return -EINVAL;
2468 : }
2469 :
2470 0 : obj = drm_gem_object_lookup(file_priv, handle);
2471 0 : if (!obj) {
2472 0 : DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2473 0 : return -ENOENT;
2474 : }
2475 :
2476 0 : aobj = gem_to_amdgpu_bo(obj);
2477 0 : ret = amdgpu_bo_reserve(aobj, false);
2478 0 : if (ret != 0) {
2479 0 : drm_gem_object_put(obj);
2480 0 : return ret;
2481 : }
2482 :
2483 0 : ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2484 0 : amdgpu_bo_unreserve(aobj);
2485 0 : if (ret) {
2486 0 : DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2487 0 : drm_gem_object_put(obj);
2488 0 : return ret;
2489 : }
2490 0 : amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2491 :
2492 0 : dce_v11_0_lock_cursor(crtc, true);
2493 :
2494 0 : if (width != amdgpu_crtc->cursor_width ||
2495 0 : height != amdgpu_crtc->cursor_height ||
2496 0 : hot_x != amdgpu_crtc->cursor_hot_x ||
2497 0 : hot_y != amdgpu_crtc->cursor_hot_y) {
2498 : int x, y;
2499 :
2500 0 : x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2501 0 : y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2502 :
2503 0 : dce_v11_0_cursor_move_locked(crtc, x, y);
2504 :
2505 0 : amdgpu_crtc->cursor_width = width;
2506 0 : amdgpu_crtc->cursor_height = height;
2507 0 : amdgpu_crtc->cursor_hot_x = hot_x;
2508 0 : amdgpu_crtc->cursor_hot_y = hot_y;
2509 : }
2510 :
2511 0 : dce_v11_0_show_cursor(crtc);
2512 0 : dce_v11_0_lock_cursor(crtc, false);
2513 :
2514 : unpin:
2515 0 : if (amdgpu_crtc->cursor_bo) {
2516 0 : struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2517 0 : ret = amdgpu_bo_reserve(aobj, true);
2518 0 : if (likely(ret == 0)) {
2519 0 : amdgpu_bo_unpin(aobj);
2520 : amdgpu_bo_unreserve(aobj);
2521 : }
2522 0 : drm_gem_object_put(amdgpu_crtc->cursor_bo);
2523 : }
2524 :
2525 0 : amdgpu_crtc->cursor_bo = obj;
2526 0 : return 0;
2527 : }
2528 :
2529 0 : static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2530 : {
2531 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2532 :
2533 0 : if (amdgpu_crtc->cursor_bo) {
2534 0 : dce_v11_0_lock_cursor(crtc, true);
2535 :
2536 0 : dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2537 : amdgpu_crtc->cursor_y);
2538 :
2539 0 : dce_v11_0_show_cursor(crtc);
2540 :
2541 0 : dce_v11_0_lock_cursor(crtc, false);
2542 : }
2543 0 : }
2544 :
2545 0 : static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2546 : u16 *blue, uint32_t size,
2547 : struct drm_modeset_acquire_ctx *ctx)
2548 : {
2549 0 : dce_v11_0_crtc_load_lut(crtc);
2550 :
2551 0 : return 0;
2552 : }
2553 :
2554 0 : static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2555 : {
2556 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2557 :
2558 0 : drm_crtc_cleanup(crtc);
2559 0 : kfree(amdgpu_crtc);
2560 0 : }
2561 :
2562 : static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2563 : .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2564 : .cursor_move = dce_v11_0_crtc_cursor_move,
2565 : .gamma_set = dce_v11_0_crtc_gamma_set,
2566 : .set_config = amdgpu_display_crtc_set_config,
2567 : .destroy = dce_v11_0_crtc_destroy,
2568 : .page_flip_target = amdgpu_display_crtc_page_flip_target,
2569 : .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2570 : .enable_vblank = amdgpu_enable_vblank_kms,
2571 : .disable_vblank = amdgpu_disable_vblank_kms,
2572 : .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2573 : };
2574 :
2575 0 : static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2576 : {
2577 0 : struct drm_device *dev = crtc->dev;
2578 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2579 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2580 : unsigned type;
2581 :
2582 0 : switch (mode) {
2583 : case DRM_MODE_DPMS_ON:
2584 0 : amdgpu_crtc->enabled = true;
2585 0 : amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2586 0 : dce_v11_0_vga_enable(crtc, true);
2587 0 : amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2588 0 : dce_v11_0_vga_enable(crtc, false);
2589 : /* Make sure VBLANK and PFLIP interrupts are still enabled */
2590 0 : type = amdgpu_display_crtc_idx_to_irq_type(adev,
2591 : amdgpu_crtc->crtc_id);
2592 0 : amdgpu_irq_update(adev, &adev->crtc_irq, type);
2593 0 : amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2594 0 : drm_crtc_vblank_on(crtc);
2595 0 : dce_v11_0_crtc_load_lut(crtc);
2596 0 : break;
2597 : case DRM_MODE_DPMS_STANDBY:
2598 : case DRM_MODE_DPMS_SUSPEND:
2599 : case DRM_MODE_DPMS_OFF:
2600 0 : drm_crtc_vblank_off(crtc);
2601 0 : if (amdgpu_crtc->enabled) {
2602 0 : dce_v11_0_vga_enable(crtc, true);
2603 0 : amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2604 0 : dce_v11_0_vga_enable(crtc, false);
2605 : }
2606 0 : amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2607 0 : amdgpu_crtc->enabled = false;
2608 0 : break;
2609 : }
2610 : /* adjust pm to dpms */
2611 0 : amdgpu_dpm_compute_clocks(adev);
2612 0 : }
2613 :
2614 0 : static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2615 : {
2616 : /* disable crtc pair power gating before programming */
2617 0 : amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2618 0 : amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2619 0 : dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2620 0 : }
2621 :
2622 0 : static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2623 : {
2624 0 : dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2625 0 : amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2626 0 : }
2627 :
2628 0 : static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2629 : {
2630 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2631 0 : struct drm_device *dev = crtc->dev;
2632 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2633 : struct amdgpu_atom_ss ss;
2634 : int i;
2635 :
2636 0 : dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2637 0 : if (crtc->primary->fb) {
2638 : int r;
2639 : struct amdgpu_bo *abo;
2640 :
2641 0 : abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2642 0 : r = amdgpu_bo_reserve(abo, true);
2643 0 : if (unlikely(r))
2644 0 : DRM_ERROR("failed to reserve abo before unpin\n");
2645 : else {
2646 0 : amdgpu_bo_unpin(abo);
2647 : amdgpu_bo_unreserve(abo);
2648 : }
2649 : }
2650 : /* disable the GRPH */
2651 0 : dce_v11_0_grph_enable(crtc, false);
2652 :
2653 0 : amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2654 :
2655 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
2656 0 : if (adev->mode_info.crtcs[i] &&
2657 0 : adev->mode_info.crtcs[i]->enabled &&
2658 0 : i != amdgpu_crtc->crtc_id &&
2659 0 : amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2660 : /* one other crtc is using this pll don't turn
2661 : * off the pll
2662 : */
2663 : goto done;
2664 : }
2665 : }
2666 :
2667 0 : switch (amdgpu_crtc->pll_id) {
2668 : case ATOM_PPLL0:
2669 : case ATOM_PPLL1:
2670 : case ATOM_PPLL2:
2671 : /* disable the ppll */
2672 0 : amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2673 : 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2674 0 : break;
2675 : case ATOM_COMBOPHY_PLL0:
2676 : case ATOM_COMBOPHY_PLL1:
2677 : case ATOM_COMBOPHY_PLL2:
2678 : case ATOM_COMBOPHY_PLL3:
2679 : case ATOM_COMBOPHY_PLL4:
2680 : case ATOM_COMBOPHY_PLL5:
2681 : /* disable the ppll */
2682 0 : amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2683 : 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2684 0 : break;
2685 : default:
2686 : break;
2687 : }
2688 : done:
2689 0 : amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2690 0 : amdgpu_crtc->adjusted_clock = 0;
2691 0 : amdgpu_crtc->encoder = NULL;
2692 0 : amdgpu_crtc->connector = NULL;
2693 0 : }
2694 :
2695 0 : static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2696 : struct drm_display_mode *mode,
2697 : struct drm_display_mode *adjusted_mode,
2698 : int x, int y, struct drm_framebuffer *old_fb)
2699 : {
2700 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2701 0 : struct drm_device *dev = crtc->dev;
2702 0 : struct amdgpu_device *adev = drm_to_adev(dev);
2703 :
2704 0 : if (!amdgpu_crtc->adjusted_clock)
2705 : return -EINVAL;
2706 :
2707 0 : if ((adev->asic_type == CHIP_POLARIS10) ||
2708 : (adev->asic_type == CHIP_POLARIS11) ||
2709 0 : (adev->asic_type == CHIP_POLARIS12) ||
2710 : (adev->asic_type == CHIP_VEGAM)) {
2711 0 : struct amdgpu_encoder *amdgpu_encoder =
2712 0 : to_amdgpu_encoder(amdgpu_crtc->encoder);
2713 0 : int encoder_mode =
2714 : amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2715 :
2716 : /* SetPixelClock calculates the plls and ss values now */
2717 0 : amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2718 0 : amdgpu_crtc->pll_id,
2719 : encoder_mode, amdgpu_encoder->encoder_id,
2720 0 : adjusted_mode->clock, 0, 0, 0, 0,
2721 0 : amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2722 : } else {
2723 0 : amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2724 : }
2725 0 : amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2726 0 : dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2727 0 : amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2728 0 : amdgpu_atombios_crtc_scaler_setup(crtc);
2729 0 : dce_v11_0_cursor_reset(crtc);
2730 : /* update the hw version fpr dpm */
2731 0 : amdgpu_crtc->hw_mode = *adjusted_mode;
2732 :
2733 0 : return 0;
2734 : }
2735 :
2736 0 : static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2737 : const struct drm_display_mode *mode,
2738 : struct drm_display_mode *adjusted_mode)
2739 : {
2740 0 : struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2741 0 : struct drm_device *dev = crtc->dev;
2742 : struct drm_encoder *encoder;
2743 :
2744 : /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2745 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2746 0 : if (encoder->crtc == crtc) {
2747 0 : amdgpu_crtc->encoder = encoder;
2748 0 : amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2749 0 : break;
2750 : }
2751 : }
2752 0 : if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2753 0 : amdgpu_crtc->encoder = NULL;
2754 0 : amdgpu_crtc->connector = NULL;
2755 0 : return false;
2756 : }
2757 0 : if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2758 : return false;
2759 0 : if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2760 : return false;
2761 : /* pick pll */
2762 0 : amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2763 : /* if we can't get a PPLL for a non-DP encoder, fail */
2764 0 : if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2765 0 : !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2766 : return false;
2767 :
2768 : return true;
2769 : }
2770 :
2771 0 : static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2772 : struct drm_framebuffer *old_fb)
2773 : {
2774 0 : return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2775 : }
2776 :
2777 0 : static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2778 : struct drm_framebuffer *fb,
2779 : int x, int y, enum mode_set_atomic state)
2780 : {
2781 0 : return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2782 : }
2783 :
2784 : static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2785 : .dpms = dce_v11_0_crtc_dpms,
2786 : .mode_fixup = dce_v11_0_crtc_mode_fixup,
2787 : .mode_set = dce_v11_0_crtc_mode_set,
2788 : .mode_set_base = dce_v11_0_crtc_set_base,
2789 : .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2790 : .prepare = dce_v11_0_crtc_prepare,
2791 : .commit = dce_v11_0_crtc_commit,
2792 : .disable = dce_v11_0_crtc_disable,
2793 : .get_scanout_position = amdgpu_crtc_get_scanout_position,
2794 : };
2795 :
2796 0 : static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2797 : {
2798 : struct amdgpu_crtc *amdgpu_crtc;
2799 :
2800 0 : amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2801 : (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2802 0 : if (amdgpu_crtc == NULL)
2803 : return -ENOMEM;
2804 :
2805 0 : drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2806 :
2807 0 : drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2808 0 : amdgpu_crtc->crtc_id = index;
2809 0 : adev->mode_info.crtcs[index] = amdgpu_crtc;
2810 :
2811 0 : amdgpu_crtc->max_cursor_width = 128;
2812 0 : amdgpu_crtc->max_cursor_height = 128;
2813 0 : adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2814 0 : adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2815 :
2816 0 : switch (amdgpu_crtc->crtc_id) {
2817 : case 0:
2818 : default:
2819 0 : amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2820 0 : break;
2821 : case 1:
2822 0 : amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2823 0 : break;
2824 : case 2:
2825 0 : amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2826 0 : break;
2827 : case 3:
2828 0 : amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2829 0 : break;
2830 : case 4:
2831 0 : amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2832 0 : break;
2833 : case 5:
2834 0 : amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2835 0 : break;
2836 : }
2837 :
2838 0 : amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2839 0 : amdgpu_crtc->adjusted_clock = 0;
2840 0 : amdgpu_crtc->encoder = NULL;
2841 0 : amdgpu_crtc->connector = NULL;
2842 0 : drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2843 :
2844 0 : return 0;
2845 : }
2846 :
2847 0 : static int dce_v11_0_early_init(void *handle)
2848 : {
2849 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2850 :
2851 0 : adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2852 0 : adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2853 :
2854 0 : dce_v11_0_set_display_funcs(adev);
2855 :
2856 0 : adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2857 :
2858 0 : switch (adev->asic_type) {
2859 : case CHIP_CARRIZO:
2860 0 : adev->mode_info.num_hpd = 6;
2861 0 : adev->mode_info.num_dig = 9;
2862 0 : break;
2863 : case CHIP_STONEY:
2864 0 : adev->mode_info.num_hpd = 6;
2865 0 : adev->mode_info.num_dig = 9;
2866 0 : break;
2867 : case CHIP_POLARIS10:
2868 : case CHIP_VEGAM:
2869 0 : adev->mode_info.num_hpd = 6;
2870 0 : adev->mode_info.num_dig = 6;
2871 0 : break;
2872 : case CHIP_POLARIS11:
2873 : case CHIP_POLARIS12:
2874 0 : adev->mode_info.num_hpd = 5;
2875 0 : adev->mode_info.num_dig = 5;
2876 0 : break;
2877 : default:
2878 : /* FIXME: not supported yet */
2879 : return -EINVAL;
2880 : }
2881 :
2882 0 : dce_v11_0_set_irq_funcs(adev);
2883 :
2884 0 : return 0;
2885 : }
2886 :
2887 0 : static int dce_v11_0_sw_init(void *handle)
2888 : {
2889 : int r, i;
2890 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2891 :
2892 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
2893 0 : r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2894 0 : if (r)
2895 : return r;
2896 : }
2897 :
2898 0 : for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2899 0 : r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2900 0 : if (r)
2901 : return r;
2902 : }
2903 :
2904 : /* HPD hotplug */
2905 0 : r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2906 0 : if (r)
2907 : return r;
2908 :
2909 0 : adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2910 :
2911 0 : adev_to_drm(adev)->mode_config.async_page_flip = true;
2912 :
2913 0 : adev_to_drm(adev)->mode_config.max_width = 16384;
2914 0 : adev_to_drm(adev)->mode_config.max_height = 16384;
2915 :
2916 0 : adev_to_drm(adev)->mode_config.preferred_depth = 24;
2917 0 : adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2918 :
2919 0 : adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2920 :
2921 0 : adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
2922 :
2923 0 : r = amdgpu_display_modeset_create_props(adev);
2924 0 : if (r)
2925 : return r;
2926 :
2927 0 : adev_to_drm(adev)->mode_config.max_width = 16384;
2928 0 : adev_to_drm(adev)->mode_config.max_height = 16384;
2929 :
2930 :
2931 : /* allocate crtcs */
2932 0 : for (i = 0; i < adev->mode_info.num_crtc; i++) {
2933 0 : r = dce_v11_0_crtc_init(adev, i);
2934 0 : if (r)
2935 : return r;
2936 : }
2937 :
2938 0 : if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2939 0 : amdgpu_display_print_display_setup(adev_to_drm(adev));
2940 : else
2941 : return -EINVAL;
2942 :
2943 : /* setup afmt */
2944 0 : r = dce_v11_0_afmt_init(adev);
2945 0 : if (r)
2946 : return r;
2947 :
2948 0 : r = dce_v11_0_audio_init(adev);
2949 0 : if (r)
2950 : return r;
2951 :
2952 0 : drm_kms_helper_poll_init(adev_to_drm(adev));
2953 :
2954 0 : adev->mode_info.mode_config_initialized = true;
2955 0 : return 0;
2956 : }
2957 :
2958 0 : static int dce_v11_0_sw_fini(void *handle)
2959 : {
2960 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2961 :
2962 0 : kfree(adev->mode_info.bios_hardcoded_edid);
2963 :
2964 0 : drm_kms_helper_poll_fini(adev_to_drm(adev));
2965 :
2966 0 : dce_v11_0_audio_fini(adev);
2967 :
2968 0 : dce_v11_0_afmt_fini(adev);
2969 :
2970 0 : drm_mode_config_cleanup(adev_to_drm(adev));
2971 0 : adev->mode_info.mode_config_initialized = false;
2972 :
2973 0 : return 0;
2974 : }
2975 :
2976 0 : static int dce_v11_0_hw_init(void *handle)
2977 : {
2978 : int i;
2979 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2980 :
2981 0 : dce_v11_0_init_golden_registers(adev);
2982 :
2983 : /* disable vga render */
2984 0 : dce_v11_0_set_vga_render_state(adev, false);
2985 : /* init dig PHYs, disp eng pll */
2986 0 : amdgpu_atombios_crtc_powergate_init(adev);
2987 0 : amdgpu_atombios_encoder_init_dig(adev);
2988 0 : if ((adev->asic_type == CHIP_POLARIS10) ||
2989 : (adev->asic_type == CHIP_POLARIS11) ||
2990 0 : (adev->asic_type == CHIP_POLARIS12) ||
2991 : (adev->asic_type == CHIP_VEGAM)) {
2992 0 : amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2993 : DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2994 0 : amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2995 : DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
2996 : } else {
2997 0 : amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2998 : }
2999 :
3000 : /* initialize hpd */
3001 0 : dce_v11_0_hpd_init(adev);
3002 :
3003 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3004 0 : dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3005 : }
3006 :
3007 0 : dce_v11_0_pageflip_interrupt_init(adev);
3008 :
3009 0 : return 0;
3010 : }
3011 :
3012 0 : static int dce_v11_0_hw_fini(void *handle)
3013 : {
3014 : int i;
3015 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3016 :
3017 0 : dce_v11_0_hpd_fini(adev);
3018 :
3019 0 : for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3020 0 : dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3021 : }
3022 :
3023 0 : dce_v11_0_pageflip_interrupt_fini(adev);
3024 :
3025 0 : return 0;
3026 : }
3027 :
3028 0 : static int dce_v11_0_suspend(void *handle)
3029 : {
3030 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3031 : int r;
3032 :
3033 0 : r = amdgpu_display_suspend_helper(adev);
3034 0 : if (r)
3035 : return r;
3036 :
3037 0 : adev->mode_info.bl_level =
3038 0 : amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3039 :
3040 0 : return dce_v11_0_hw_fini(handle);
3041 : }
3042 :
3043 0 : static int dce_v11_0_resume(void *handle)
3044 : {
3045 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046 : int ret;
3047 :
3048 0 : amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3049 0 : adev->mode_info.bl_level);
3050 :
3051 0 : ret = dce_v11_0_hw_init(handle);
3052 :
3053 : /* turn on the BL */
3054 0 : if (adev->mode_info.bl_encoder) {
3055 0 : u8 bl_level = amdgpu_display_backlight_get_level(adev,
3056 : adev->mode_info.bl_encoder);
3057 0 : amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3058 : bl_level);
3059 : }
3060 0 : if (ret)
3061 : return ret;
3062 :
3063 0 : return amdgpu_display_resume_helper(adev);
3064 : }
3065 :
3066 0 : static bool dce_v11_0_is_idle(void *handle)
3067 : {
3068 0 : return true;
3069 : }
3070 :
3071 0 : static int dce_v11_0_wait_for_idle(void *handle)
3072 : {
3073 0 : return 0;
3074 : }
3075 :
3076 0 : static int dce_v11_0_soft_reset(void *handle)
3077 : {
3078 0 : u32 srbm_soft_reset = 0, tmp;
3079 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3080 :
3081 0 : if (dce_v11_0_is_display_hung(adev))
3082 0 : srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3083 :
3084 0 : if (srbm_soft_reset) {
3085 0 : tmp = RREG32(mmSRBM_SOFT_RESET);
3086 0 : tmp |= srbm_soft_reset;
3087 0 : dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3088 0 : WREG32(mmSRBM_SOFT_RESET, tmp);
3089 0 : tmp = RREG32(mmSRBM_SOFT_RESET);
3090 :
3091 0 : udelay(50);
3092 :
3093 0 : tmp &= ~srbm_soft_reset;
3094 0 : WREG32(mmSRBM_SOFT_RESET, tmp);
3095 0 : tmp = RREG32(mmSRBM_SOFT_RESET);
3096 :
3097 : /* Wait a little for things to settle down */
3098 : udelay(50);
3099 : }
3100 0 : return 0;
3101 : }
3102 :
3103 0 : static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3104 : int crtc,
3105 : enum amdgpu_interrupt_state state)
3106 : {
3107 : u32 lb_interrupt_mask;
3108 :
3109 0 : if (crtc >= adev->mode_info.num_crtc) {
3110 0 : DRM_DEBUG("invalid crtc %d\n", crtc);
3111 0 : return;
3112 : }
3113 :
3114 0 : switch (state) {
3115 : case AMDGPU_IRQ_STATE_DISABLE:
3116 0 : lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3117 0 : lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3118 : VBLANK_INTERRUPT_MASK, 0);
3119 0 : WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3120 0 : break;
3121 : case AMDGPU_IRQ_STATE_ENABLE:
3122 0 : lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3123 0 : lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3124 : VBLANK_INTERRUPT_MASK, 1);
3125 0 : WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3126 0 : break;
3127 : default:
3128 : break;
3129 : }
3130 : }
3131 :
3132 0 : static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3133 : int crtc,
3134 : enum amdgpu_interrupt_state state)
3135 : {
3136 : u32 lb_interrupt_mask;
3137 :
3138 0 : if (crtc >= adev->mode_info.num_crtc) {
3139 0 : DRM_DEBUG("invalid crtc %d\n", crtc);
3140 0 : return;
3141 : }
3142 :
3143 0 : switch (state) {
3144 : case AMDGPU_IRQ_STATE_DISABLE:
3145 0 : lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3146 0 : lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3147 : VLINE_INTERRUPT_MASK, 0);
3148 0 : WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3149 0 : break;
3150 : case AMDGPU_IRQ_STATE_ENABLE:
3151 0 : lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3152 0 : lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3153 : VLINE_INTERRUPT_MASK, 1);
3154 0 : WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3155 0 : break;
3156 : default:
3157 : break;
3158 : }
3159 : }
3160 :
3161 0 : static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3162 : struct amdgpu_irq_src *source,
3163 : unsigned hpd,
3164 : enum amdgpu_interrupt_state state)
3165 : {
3166 : u32 tmp;
3167 :
3168 0 : if (hpd >= adev->mode_info.num_hpd) {
3169 0 : DRM_DEBUG("invalid hdp %d\n", hpd);
3170 0 : return 0;
3171 : }
3172 :
3173 0 : switch (state) {
3174 : case AMDGPU_IRQ_STATE_DISABLE:
3175 0 : tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3176 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3177 0 : WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3178 0 : break;
3179 : case AMDGPU_IRQ_STATE_ENABLE:
3180 0 : tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3181 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3182 0 : WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3183 0 : break;
3184 : default:
3185 : break;
3186 : }
3187 :
3188 : return 0;
3189 : }
3190 :
3191 0 : static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3192 : struct amdgpu_irq_src *source,
3193 : unsigned type,
3194 : enum amdgpu_interrupt_state state)
3195 : {
3196 0 : switch (type) {
3197 : case AMDGPU_CRTC_IRQ_VBLANK1:
3198 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3199 0 : break;
3200 : case AMDGPU_CRTC_IRQ_VBLANK2:
3201 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3202 0 : break;
3203 : case AMDGPU_CRTC_IRQ_VBLANK3:
3204 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3205 0 : break;
3206 : case AMDGPU_CRTC_IRQ_VBLANK4:
3207 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3208 0 : break;
3209 : case AMDGPU_CRTC_IRQ_VBLANK5:
3210 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3211 0 : break;
3212 : case AMDGPU_CRTC_IRQ_VBLANK6:
3213 0 : dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3214 0 : break;
3215 : case AMDGPU_CRTC_IRQ_VLINE1:
3216 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3217 0 : break;
3218 : case AMDGPU_CRTC_IRQ_VLINE2:
3219 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3220 0 : break;
3221 : case AMDGPU_CRTC_IRQ_VLINE3:
3222 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3223 0 : break;
3224 : case AMDGPU_CRTC_IRQ_VLINE4:
3225 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3226 0 : break;
3227 : case AMDGPU_CRTC_IRQ_VLINE5:
3228 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3229 0 : break;
3230 : case AMDGPU_CRTC_IRQ_VLINE6:
3231 0 : dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3232 0 : break;
3233 : default:
3234 : break;
3235 : }
3236 0 : return 0;
3237 : }
3238 :
3239 0 : static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3240 : struct amdgpu_irq_src *src,
3241 : unsigned type,
3242 : enum amdgpu_interrupt_state state)
3243 : {
3244 : u32 reg;
3245 :
3246 0 : if (type >= adev->mode_info.num_crtc) {
3247 0 : DRM_ERROR("invalid pageflip crtc %d\n", type);
3248 0 : return -EINVAL;
3249 : }
3250 :
3251 0 : reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3252 0 : if (state == AMDGPU_IRQ_STATE_DISABLE)
3253 0 : WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3254 : reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3255 : else
3256 0 : WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3257 : reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3258 :
3259 : return 0;
3260 : }
3261 :
3262 0 : static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3263 : struct amdgpu_irq_src *source,
3264 : struct amdgpu_iv_entry *entry)
3265 : {
3266 : unsigned long flags;
3267 : unsigned crtc_id;
3268 : struct amdgpu_crtc *amdgpu_crtc;
3269 : struct amdgpu_flip_work *works;
3270 :
3271 0 : crtc_id = (entry->src_id - 8) >> 1;
3272 0 : amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3273 :
3274 0 : if (crtc_id >= adev->mode_info.num_crtc) {
3275 0 : DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3276 0 : return -EINVAL;
3277 : }
3278 :
3279 0 : if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3280 : GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3281 0 : WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3282 : GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3283 :
3284 : /* IRQ could occur when in initial stage */
3285 0 : if(amdgpu_crtc == NULL)
3286 : return 0;
3287 :
3288 0 : spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3289 0 : works = amdgpu_crtc->pflip_works;
3290 0 : if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3291 0 : DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3292 : "AMDGPU_FLIP_SUBMITTED(%d)\n",
3293 : amdgpu_crtc->pflip_status,
3294 : AMDGPU_FLIP_SUBMITTED);
3295 0 : spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3296 0 : return 0;
3297 : }
3298 :
3299 : /* page flip completed. clean up */
3300 0 : amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3301 0 : amdgpu_crtc->pflip_works = NULL;
3302 :
3303 : /* wakeup usersapce */
3304 0 : if(works->event)
3305 0 : drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3306 :
3307 0 : spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3308 :
3309 0 : drm_crtc_vblank_put(&amdgpu_crtc->base);
3310 0 : schedule_work(&works->unpin_work);
3311 :
3312 0 : return 0;
3313 : }
3314 :
3315 0 : static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3316 : int hpd)
3317 : {
3318 : u32 tmp;
3319 :
3320 0 : if (hpd >= adev->mode_info.num_hpd) {
3321 0 : DRM_DEBUG("invalid hdp %d\n", hpd);
3322 0 : return;
3323 : }
3324 :
3325 0 : tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3326 0 : tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3327 0 : WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3328 : }
3329 :
3330 0 : static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3331 : int crtc)
3332 : {
3333 : u32 tmp;
3334 :
3335 0 : if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3336 0 : DRM_DEBUG("invalid crtc %d\n", crtc);
3337 0 : return;
3338 : }
3339 :
3340 0 : tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3341 0 : tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3342 0 : WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3343 : }
3344 :
3345 0 : static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3346 : int crtc)
3347 : {
3348 : u32 tmp;
3349 :
3350 0 : if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3351 0 : DRM_DEBUG("invalid crtc %d\n", crtc);
3352 0 : return;
3353 : }
3354 :
3355 0 : tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3356 0 : tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3357 0 : WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3358 : }
3359 :
3360 0 : static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3361 : struct amdgpu_irq_src *source,
3362 : struct amdgpu_iv_entry *entry)
3363 : {
3364 0 : unsigned crtc = entry->src_id - 1;
3365 0 : uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3366 0 : unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3367 : crtc);
3368 :
3369 0 : switch (entry->src_data[0]) {
3370 : case 0: /* vblank */
3371 0 : if (disp_int & interrupt_status_offsets[crtc].vblank)
3372 0 : dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3373 : else
3374 0 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3375 :
3376 0 : if (amdgpu_irq_enabled(adev, source, irq_type)) {
3377 0 : drm_handle_vblank(adev_to_drm(adev), crtc);
3378 : }
3379 0 : DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3380 :
3381 0 : break;
3382 : case 1: /* vline */
3383 0 : if (disp_int & interrupt_status_offsets[crtc].vline)
3384 0 : dce_v11_0_crtc_vline_int_ack(adev, crtc);
3385 : else
3386 0 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3387 :
3388 0 : DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3389 :
3390 0 : break;
3391 : default:
3392 0 : DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3393 0 : break;
3394 : }
3395 :
3396 0 : return 0;
3397 : }
3398 :
3399 0 : static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3400 : struct amdgpu_irq_src *source,
3401 : struct amdgpu_iv_entry *entry)
3402 : {
3403 : uint32_t disp_int, mask;
3404 : unsigned hpd;
3405 :
3406 0 : if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3407 0 : DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3408 0 : return 0;
3409 : }
3410 :
3411 0 : hpd = entry->src_data[0];
3412 0 : disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3413 0 : mask = interrupt_status_offsets[hpd].hpd;
3414 :
3415 0 : if (disp_int & mask) {
3416 0 : dce_v11_0_hpd_int_ack(adev, hpd);
3417 0 : schedule_work(&adev->hotplug_work);
3418 0 : DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3419 : }
3420 :
3421 : return 0;
3422 : }
3423 :
3424 0 : static int dce_v11_0_set_clockgating_state(void *handle,
3425 : enum amd_clockgating_state state)
3426 : {
3427 0 : return 0;
3428 : }
3429 :
3430 0 : static int dce_v11_0_set_powergating_state(void *handle,
3431 : enum amd_powergating_state state)
3432 : {
3433 0 : return 0;
3434 : }
3435 :
3436 : static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3437 : .name = "dce_v11_0",
3438 : .early_init = dce_v11_0_early_init,
3439 : .late_init = NULL,
3440 : .sw_init = dce_v11_0_sw_init,
3441 : .sw_fini = dce_v11_0_sw_fini,
3442 : .hw_init = dce_v11_0_hw_init,
3443 : .hw_fini = dce_v11_0_hw_fini,
3444 : .suspend = dce_v11_0_suspend,
3445 : .resume = dce_v11_0_resume,
3446 : .is_idle = dce_v11_0_is_idle,
3447 : .wait_for_idle = dce_v11_0_wait_for_idle,
3448 : .soft_reset = dce_v11_0_soft_reset,
3449 : .set_clockgating_state = dce_v11_0_set_clockgating_state,
3450 : .set_powergating_state = dce_v11_0_set_powergating_state,
3451 : };
3452 :
3453 : static void
3454 0 : dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3455 : struct drm_display_mode *mode,
3456 : struct drm_display_mode *adjusted_mode)
3457 : {
3458 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3459 :
3460 0 : amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3461 :
3462 : /* need to call this here rather than in prepare() since we need some crtc info */
3463 0 : amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3464 :
3465 : /* set scaler clears this on some chips */
3466 0 : dce_v11_0_set_interleave(encoder->crtc, mode);
3467 :
3468 0 : if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3469 0 : dce_v11_0_afmt_enable(encoder, true);
3470 0 : dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3471 : }
3472 0 : }
3473 :
3474 0 : static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3475 : {
3476 0 : struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3477 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3478 0 : struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3479 :
3480 0 : if ((amdgpu_encoder->active_device &
3481 0 : (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3482 0 : (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3483 : ENCODER_OBJECT_ID_NONE)) {
3484 0 : struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3485 0 : if (dig) {
3486 0 : dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3487 0 : if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3488 0 : dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3489 : }
3490 : }
3491 :
3492 0 : amdgpu_atombios_scratch_regs_lock(adev, true);
3493 :
3494 0 : if (connector) {
3495 0 : struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3496 :
3497 : /* select the clock/data port if it uses a router */
3498 0 : if (amdgpu_connector->router.cd_valid)
3499 0 : amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3500 :
3501 : /* turn eDP panel on for mode set */
3502 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3503 0 : amdgpu_atombios_encoder_set_edp_panel_power(connector,
3504 : ATOM_TRANSMITTER_ACTION_POWER_ON);
3505 : }
3506 :
3507 : /* this is needed for the pll/ss setup to work correctly in some cases */
3508 0 : amdgpu_atombios_encoder_set_crtc_source(encoder);
3509 : /* set up the FMT blocks */
3510 0 : dce_v11_0_program_fmt(encoder);
3511 0 : }
3512 :
3513 0 : static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3514 : {
3515 0 : struct drm_device *dev = encoder->dev;
3516 0 : struct amdgpu_device *adev = drm_to_adev(dev);
3517 :
3518 : /* need to call this here as we need the crtc set up */
3519 0 : amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3520 0 : amdgpu_atombios_scratch_regs_lock(adev, false);
3521 0 : }
3522 :
3523 0 : static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3524 : {
3525 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3526 : struct amdgpu_encoder_atom_dig *dig;
3527 :
3528 0 : amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3529 :
3530 0 : if (amdgpu_atombios_encoder_is_digital(encoder)) {
3531 0 : if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3532 0 : dce_v11_0_afmt_enable(encoder, false);
3533 0 : dig = amdgpu_encoder->enc_priv;
3534 0 : dig->dig_encoder = -1;
3535 : }
3536 0 : amdgpu_encoder->active_device = 0;
3537 0 : }
3538 :
3539 : /* these are handled by the primary encoders */
3540 0 : static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3541 : {
3542 :
3543 0 : }
3544 :
3545 0 : static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3546 : {
3547 :
3548 0 : }
3549 :
3550 : static void
3551 0 : dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3552 : struct drm_display_mode *mode,
3553 : struct drm_display_mode *adjusted_mode)
3554 : {
3555 :
3556 0 : }
3557 :
3558 0 : static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3559 : {
3560 :
3561 0 : }
3562 :
3563 : static void
3564 0 : dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3565 : {
3566 :
3567 0 : }
3568 :
3569 : static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3570 : .dpms = dce_v11_0_ext_dpms,
3571 : .prepare = dce_v11_0_ext_prepare,
3572 : .mode_set = dce_v11_0_ext_mode_set,
3573 : .commit = dce_v11_0_ext_commit,
3574 : .disable = dce_v11_0_ext_disable,
3575 : /* no detect for TMDS/LVDS yet */
3576 : };
3577 :
3578 : static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3579 : .dpms = amdgpu_atombios_encoder_dpms,
3580 : .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3581 : .prepare = dce_v11_0_encoder_prepare,
3582 : .mode_set = dce_v11_0_encoder_mode_set,
3583 : .commit = dce_v11_0_encoder_commit,
3584 : .disable = dce_v11_0_encoder_disable,
3585 : .detect = amdgpu_atombios_encoder_dig_detect,
3586 : };
3587 :
3588 : static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3589 : .dpms = amdgpu_atombios_encoder_dpms,
3590 : .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3591 : .prepare = dce_v11_0_encoder_prepare,
3592 : .mode_set = dce_v11_0_encoder_mode_set,
3593 : .commit = dce_v11_0_encoder_commit,
3594 : .detect = amdgpu_atombios_encoder_dac_detect,
3595 : };
3596 :
3597 0 : static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3598 : {
3599 0 : struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3600 0 : if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3601 0 : amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3602 0 : kfree(amdgpu_encoder->enc_priv);
3603 0 : drm_encoder_cleanup(encoder);
3604 0 : kfree(amdgpu_encoder);
3605 0 : }
3606 :
3607 : static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3608 : .destroy = dce_v11_0_encoder_destroy,
3609 : };
3610 :
3611 0 : static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3612 : uint32_t encoder_enum,
3613 : uint32_t supported_device,
3614 : u16 caps)
3615 : {
3616 0 : struct drm_device *dev = adev_to_drm(adev);
3617 : struct drm_encoder *encoder;
3618 : struct amdgpu_encoder *amdgpu_encoder;
3619 :
3620 : /* see if we already added it */
3621 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3622 0 : amdgpu_encoder = to_amdgpu_encoder(encoder);
3623 0 : if (amdgpu_encoder->encoder_enum == encoder_enum) {
3624 0 : amdgpu_encoder->devices |= supported_device;
3625 0 : return;
3626 : }
3627 :
3628 : }
3629 :
3630 : /* add a new one */
3631 0 : amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3632 0 : if (!amdgpu_encoder)
3633 : return;
3634 :
3635 0 : encoder = &amdgpu_encoder->base;
3636 0 : switch (adev->mode_info.num_crtc) {
3637 : case 1:
3638 0 : encoder->possible_crtcs = 0x1;
3639 0 : break;
3640 : case 2:
3641 : default:
3642 0 : encoder->possible_crtcs = 0x3;
3643 0 : break;
3644 : case 3:
3645 0 : encoder->possible_crtcs = 0x7;
3646 0 : break;
3647 : case 4:
3648 0 : encoder->possible_crtcs = 0xf;
3649 0 : break;
3650 : case 5:
3651 0 : encoder->possible_crtcs = 0x1f;
3652 0 : break;
3653 : case 6:
3654 0 : encoder->possible_crtcs = 0x3f;
3655 0 : break;
3656 : }
3657 :
3658 0 : amdgpu_encoder->enc_priv = NULL;
3659 :
3660 0 : amdgpu_encoder->encoder_enum = encoder_enum;
3661 0 : amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3662 0 : amdgpu_encoder->devices = supported_device;
3663 0 : amdgpu_encoder->rmx_type = RMX_OFF;
3664 0 : amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3665 0 : amdgpu_encoder->is_ext_encoder = false;
3666 0 : amdgpu_encoder->caps = caps;
3667 :
3668 : switch (amdgpu_encoder->encoder_id) {
3669 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3670 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3671 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3672 : DRM_MODE_ENCODER_DAC, NULL);
3673 0 : drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3674 : break;
3675 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3676 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3677 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3678 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3679 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3680 0 : if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3681 0 : amdgpu_encoder->rmx_type = RMX_FULL;
3682 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3683 : DRM_MODE_ENCODER_LVDS, NULL);
3684 0 : amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3685 0 : } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3686 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3687 : DRM_MODE_ENCODER_DAC, NULL);
3688 0 : amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3689 : } else {
3690 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3691 : DRM_MODE_ENCODER_TMDS, NULL);
3692 0 : amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3693 : }
3694 0 : drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3695 : break;
3696 : case ENCODER_OBJECT_ID_SI170B:
3697 : case ENCODER_OBJECT_ID_CH7303:
3698 : case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3699 : case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3700 : case ENCODER_OBJECT_ID_TITFP513:
3701 : case ENCODER_OBJECT_ID_VT1623:
3702 : case ENCODER_OBJECT_ID_HDMI_SI1930:
3703 : case ENCODER_OBJECT_ID_TRAVIS:
3704 : case ENCODER_OBJECT_ID_NUTMEG:
3705 : /* these are handled by the primary encoders */
3706 0 : amdgpu_encoder->is_ext_encoder = true;
3707 0 : if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3708 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3709 : DRM_MODE_ENCODER_LVDS, NULL);
3710 0 : else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3711 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3712 : DRM_MODE_ENCODER_DAC, NULL);
3713 : else
3714 0 : drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3715 : DRM_MODE_ENCODER_TMDS, NULL);
3716 0 : drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3717 : break;
3718 : }
3719 : }
3720 :
3721 : static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3722 : .bandwidth_update = &dce_v11_0_bandwidth_update,
3723 : .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3724 : .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3725 : .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3726 : .hpd_sense = &dce_v11_0_hpd_sense,
3727 : .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3728 : .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3729 : .page_flip = &dce_v11_0_page_flip,
3730 : .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3731 : .add_encoder = &dce_v11_0_encoder_add,
3732 : .add_connector = &amdgpu_connector_add,
3733 : };
3734 :
3735 : static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3736 : {
3737 0 : adev->mode_info.funcs = &dce_v11_0_display_funcs;
3738 : }
3739 :
3740 : static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3741 : .set = dce_v11_0_set_crtc_irq_state,
3742 : .process = dce_v11_0_crtc_irq,
3743 : };
3744 :
3745 : static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3746 : .set = dce_v11_0_set_pageflip_irq_state,
3747 : .process = dce_v11_0_pageflip_irq,
3748 : };
3749 :
3750 : static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3751 : .set = dce_v11_0_set_hpd_irq_state,
3752 : .process = dce_v11_0_hpd_irq,
3753 : };
3754 :
3755 : static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3756 : {
3757 0 : if (adev->mode_info.num_crtc > 0)
3758 0 : adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3759 : else
3760 0 : adev->crtc_irq.num_types = 0;
3761 0 : adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3762 :
3763 0 : adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3764 0 : adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3765 :
3766 0 : adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3767 0 : adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3768 : }
3769 :
3770 : const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3771 : {
3772 : .type = AMD_IP_BLOCK_TYPE_DCE,
3773 : .major = 11,
3774 : .minor = 0,
3775 : .rev = 0,
3776 : .funcs = &dce_v11_0_ip_funcs,
3777 : };
3778 :
3779 : const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3780 : {
3781 : .type = AMD_IP_BLOCK_TYPE_DCE,
3782 : .major = 11,
3783 : .minor = 2,
3784 : .rev = 0,
3785 : .funcs = &dce_v11_0_ip_funcs,
3786 : };
|
