LCOV - code coverage report

Current view: top level - drivers/gpu/drm/amd/amdgpu - gfx_v9_0.c (source / functions) Hit Total Coverage Test: coverage.info Lines: 0 2753 0.0 % Date: 2022-12-09 01:23:36 Functions: 0 161 0.0 %

Function Name	Hit count
gfx_v9_0_check_fw_write_wait	0
gfx_v9_0_check_if_need_gfxoff	0
gfx_v9_0_compute_ring_init	0
gfx_v9_0_constants_init	0
gfx_v9_0_cp_compute_enable	0
gfx_v9_0_cp_compute_load_microcode	0
gfx_v9_0_cp_enable	0
gfx_v9_0_cp_gfx_enable	0
gfx_v9_0_cp_gfx_load_microcode	0
gfx_v9_0_cp_gfx_resume	0
gfx_v9_0_cp_gfx_start	0
gfx_v9_0_cp_jump_table_num	0
gfx_v9_0_cp_resume	0
gfx_v9_0_do_edc_gds_workarounds	0
gfx_v9_0_do_edc_gpr_workarounds	0
gfx_v9_0_early_init	0
gfx_v9_0_ecc_late_init	0
gfx_v9_0_emit_mem_sync	0
gfx_v9_0_emit_wave_limit	0
gfx_v9_0_emit_wave_limit_cs	0
gfx_v9_0_enable_cp_power_gating	0
gfx_v9_0_enable_gfx_cg_power_gating	0
gfx_v9_0_enable_gfx_dynamic_mg_power_gating	0
gfx_v9_0_enable_gfx_pipeline_powergating	0
gfx_v9_0_enable_gfx_static_mg_power_gating	0
gfx_v9_0_enable_gui_idle_interrupt	0
gfx_v9_0_enable_lbpw	0
gfx_v9_0_enable_save_restore_machine	0
gfx_v9_0_enable_sck_slow_down_on_power_down	0
gfx_v9_0_enable_sck_slow_down_on_power_up	0
gfx_v9_0_eop_irq	0
gfx_v9_0_fault.isra.15	0
gfx_v9_0_free_microcode	0
gfx_v9_0_get_clockgating_state	0
gfx_v9_0_get_csb_buffer	0
gfx_v9_0_get_csb_size	0
gfx_v9_0_get_cu_active_bitmap	0
gfx_v9_0_get_cu_info	0
gfx_v9_0_get_gpu_clock_counter	0
gfx_v9_0_get_rb_active_bitmap	0
gfx_v9_0_gpu_early_init	0
gfx_v9_0_hw_fini	0
gfx_v9_0_hw_init	0
gfx_v9_0_init_always_on_cu_mask	0
gfx_v9_0_init_compute_vmid	0
gfx_v9_0_init_cp_compute_microcode	0
gfx_v9_0_init_cp_gfx_microcode	0
gfx_v9_0_init_csb	0
gfx_v9_0_init_gds_vmid	0
gfx_v9_0_init_gfx_power_gating	0
gfx_v9_0_init_golden_registers	0
gfx_v9_0_init_lbpw	0
gfx_v9_0_init_microcode	0
gfx_v9_0_init_pg	0
gfx_v9_0_init_rlc_ext_microcode	0
gfx_v9_0_init_rlc_microcode	0
gfx_v9_0_init_rlcg_reg_access_ctrl	0
gfx_v9_0_init_sq_config	0
gfx_v9_0_init_tcp_config	0
gfx_v9_0_is_idle	0
gfx_v9_0_is_rlc_enabled	0
gfx_v9_0_is_rlcg_access_range	0
gfx_v9_0_kcq_init_queue	0
gfx_v9_0_kcq_resume	0
gfx_v9_0_kiq_fini_register.isra.13	0
gfx_v9_0_kiq_init_queue	0
gfx_v9_0_kiq_init_register	0
gfx_v9_0_kiq_invalidate_tlbs	0
gfx_v9_0_kiq_map_queues	0
gfx_v9_0_kiq_query_status	0
gfx_v9_0_kiq_read_clock	0
gfx_v9_0_kiq_resume	0
gfx_v9_0_kiq_set_resources	0
gfx_v9_0_kiq_setting	0
gfx_v9_0_kiq_unmap_queues	0
gfx_v9_0_late_init	0
gfx_v9_0_mec_fini	0
gfx_v9_0_mec_init	0
gfx_v9_0_mqd_init	0
gfx_v9_0_priv_inst_irq	0
gfx_v9_0_priv_reg_irq	0
gfx_v9_0_query_ras_error_count	0
gfx_v9_0_query_utc_edc_status.isra.12	0
gfx_v9_0_ras_error_count.isra.11	0
gfx_v9_0_ras_error_inject	0
gfx_v9_0_read_wave_data	0
gfx_v9_0_read_wave_sgprs	0
gfx_v9_0_read_wave_vgprs	0
gfx_v9_0_reset_ras_error_count	0
gfx_v9_0_resume	0
gfx_v9_0_ring_emit_ce_meta	0
gfx_v9_0_ring_emit_de_meta	0
gfx_v9_0_ring_emit_fence	0
gfx_v9_0_ring_emit_fence_kiq	0
gfx_v9_0_ring_emit_frame_cntl	0
gfx_v9_0_ring_emit_gds_switch	0
gfx_v9_0_ring_emit_hdp_flush	0
gfx_v9_0_ring_emit_ib_compute	0
gfx_v9_0_ring_emit_ib_gfx	0
gfx_v9_0_ring_emit_init_cond_exec	0
gfx_v9_0_ring_emit_patch_cond_exec	0
gfx_v9_0_ring_emit_pipeline_sync	0
gfx_v9_0_ring_emit_reg_wait	0
gfx_v9_0_ring_emit_reg_write_reg_wait	0
gfx_v9_0_ring_emit_rreg	0
gfx_v9_0_ring_emit_vm_flush	0
gfx_v9_0_ring_emit_wreg	0
gfx_v9_0_ring_get_rptr_compute	0
gfx_v9_0_ring_get_rptr_gfx	0
gfx_v9_0_ring_get_wptr_compute	0
gfx_v9_0_ring_get_wptr_gfx	0
gfx_v9_0_ring_set_wptr_compute	0
gfx_v9_0_ring_set_wptr_gfx	0
gfx_v9_0_ring_soft_recovery	0
gfx_v9_0_ring_test_ib	0
gfx_v9_0_ring_test_ring	0
gfx_v9_0_rlc_init	0
gfx_v9_0_rlc_load_microcode	0
gfx_v9_0_rlc_reset	0
gfx_v9_0_rlc_resume	0
gfx_v9_0_rlc_start	0
gfx_v9_0_rlc_stop	0
gfx_v9_0_select_me_pipe_q	0
gfx_v9_0_select_se_sh	0
gfx_v9_0_set_clockgating_state	0
gfx_v9_0_set_compute_eop_interrupt_state	0
gfx_v9_0_set_cp_ecc_error_state	0
gfx_v9_0_set_eop_interrupt_state	0
gfx_v9_0_set_gds_init	0
gfx_v9_0_set_gfx_eop_interrupt_state	0
gfx_v9_0_set_powergating_state	0
gfx_v9_0_set_priv_inst_fault_state	0
gfx_v9_0_set_priv_reg_fault_state	0
gfx_v9_0_set_safe_mode	0
gfx_v9_0_set_user_cu_inactive_bitmap	0
gfx_v9_0_setup_rb	0
gfx_v9_0_should_disable_gfxoff	0
gfx_v9_0_soft_reset	0
gfx_v9_0_suspend	0
gfx_v9_0_sw_fini	0
gfx_v9_0_sw_init	0
gfx_v9_0_unset_safe_mode	0
gfx_v9_0_update_3d_clock_gating	0
gfx_v9_0_update_coarse_grain_clock_gating	0
gfx_v9_0_update_gfx_cg_power_gating	0
gfx_v9_0_update_gfx_clock_gating	0
gfx_v9_0_update_gfx_mg_power_gating	0
gfx_v9_0_update_medium_grain_clock_gating	0
gfx_v9_0_update_spm_vmid	0
gfx_v9_0_wait_for_idle	0
gfx_v9_0_wait_for_rlc_serdes	0
gfx_v9_0_wait_reg_mem	0
gfx_v9_0_write_data_to_reg	0
gfx_v9_1_init_rlc_save_restore_list	0
gfx_v9_1_parse_ind_reg_list	0
gfx_v9_4_init_lbpw	0
gfx_v9_ring_emit_cntxcntl	0
gfx_v9_ring_emit_sb	0
pwr_10_0_gfxip_control_over_cgpg	0
wave_read_ind	0
wave_read_regs	0

Generated by: LCOV version 1.14