Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include "amdgpu.h"
25 : #include "gfxhub_v2_0.h"
26 :
27 : #include "gc/gc_10_1_0_offset.h"
28 : #include "gc/gc_10_1_0_sh_mask.h"
29 : #include "gc/gc_10_1_0_default.h"
30 : #include "navi10_enum.h"
31 :
32 : #include "soc15_common.h"
33 :
34 : static const char *gfxhub_client_ids[] = {
35 : "CB/DB",
36 : "Reserved",
37 : "GE1",
38 : "GE2",
39 : "CPF",
40 : "CPC",
41 : "CPG",
42 : "RLC",
43 : "TCP",
44 : "SQC (inst)",
45 : "SQC (data)",
46 : "SQG",
47 : "Reserved",
48 : "SDMA0",
49 : "SDMA1",
50 : "GCR",
51 : "SDMA2",
52 : "SDMA3",
53 : };
54 :
55 0 : static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid,
56 : uint32_t flush_type)
57 : {
58 0 : u32 req = 0;
59 :
60 : /* invalidate using legacy mode on vmid*/
61 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
62 : PER_VMID_INVALIDATE_REQ, 1 << vmid);
63 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
64 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
65 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
66 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
67 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
68 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
69 0 : req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
70 : CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
71 :
72 0 : return req;
73 : }
74 :
75 : static void
76 0 : gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
77 : uint32_t status)
78 : {
79 0 : u32 cid = REG_GET_FIELD(status,
80 : GCVM_L2_PROTECTION_FAULT_STATUS, CID);
81 :
82 0 : dev_err(adev->dev,
83 : "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
84 : status);
85 0 : dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
86 : cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
87 : cid);
88 0 : dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
89 : REG_GET_FIELD(status,
90 : GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
91 0 : dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
92 : REG_GET_FIELD(status,
93 : GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
94 0 : dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
95 : REG_GET_FIELD(status,
96 : GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
97 0 : dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
98 : REG_GET_FIELD(status,
99 : GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
100 0 : dev_err(adev->dev, "\t RW: 0x%lx\n",
101 : REG_GET_FIELD(status,
102 : GCVM_L2_PROTECTION_FAULT_STATUS, RW));
103 0 : }
104 :
105 0 : static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
106 : {
107 0 : u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
108 :
109 0 : base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
110 0 : base <<= 24;
111 :
112 0 : return base;
113 : }
114 :
115 0 : static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
116 : {
117 0 : return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
118 : }
119 :
120 0 : static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
121 : uint64_t page_table_base)
122 : {
123 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
124 :
125 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
126 : hub->ctx_addr_distance * vmid,
127 : lower_32_bits(page_table_base));
128 :
129 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
130 : hub->ctx_addr_distance * vmid,
131 : upper_32_bits(page_table_base));
132 0 : }
133 :
134 0 : static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
135 : {
136 0 : uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
137 :
138 0 : gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
139 :
140 0 : WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
141 : (u32)(adev->gmc.gart_start >> 12));
142 0 : WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
143 : (u32)(adev->gmc.gart_start >> 44));
144 :
145 0 : WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
146 : (u32)(adev->gmc.gart_end >> 12));
147 0 : WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
148 : (u32)(adev->gmc.gart_end >> 44));
149 0 : }
150 :
151 0 : static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
152 : {
153 : uint64_t value;
154 :
155 0 : if (!amdgpu_sriov_vf(adev)) {
156 : /* Program the AGP BAR */
157 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
158 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
159 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
160 :
161 : /* Program the system aperture low logical page number. */
162 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
163 : min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
164 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
165 : max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
166 :
167 : /* Set default page address. */
168 0 : value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
169 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
170 : (u32)(value >> 12));
171 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
172 : (u32)(value >> 44));
173 : }
174 :
175 : /* Program "protection fault". */
176 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
177 : (u32)(adev->dummy_page_addr >> 12));
178 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
179 : (u32)((u64)adev->dummy_page_addr >> 44));
180 :
181 0 : WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
182 : ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
183 0 : }
184 :
185 :
186 0 : static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
187 : {
188 : uint32_t tmp;
189 :
190 : /* Setup TLB control */
191 0 : tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
192 :
193 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
194 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
195 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
196 : ENABLE_ADVANCED_DRIVER_MODEL, 1);
197 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
198 : SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
199 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
200 : MTYPE, MTYPE_UC); /* UC, uncached */
201 :
202 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
203 0 : }
204 :
205 0 : static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
206 : {
207 : uint32_t tmp;
208 :
209 : /* These regs are not accessible for VF, PF will program these in SRIOV */
210 0 : if (amdgpu_sriov_vf(adev))
211 : return;
212 :
213 : /* Setup L2 cache */
214 0 : tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
215 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
216 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
217 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
218 : ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
219 : /* XXX for emulation, Refer to closed source code.*/
220 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
221 : L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
222 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
223 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
224 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
225 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
226 :
227 0 : tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
228 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
229 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
230 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
231 :
232 0 : tmp = mmGCVM_L2_CNTL3_DEFAULT;
233 0 : if (adev->gmc.translate_further) {
234 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
235 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
236 : L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
237 : } else {
238 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
239 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
240 : L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
241 : }
242 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
243 :
244 0 : tmp = mmGCVM_L2_CNTL4_DEFAULT;
245 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
246 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
247 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
248 :
249 0 : tmp = mmGCVM_L2_CNTL5_DEFAULT;
250 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
251 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
252 : }
253 :
254 0 : static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
255 : {
256 : uint32_t tmp;
257 :
258 0 : tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
259 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
260 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
261 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
262 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
263 0 : WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
264 0 : }
265 :
266 0 : static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
267 : {
268 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
269 : 0xFFFFFFFF);
270 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
271 : 0x0000000F);
272 :
273 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
274 : 0);
275 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
276 : 0);
277 :
278 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
279 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
280 :
281 0 : }
282 :
283 0 : static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
284 : {
285 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
286 : int i;
287 : uint32_t tmp;
288 :
289 0 : for (i = 0; i <= 14; i++) {
290 0 : tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
291 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
292 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
293 : adev->vm_manager.num_level);
294 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
295 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
296 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
297 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
298 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
299 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
300 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
301 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
302 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
303 : READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
304 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
305 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
306 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
307 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
308 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
309 : PAGE_TABLE_BLOCK_SIZE,
310 : adev->vm_manager.block_size - 9);
311 : /* Send no-retry XNACK on fault to suppress VM fault storm. */
312 0 : tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
313 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
314 : !adev->gmc.noretry);
315 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
316 : i * hub->ctx_distance, tmp);
317 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
318 : i * hub->ctx_addr_distance, 0);
319 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
320 : i * hub->ctx_addr_distance, 0);
321 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
322 : i * hub->ctx_addr_distance,
323 : lower_32_bits(adev->vm_manager.max_pfn - 1));
324 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
325 : i * hub->ctx_addr_distance,
326 : upper_32_bits(adev->vm_manager.max_pfn - 1));
327 : }
328 :
329 0 : hub->vm_cntx_cntl = tmp;
330 0 : }
331 :
332 0 : static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
333 : {
334 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
335 : unsigned i;
336 :
337 0 : for (i = 0 ; i < 18; ++i) {
338 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
339 : i * hub->eng_addr_distance, 0xffffffff);
340 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
341 : i * hub->eng_addr_distance, 0x1f);
342 : }
343 0 : }
344 :
345 0 : static int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
346 : {
347 : /* GART Enable. */
348 0 : gfxhub_v2_0_init_gart_aperture_regs(adev);
349 0 : gfxhub_v2_0_init_system_aperture_regs(adev);
350 0 : gfxhub_v2_0_init_tlb_regs(adev);
351 0 : gfxhub_v2_0_init_cache_regs(adev);
352 :
353 0 : gfxhub_v2_0_enable_system_domain(adev);
354 0 : gfxhub_v2_0_disable_identity_aperture(adev);
355 0 : gfxhub_v2_0_setup_vmid_config(adev);
356 0 : gfxhub_v2_0_program_invalidation(adev);
357 :
358 0 : return 0;
359 : }
360 :
361 0 : static void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
362 : {
363 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
364 : u32 tmp;
365 : u32 i;
366 :
367 : /* Disable all tables */
368 0 : for (i = 0; i < 16; i++)
369 0 : WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
370 : i * hub->ctx_distance, 0);
371 :
372 : /* Setup TLB control */
373 0 : tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
374 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
375 0 : tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
376 : ENABLE_ADVANCED_DRIVER_MODEL, 0);
377 0 : WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
378 :
379 0 : if (!amdgpu_sriov_vf(adev)) {
380 : /* Setup L2 cache */
381 0 : WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
382 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
383 : }
384 0 : }
385 :
386 : /**
387 : * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
388 : *
389 : * @adev: amdgpu_device pointer
390 : * @value: true redirects VM faults to the default page
391 : */
392 0 : static void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
393 : bool value)
394 : {
395 : u32 tmp;
396 0 : tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
397 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
398 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
399 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
400 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
401 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
402 : PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
403 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
404 : PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
405 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
406 : TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
407 : value);
408 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
409 : NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
410 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
411 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
412 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
413 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
414 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
415 : READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
416 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
417 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
418 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
419 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
420 0 : if (!value) {
421 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
422 : CRASH_ON_NO_RETRY_FAULT, 1);
423 0 : tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
424 : CRASH_ON_RETRY_FAULT, 1);
425 : }
426 0 : WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
427 0 : }
428 :
429 : static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
430 : .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
431 : .get_invalidate_req = gfxhub_v2_0_get_invalidate_req,
432 : };
433 :
434 0 : static void gfxhub_v2_0_init(struct amdgpu_device *adev)
435 : {
436 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
437 :
438 0 : hub->ctx0_ptb_addr_lo32 =
439 0 : SOC15_REG_OFFSET(GC, 0,
440 : mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
441 0 : hub->ctx0_ptb_addr_hi32 =
442 0 : SOC15_REG_OFFSET(GC, 0,
443 : mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
444 0 : hub->vm_inv_eng0_sem =
445 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
446 0 : hub->vm_inv_eng0_req =
447 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
448 0 : hub->vm_inv_eng0_ack =
449 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
450 0 : hub->vm_context0_cntl =
451 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
452 0 : hub->vm_l2_pro_fault_status =
453 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
454 0 : hub->vm_l2_pro_fault_cntl =
455 0 : SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
456 :
457 0 : hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
458 0 : hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
459 : mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
460 0 : hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
461 : mmGCVM_INVALIDATE_ENG0_REQ;
462 0 : hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
463 : mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
464 :
465 0 : hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
466 : GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
467 : GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
468 : GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
469 : GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
470 : GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
471 : GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
472 :
473 0 : hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
474 0 : }
475 :
476 : const struct amdgpu_gfxhub_funcs gfxhub_v2_0_funcs = {
477 : .get_fb_location = gfxhub_v2_0_get_fb_location,
478 : .get_mc_fb_offset = gfxhub_v2_0_get_mc_fb_offset,
479 : .setup_vm_pt_regs = gfxhub_v2_0_setup_vm_pt_regs,
480 : .gart_enable = gfxhub_v2_0_gart_enable,
481 : .gart_disable = gfxhub_v2_0_gart_disable,
482 : .set_fault_enable_default = gfxhub_v2_0_set_fault_enable_default,
483 : .init = gfxhub_v2_0_init,
484 : };
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