Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_atombios.h"
25 : #include "hdp_v4_0.h"
26 : #include "amdgpu_ras.h"
27 :
28 : #include "hdp/hdp_4_0_offset.h"
29 : #include "hdp/hdp_4_0_sh_mask.h"
30 : #include <uapi/linux/kfd_ioctl.h>
31 :
32 : /* for Vega20 register name change */
33 : #define mmHDP_MEM_POWER_CTRL 0x00d4
34 : #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
35 : #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
36 : #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
37 : #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
38 : #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
39 :
40 0 : static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
41 : struct amdgpu_ring *ring)
42 : {
43 0 : if (!ring || !ring->funcs->emit_wreg)
44 0 : WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
45 : else
46 0 : amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
47 0 : }
48 :
49 0 : static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
50 : struct amdgpu_ring *ring)
51 : {
52 0 : if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
53 : return;
54 :
55 0 : if (!ring || !ring->funcs->emit_wreg)
56 0 : WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
57 : else
58 0 : amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
59 : HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
60 : }
61 :
62 0 : static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,
63 : void *ras_error_status)
64 : {
65 0 : struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
66 :
67 0 : err_data->ue_count = 0;
68 0 : err_data->ce_count = 0;
69 :
70 0 : if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
71 : return;
72 :
73 : /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */
74 0 : err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
75 : };
76 :
77 0 : static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
78 : {
79 0 : if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
80 : return;
81 :
82 0 : if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0))
83 0 : WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0);
84 : else
85 : /*read back hdp ras counter to reset it to 0 */
86 0 : RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
87 : }
88 :
89 0 : static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev,
90 : bool enable)
91 : {
92 : uint32_t def, data;
93 :
94 0 : if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) ||
95 0 : adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) ||
96 0 : adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) ||
97 : adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) {
98 0 : def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
99 :
100 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
101 0 : data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
102 : else
103 0 : data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
104 :
105 0 : if (def != data)
106 0 : WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
107 : } else {
108 0 : def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
109 :
110 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
111 0 : data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
112 : HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
113 : HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
114 : HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
115 : else
116 0 : data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
117 : HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
118 : HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
119 : HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
120 :
121 0 : if (def != data)
122 0 : WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
123 : }
124 0 : }
125 :
126 0 : static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev,
127 : u64 *flags)
128 : {
129 : int data;
130 :
131 : /* AMD_CG_SUPPORT_HDP_LS */
132 0 : data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
133 0 : if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
134 0 : *flags |= AMD_CG_SUPPORT_HDP_LS;
135 0 : }
136 :
137 0 : static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
138 : {
139 0 : switch (adev->ip_versions[HDP_HWIP][0]) {
140 : case IP_VERSION(4, 2, 1):
141 0 : WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
142 : break;
143 : default:
144 : break;
145 : }
146 :
147 0 : WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
148 :
149 0 : if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
150 0 : WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
151 :
152 0 : WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
153 0 : WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
154 0 : }
155 :
156 : struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
157 : .query_ras_error_count = hdp_v4_0_query_ras_error_count,
158 : .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
159 : };
160 :
161 : struct amdgpu_hdp_ras hdp_v4_0_ras = {
162 : .ras_block = {
163 : .ras_comm = {
164 : .name = "hdp",
165 : .block = AMDGPU_RAS_BLOCK__HDP,
166 : .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
167 : },
168 : .hw_ops = &hdp_v4_0_ras_hw_ops,
169 : },
170 : };
171 :
172 : const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
173 : .flush_hdp = hdp_v4_0_flush_hdp,
174 : .invalidate_hdp = hdp_v4_0_invalidate_hdp,
175 : .update_clock_gating = hdp_v4_0_update_clock_gating,
176 : .get_clock_gating_state = hdp_v4_0_get_clockgating_state,
177 : .init_registers = hdp_v4_0_init_registers,
178 : };
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