Line data Source code
1 : /*
2 : * Copyright 2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/firmware.h>
25 : #include "amdgpu.h"
26 : #include "amdgpu_imu.h"
27 : #include "amdgpu_dpm.h"
28 :
29 : #include "imu_v11_0_3.h"
30 :
31 : #include "gc/gc_11_0_0_offset.h"
32 : #include "gc/gc_11_0_0_sh_mask.h"
33 :
34 : MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin");
35 : MODULE_FIRMWARE("amdgpu/gc_11_0_1_imu.bin");
36 : MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin");
37 : MODULE_FIRMWARE("amdgpu/gc_11_0_3_imu.bin");
38 :
39 0 : static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
40 : {
41 : char fw_name[40];
42 : char ucode_prefix[30];
43 : int err;
44 : const struct imu_firmware_header_v1_0 *imu_hdr;
45 0 : struct amdgpu_firmware_info *info = NULL;
46 :
47 0 : DRM_DEBUG("\n");
48 :
49 0 : amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
50 :
51 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix);
52 0 : err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev);
53 0 : if (err)
54 : goto out;
55 0 : err = amdgpu_ucode_validate(adev->gfx.imu_fw);
56 0 : if (err)
57 : goto out;
58 0 : imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
59 0 : adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
60 : //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
61 :
62 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
63 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
64 0 : info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
65 0 : info->fw = adev->gfx.imu_fw;
66 0 : adev->firmware.fw_size +=
67 0 : ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE);
68 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D];
69 0 : info->ucode_id = AMDGPU_UCODE_ID_IMU_D;
70 0 : info->fw = adev->gfx.imu_fw;
71 0 : adev->firmware.fw_size +=
72 0 : ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE);
73 : }
74 :
75 : out:
76 0 : if (err) {
77 0 : dev_err(adev->dev,
78 : "gfx11: Failed to load firmware \"%s\"\n",
79 : fw_name);
80 0 : release_firmware(adev->gfx.imu_fw);
81 : }
82 :
83 0 : return err;
84 : }
85 :
86 0 : static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
87 : {
88 : const struct imu_firmware_header_v1_0 *hdr;
89 : const __le32 *fw_data;
90 : unsigned i, fw_size;
91 :
92 0 : if (!adev->gfx.imu_fw)
93 : return -EINVAL;
94 :
95 0 : hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
96 : //amdgpu_ucode_print_rlc_hdr(&hdr->header);
97 :
98 0 : fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
99 0 : le32_to_cpu(hdr->header.ucode_array_offset_bytes));
100 0 : fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4;
101 :
102 0 : WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0);
103 :
104 0 : for (i = 0; i < fw_size; i++)
105 0 : WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++));
106 :
107 0 : WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version);
108 :
109 0 : fw_data = (const __le32 *)(adev->gfx.imu_fw->data +
110 0 : le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
111 0 : le32_to_cpu(hdr->imu_iram_ucode_size_bytes));
112 0 : fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4;
113 :
114 0 : WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0);
115 :
116 0 : for (i = 0; i < fw_size; i++)
117 0 : WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++));
118 :
119 0 : WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version);
120 :
121 : return 0;
122 : }
123 :
124 0 : static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
125 : {
126 0 : int i, imu_reg_val = 0;
127 :
128 0 : for (i = 0; i < adev->usec_timeout; i++) {
129 0 : imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
130 0 : if ((imu_reg_val & 0x1f) == 0x1f)
131 : break;
132 0 : udelay(1);
133 : }
134 :
135 0 : if (i >= adev->usec_timeout) {
136 0 : dev_err(adev->dev, "init imu: IMU start timeout\n");
137 0 : return -ETIMEDOUT;
138 : }
139 :
140 : return 0;
141 : }
142 :
143 0 : static void imu_v11_0_setup(struct amdgpu_device *adev)
144 : {
145 : int imu_reg_val;
146 :
147 : //enable IMU debug mode
148 0 : WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
149 0 : WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
150 :
151 0 : if (adev->gfx.imu.mode == DEBUG_MODE) {
152 0 : imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
153 0 : imu_reg_val |= 0x1;
154 0 : WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
155 : }
156 :
157 : //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
158 0 : imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
159 0 : imu_reg_val |= 0x10007;
160 0 : WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val);
161 0 : }
162 :
163 0 : static int imu_v11_0_start(struct amdgpu_device *adev)
164 : {
165 : int imu_reg_val;
166 :
167 : //Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0
168 0 : imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
169 0 : imu_reg_val &= 0xfffffffe;
170 0 : WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
171 :
172 0 : if (adev->flags & AMD_IS_APU)
173 0 : amdgpu_dpm_set_gfx_power_up_by_imu(adev);
174 :
175 0 : return imu_v11_0_wait_for_reset_status(adev);
176 : }
177 :
178 : static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
179 : {
180 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
181 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
182 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
183 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
184 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS , 0x003f3fff, 0xe0000000),
185 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
186 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
187 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
188 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
189 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
190 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
191 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
192 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS , 0x003f3fbf, 0xe0000000),
193 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10201000, 0xe0000000),
194 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000080, 0xe0000000),
195 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000),
196 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000),
197 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000),
198 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
199 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000003f7, 0xe0000000),
200 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000),
201 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
202 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
203 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000),
204 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
205 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000),
206 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000),
207 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x0fffff01, 0xe0000000),
208 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000),
209 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000),
210 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000),
211 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000),
212 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000),
213 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000fffff, 0xe0000000),
214 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
215 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
216 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),
217 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000),
218 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000),
219 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
220 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000501, 0xe0000000),
221 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
222 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
223 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
224 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
225 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
226 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
227 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
228 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
229 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000545, 0xe0000000),
230 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13455431, 0xe0000000),
231 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x13455431, 0xe0000000),
232 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x76027602, 0xe0000000),
233 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x76207620, 0xe0000000),
234 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000345, 0xe0000000),
235 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x0000003e, 0xe0000000),
236 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000),
237 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000061ff, 0xe0000000),
238 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
239 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
240 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
241 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
242 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
243 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
244 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
245 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
246 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
247 : };
248 :
249 : static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11_0_2[] =
250 : {
251 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000),
252 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS, 0x003f3fbf, 0xe0000000),
253 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10200800, 0xe0000000),
254 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000088, 0xe0000000),
255 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000),
256 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000),
257 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000),
258 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000),
259 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000007ef, 0xe0000000),
260 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_DRAM_PAGE_BURST, 0x20080200, 0xe0000000),
261 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000),
262 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
263 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000),
264 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
265 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
266 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
267 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
268 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
269 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
270 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
271 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
272 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
273 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
274 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000),
275 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000),
276 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000),
277 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000),
278 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x00000f01, 0xe0000000),
279 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000),
280 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x000000e4, 0xe0000000),
281 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x000000e4, 0xe0000000),
282 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x01231023, 0xe0000000),
283 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000243, 0xe0000000),
284 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x00000002, 0xe0000000),
285 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000),
286 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000),
287 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000),
288 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000),
289 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000001ff, 0xe0000000),
290 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000),
291 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000061ff, 0xe0000000),
292 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000),
293 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000),
294 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000),
295 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000),
296 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000),
297 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000),
298 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000),
299 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
300 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
301 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000),
302 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00002825, 0xe0000000),
303 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000501, 0xe0000000),
304 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000),
305 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000),
306 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000),
307 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000),
308 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000),
309 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
310 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000),
311 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000),
312 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
313 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
314 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
315 : IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
316 : };
317 :
318 0 : static void program_imu_rlc_ram(struct amdgpu_device *adev,
319 : const struct imu_rlc_ram_golden *regs,
320 : const u32 array_size)
321 : {
322 : const struct imu_rlc_ram_golden *entry;
323 : u32 reg, data;
324 : int i;
325 :
326 0 : for (i = 0; i < array_size; ++i) {
327 0 : entry = ®s[i];
328 0 : reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
329 0 : reg |= entry->addr_mask;
330 :
331 0 : data = entry->data;
332 0 : if (entry->reg == regGCMC_VM_AGP_BASE)
333 : data = 0x00ffffff;
334 0 : else if (entry->reg == regGCMC_VM_AGP_TOP)
335 : data = 0x0;
336 0 : else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE)
337 0 : data = adev->gmc.vram_start >> 24;
338 0 : else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP)
339 0 : data = adev->gmc.vram_end >> 24;
340 :
341 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
342 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg);
343 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
344 : }
345 : //Indicate the latest entry
346 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
347 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);
348 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);
349 0 : }
350 :
351 0 : static void imu_v11_0_program_rlc_ram(struct amdgpu_device *adev)
352 : {
353 : u32 reg_data;
354 :
355 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
356 :
357 0 : switch (adev->ip_versions[GC_HWIP][0]) {
358 : case IP_VERSION(11, 0, 0):
359 0 : program_imu_rlc_ram(adev, imu_rlc_ram_golden_11,
360 : (const u32)ARRAY_SIZE(imu_rlc_ram_golden_11));
361 0 : break;
362 : case IP_VERSION(11, 0, 2):
363 0 : program_imu_rlc_ram(adev, imu_rlc_ram_golden_11_0_2,
364 : (const u32)ARRAY_SIZE(imu_rlc_ram_golden_11_0_2));
365 0 : break;
366 : case IP_VERSION(11, 0, 3):
367 0 : imu_v11_0_3_program_rlc_ram(adev);
368 0 : break;
369 : default:
370 0 : BUG();
371 : break;
372 : }
373 :
374 : //Indicate the contents of the RAM are valid
375 0 : reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);
376 0 : reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;
377 0 : WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);
378 0 : }
379 :
380 : const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
381 : .init_microcode = imu_v11_0_init_microcode,
382 : .load_microcode = imu_v11_0_load_microcode,
383 : .setup_imu = imu_v11_0_setup,
384 : .start_imu = imu_v11_0_start,
385 : .program_rlc_ram = imu_v11_0_program_rlc_ram,
386 : .wait_for_reset_status = imu_v11_0_wait_for_reset_status,
387 : };
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