Line data Source code
1 : /*
2 : * Copyright 2022 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include "amdgpu.h"
25 : #include "mmhub_v3_0_1.h"
26 :
27 : #include "mmhub/mmhub_3_0_1_offset.h"
28 : #include "mmhub/mmhub_3_0_1_sh_mask.h"
29 : #include "navi10_enum.h"
30 :
31 : #include "soc15_common.h"
32 :
33 : #define regMMVM_L2_CNTL3_DEFAULT 0x80100007
34 : #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1
35 : #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0
36 :
37 : static const char *mmhub_client_ids_v3_0_1[][2] = {
38 : [0][0] = "VMC",
39 : [4][0] = "DCEDMC",
40 : [5][0] = "DCEVGA",
41 : [6][0] = "MP0",
42 : [7][0] = "MP1",
43 : [8][0] = "MPIO",
44 : [16][0] = "HDP",
45 : [17][0] = "LSDMA",
46 : [18][0] = "JPEG",
47 : [19][0] = "VCNU0",
48 : [21][0] = "VSCH",
49 : [22][0] = "VCNU1",
50 : [23][0] = "VCN1",
51 : [32+20][0] = "VCN0",
52 : [2][1] = "DBGUNBIO",
53 : [3][1] = "DCEDWB",
54 : [4][1] = "DCEDMC",
55 : [5][1] = "DCEVGA",
56 : [6][1] = "MP0",
57 : [7][1] = "MP1",
58 : [8][1] = "MPIO",
59 : [10][1] = "DBGU0",
60 : [11][1] = "DBGU1",
61 : [12][1] = "DBGU2",
62 : [13][1] = "DBGU3",
63 : [14][1] = "XDP",
64 : [15][1] = "OSSSYS",
65 : [16][1] = "HDP",
66 : [17][1] = "LSDMA",
67 : [18][1] = "JPEG",
68 : [19][1] = "VCNU0",
69 : [20][1] = "VCN0",
70 : [21][1] = "VSCH",
71 : [22][1] = "VCNU1",
72 : [23][1] = "VCN1",
73 : };
74 :
75 0 : static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
76 : uint32_t flush_type)
77 : {
78 0 : u32 req = 0;
79 :
80 : /* invalidate using legacy mode on vmid*/
81 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
82 : PER_VMID_INVALIDATE_REQ, 1 << vmid);
83 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
84 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
85 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
86 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
87 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
88 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
89 0 : req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
90 : CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
91 :
92 0 : return req;
93 : }
94 :
95 : static void
96 0 : mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
97 : uint32_t status)
98 : {
99 : uint32_t cid, rw;
100 0 : const char *mmhub_cid = NULL;
101 :
102 0 : cid = REG_GET_FIELD(status,
103 : MMVM_L2_PROTECTION_FAULT_STATUS, CID);
104 0 : rw = REG_GET_FIELD(status,
105 : MMVM_L2_PROTECTION_FAULT_STATUS, RW);
106 :
107 0 : dev_err(adev->dev,
108 : "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
109 : status);
110 :
111 0 : switch (adev->ip_versions[MMHUB_HWIP][0]) {
112 : case IP_VERSION(3, 0, 1):
113 0 : mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
114 0 : break;
115 : default:
116 : mmhub_cid = NULL;
117 : break;
118 : }
119 :
120 0 : dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
121 : mmhub_cid ? mmhub_cid : "unknown", cid);
122 0 : dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
123 : REG_GET_FIELD(status,
124 : MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
125 0 : dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
126 : REG_GET_FIELD(status,
127 : MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
128 0 : dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
129 : REG_GET_FIELD(status,
130 : MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
131 0 : dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
132 : REG_GET_FIELD(status,
133 : MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
134 0 : dev_err(adev->dev, "\t RW: 0x%x\n", rw);
135 0 : }
136 :
137 0 : static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
138 : uint32_t vmid,
139 : uint64_t page_table_base)
140 : {
141 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
142 :
143 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
144 : hub->ctx_addr_distance * vmid,
145 : lower_32_bits(page_table_base));
146 :
147 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
148 : hub->ctx_addr_distance * vmid,
149 : upper_32_bits(page_table_base));
150 0 : }
151 :
152 0 : static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
153 : {
154 0 : uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
155 :
156 0 : mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
157 :
158 0 : WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
159 : (u32)(adev->gmc.gart_start >> 12));
160 0 : WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
161 : (u32)(adev->gmc.gart_start >> 44));
162 :
163 0 : WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
164 : (u32)(adev->gmc.gart_end >> 12));
165 0 : WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
166 : (u32)(adev->gmc.gart_end >> 44));
167 0 : }
168 :
169 0 : static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
170 : {
171 : uint64_t value;
172 : uint32_t tmp;
173 :
174 : /* Program the AGP BAR */
175 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
176 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
177 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
178 :
179 : /*
180 : * the new L1 policy will block SRIOV guest from writing
181 : * these regs, and they will be programed at host.
182 : * so skip programing these regs.
183 : */
184 : /* Program the system aperture low logical page number. */
185 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
186 : adev->gmc.vram_start >> 18);
187 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
188 : adev->gmc.vram_end >> 18);
189 :
190 : /* Set default page address. */
191 0 : value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
192 0 : adev->vm_manager.vram_base_offset;
193 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
194 : (u32)(value >> 12));
195 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
196 : (u32)(value >> 44));
197 :
198 : /* Program "protection fault". */
199 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
200 : (u32)(adev->dummy_page_addr >> 12));
201 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
202 : (u32)((u64)adev->dummy_page_addr >> 44));
203 :
204 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
205 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
206 : ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
207 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
208 0 : }
209 :
210 0 : static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
211 : {
212 : uint32_t tmp;
213 :
214 : /* Setup TLB control */
215 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
216 :
217 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
218 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
219 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
220 : ENABLE_ADVANCED_DRIVER_MODEL, 1);
221 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
222 : SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
223 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
224 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
225 : MTYPE, MTYPE_UC); /* UC, uncached */
226 :
227 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
228 0 : }
229 :
230 0 : static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
231 : {
232 : uint32_t tmp;
233 :
234 : /* Setup L2 cache */
235 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
236 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
237 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
238 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
239 : ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
240 : /* XXX for emulation, Refer to closed source code.*/
241 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
242 : 0);
243 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
244 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
245 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
246 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
247 :
248 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
249 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
250 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
251 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
252 :
253 0 : tmp = regMMVM_L2_CNTL3_DEFAULT;
254 0 : if (adev->gmc.translate_further) {
255 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
256 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
257 : L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
258 : } else {
259 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
260 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
261 : L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
262 : }
263 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
264 :
265 0 : tmp = regMMVM_L2_CNTL4_DEFAULT;
266 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
267 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
268 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
269 :
270 0 : tmp = regMMVM_L2_CNTL5_DEFAULT;
271 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
272 0 : WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
273 0 : }
274 :
275 0 : static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
276 : {
277 : uint32_t tmp;
278 :
279 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
280 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
281 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
282 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
283 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
284 0 : WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
285 0 : }
286 :
287 0 : static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
288 : {
289 0 : WREG32_SOC15(MMHUB, 0,
290 : regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
291 : 0xFFFFFFFF);
292 0 : WREG32_SOC15(MMHUB, 0,
293 : regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
294 : 0x0000000F);
295 :
296 0 : WREG32_SOC15(MMHUB, 0,
297 : regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
298 0 : WREG32_SOC15(MMHUB, 0,
299 : regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
300 :
301 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
302 : 0);
303 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
304 : 0);
305 0 : }
306 :
307 0 : static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
308 : {
309 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
310 : int i;
311 : uint32_t tmp;
312 :
313 0 : for (i = 0; i <= 14; i++) {
314 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
315 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
316 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
317 : adev->vm_manager.num_level);
318 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
319 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
320 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
321 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
322 : 1);
323 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
324 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
325 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
326 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
327 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
328 : READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
329 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
330 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
331 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
332 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
333 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
334 : PAGE_TABLE_BLOCK_SIZE,
335 : adev->vm_manager.block_size - 9);
336 : /* Send no-retry XNACK on fault to suppress VM fault storm. */
337 0 : tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
338 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
339 : !amdgpu_noretry);
340 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
341 : i * hub->ctx_distance, tmp);
342 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
343 : i * hub->ctx_addr_distance, 0);
344 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
345 : i * hub->ctx_addr_distance, 0);
346 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
347 : i * hub->ctx_addr_distance,
348 : lower_32_bits(adev->vm_manager.max_pfn - 1));
349 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
350 : i * hub->ctx_addr_distance,
351 : upper_32_bits(adev->vm_manager.max_pfn - 1));
352 : }
353 :
354 0 : hub->vm_cntx_cntl = tmp;
355 0 : }
356 :
357 0 : static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
358 : {
359 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
360 : unsigned i;
361 :
362 0 : for (i = 0; i < 18; ++i) {
363 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
364 : i * hub->eng_addr_distance, 0xffffffff);
365 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
366 : i * hub->eng_addr_distance, 0x1f);
367 : }
368 0 : }
369 :
370 0 : static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
371 : {
372 : /* GART Enable. */
373 0 : mmhub_v3_0_1_init_gart_aperture_regs(adev);
374 0 : mmhub_v3_0_1_init_system_aperture_regs(adev);
375 0 : mmhub_v3_0_1_init_tlb_regs(adev);
376 0 : mmhub_v3_0_1_init_cache_regs(adev);
377 :
378 0 : mmhub_v3_0_1_enable_system_domain(adev);
379 0 : mmhub_v3_0_1_disable_identity_aperture(adev);
380 0 : mmhub_v3_0_1_setup_vmid_config(adev);
381 0 : mmhub_v3_0_1_program_invalidation(adev);
382 :
383 0 : return 0;
384 : }
385 :
386 0 : static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
387 : {
388 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
389 : u32 tmp;
390 : u32 i;
391 :
392 : /* Disable all tables */
393 0 : for (i = 0; i < 16; i++)
394 0 : WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
395 : i * hub->ctx_distance, 0);
396 :
397 : /* Setup TLB control */
398 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
399 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
400 0 : tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
401 : ENABLE_ADVANCED_DRIVER_MODEL, 0);
402 0 : WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
403 :
404 : /* Setup L2 cache */
405 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
406 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
407 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
408 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
409 0 : }
410 :
411 : /**
412 : * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
413 : *
414 : * @adev: amdgpu_device pointer
415 : * @value: true redirects VM faults to the default page
416 : */
417 0 : static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
418 : bool value)
419 : {
420 : u32 tmp;
421 :
422 0 : tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
423 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
424 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
425 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
426 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
427 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
428 : PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
429 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
430 : PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
431 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
432 : TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
433 : value);
434 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
435 : NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
436 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
437 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
438 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
439 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
440 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
441 : READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
442 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
443 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
444 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
445 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
446 0 : if (!value) {
447 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
448 : CRASH_ON_NO_RETRY_FAULT, 1);
449 0 : tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
450 : CRASH_ON_RETRY_FAULT, 1);
451 : }
452 0 : WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
453 0 : }
454 :
455 : static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
456 : .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
457 : .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
458 : };
459 :
460 0 : static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
461 : {
462 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
463 :
464 0 : hub->ctx0_ptb_addr_lo32 =
465 0 : SOC15_REG_OFFSET(MMHUB, 0,
466 : regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
467 0 : hub->ctx0_ptb_addr_hi32 =
468 0 : SOC15_REG_OFFSET(MMHUB, 0,
469 : regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
470 0 : hub->vm_inv_eng0_sem =
471 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
472 0 : hub->vm_inv_eng0_req =
473 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
474 0 : hub->vm_inv_eng0_ack =
475 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
476 0 : hub->vm_context0_cntl =
477 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
478 0 : hub->vm_l2_pro_fault_status =
479 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
480 0 : hub->vm_l2_pro_fault_cntl =
481 0 : SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
482 :
483 0 : hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
484 0 : hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
485 : regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
486 0 : hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
487 : regMMVM_INVALIDATE_ENG0_REQ;
488 0 : hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
489 : regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
490 :
491 0 : hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
492 : MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
493 : MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
494 : MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
495 : MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
496 : MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
497 : MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
498 :
499 0 : hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
500 0 : }
501 :
502 0 : static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
503 : {
504 : u64 base;
505 :
506 0 : base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
507 0 : base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
508 0 : base <<= 24;
509 :
510 0 : return base;
511 : }
512 :
513 0 : static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
514 : {
515 0 : return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
516 : }
517 :
518 0 : static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
519 : bool enable)
520 : {
521 : uint32_t def, data;
522 :
523 0 : def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
524 :
525 0 : if (enable)
526 0 : data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
527 : else
528 0 : data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
529 :
530 0 : if (def != data)
531 0 : WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
532 0 : }
533 :
534 0 : static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
535 : bool enable)
536 : {
537 : uint32_t def, data;
538 :
539 0 : def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
540 :
541 0 : if (enable)
542 0 : data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
543 : else
544 0 : data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
545 :
546 0 : if (def != data)
547 0 : WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
548 0 : }
549 :
550 0 : static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
551 : enum amd_clockgating_state state)
552 : {
553 0 : if (amdgpu_sriov_vf(adev))
554 : return 0;
555 :
556 0 : mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
557 : state == AMD_CG_STATE_GATE);
558 0 : mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
559 : state == AMD_CG_STATE_GATE);
560 0 : return 0;
561 : }
562 :
563 0 : static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
564 : {
565 : int data;
566 :
567 0 : if (amdgpu_sriov_vf(adev))
568 0 : *flags = 0;
569 :
570 0 : data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
571 :
572 : /* AMD_CG_SUPPORT_MC_MGCG */
573 0 : if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
574 0 : *flags |= AMD_CG_SUPPORT_MC_MGCG;
575 :
576 : /* AMD_CG_SUPPORT_MC_LS */
577 0 : if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
578 0 : *flags |= AMD_CG_SUPPORT_MC_LS;
579 0 : }
580 :
581 : const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
582 : .init = mmhub_v3_0_1_init,
583 : .get_fb_location = mmhub_v3_0_1_get_fb_location,
584 : .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
585 : .gart_enable = mmhub_v3_0_1_gart_enable,
586 : .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
587 : .gart_disable = mmhub_v3_0_1_gart_disable,
588 : .set_clockgating = mmhub_v3_0_1_set_clockgating,
589 : .get_clockgating = mmhub_v3_0_1_get_clockgating,
590 : .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
591 : };
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