Line data Source code
1 : /*
2 : * Copyright 2018 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_ras.h"
25 : #include "mmhub_v9_4.h"
26 :
27 : #include "mmhub/mmhub_9_4_1_offset.h"
28 : #include "mmhub/mmhub_9_4_1_sh_mask.h"
29 : #include "mmhub/mmhub_9_4_1_default.h"
30 : #include "athub/athub_1_0_offset.h"
31 : #include "athub/athub_1_0_sh_mask.h"
32 : #include "vega10_enum.h"
33 : #include "soc15.h"
34 : #include "soc15_common.h"
35 :
36 : #define MMHUB_NUM_INSTANCES 2
37 : #define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000
38 :
39 0 : static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
40 : {
41 : /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
42 0 : u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
43 0 : u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
44 :
45 0 : base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
46 0 : base <<= 24;
47 :
48 0 : top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
49 0 : top <<= 24;
50 :
51 0 : adev->gmc.fb_start = base;
52 0 : adev->gmc.fb_end = top;
53 :
54 0 : return base;
55 : }
56 :
57 0 : static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
58 : uint32_t vmid, uint64_t value)
59 : {
60 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
61 :
62 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
63 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
64 : hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
65 : lower_32_bits(value));
66 :
67 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
68 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
69 : hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
70 : upper_32_bits(value));
71 :
72 0 : }
73 :
74 0 : static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
75 : int hubid)
76 : {
77 0 : uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
78 :
79 0 : mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
80 :
81 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
82 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
83 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
84 : (u32)(adev->gmc.gart_start >> 12));
85 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
86 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
87 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
88 : (u32)(adev->gmc.gart_start >> 44));
89 :
90 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
91 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
92 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
93 : (u32)(adev->gmc.gart_end >> 12));
94 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
95 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
96 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
97 : (u32)(adev->gmc.gart_end >> 44));
98 0 : }
99 :
100 0 : static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
101 : uint64_t page_table_base)
102 : {
103 : int i;
104 :
105 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
106 0 : mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
107 : page_table_base);
108 0 : }
109 :
110 0 : static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
111 : int hubid)
112 : {
113 : uint64_t value;
114 : uint32_t tmp;
115 :
116 : /* Program the AGP BAR */
117 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
118 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
119 : 0);
120 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
121 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
122 : adev->gmc.agp_end >> 24);
123 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
124 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
125 : adev->gmc.agp_start >> 24);
126 :
127 0 : if (!amdgpu_sriov_vf(adev)) {
128 : /* Program the system aperture low logical page number. */
129 0 : WREG32_SOC15_OFFSET(
130 : MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
131 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
132 : min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
133 0 : WREG32_SOC15_OFFSET(
134 : MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
135 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
136 : max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
137 :
138 : /* Set default page address. */
139 0 : value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
140 0 : WREG32_SOC15_OFFSET(
141 : MMHUB, 0,
142 : mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
143 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
144 : (u32)(value >> 12));
145 0 : WREG32_SOC15_OFFSET(
146 : MMHUB, 0,
147 : mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
148 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
149 : (u32)(value >> 44));
150 :
151 : /* Program "protection fault". */
152 0 : WREG32_SOC15_OFFSET(
153 : MMHUB, 0,
154 : mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
155 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
156 : (u32)(adev->dummy_page_addr >> 12));
157 0 : WREG32_SOC15_OFFSET(
158 : MMHUB, 0,
159 : mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
160 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
161 : (u32)((u64)adev->dummy_page_addr >> 44));
162 :
163 0 : tmp = RREG32_SOC15_OFFSET(
164 : MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
165 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
166 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
167 : ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
168 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
169 : mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
170 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
171 : tmp);
172 : }
173 0 : }
174 :
175 0 : static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
176 : {
177 : uint32_t tmp;
178 :
179 : /* Setup TLB control */
180 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
181 : mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
182 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
183 :
184 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
185 : ENABLE_L1_TLB, 1);
186 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
187 : SYSTEM_ACCESS_MODE, 3);
188 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
189 : ENABLE_ADVANCED_DRIVER_MODEL, 1);
190 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
191 : SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
192 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
193 : MTYPE, MTYPE_UC);/* XXX for emulation. */
194 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
195 : ATC_EN, 1);
196 :
197 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
198 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
199 0 : }
200 :
201 0 : static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
202 : {
203 : uint32_t tmp;
204 :
205 : /* Setup L2 cache */
206 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
207 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
208 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
209 : ENABLE_L2_CACHE, 1);
210 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
211 : ENABLE_L2_FRAGMENT_PROCESSING, 1);
212 : /* XXX for emulation, Refer to closed source code.*/
213 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
214 : L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
215 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
216 : PDE_FAULT_CLASSIFICATION, 0);
217 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
218 : CONTEXT1_IDENTITY_ACCESS_MODE, 1);
219 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
220 : IDENTITY_MODE_FRAGMENT_SIZE, 0);
221 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
222 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
223 :
224 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
225 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
226 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
227 : INVALIDATE_ALL_L1_TLBS, 1);
228 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
229 : INVALIDATE_L2_CACHE, 1);
230 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
231 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
232 :
233 0 : tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
234 0 : if (adev->gmc.translate_further) {
235 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
236 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
237 : L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
238 : } else {
239 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
240 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
241 : L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
242 : }
243 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
244 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
245 :
246 0 : tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
247 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
248 : VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
249 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
250 : VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
251 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
252 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
253 0 : }
254 :
255 0 : static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
256 : int hubid)
257 : {
258 : uint32_t tmp;
259 :
260 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
261 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
262 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
263 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
264 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
265 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
266 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
267 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
268 0 : }
269 :
270 0 : static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
271 : int hubid)
272 : {
273 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
274 : mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
275 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
276 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
277 : mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
278 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
279 :
280 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
281 : mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
282 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
283 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
284 : mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
285 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
286 :
287 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
288 : mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
289 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
290 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
291 : mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
292 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
293 0 : }
294 :
295 0 : static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
296 : {
297 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
298 : unsigned int num_level, block_size;
299 : uint32_t tmp;
300 : int i;
301 :
302 0 : num_level = adev->vm_manager.num_level;
303 0 : block_size = adev->vm_manager.block_size;
304 0 : if (adev->gmc.translate_further)
305 0 : num_level -= 1;
306 : else
307 0 : block_size -= 9;
308 :
309 0 : for (i = 0; i <= 14; i++) {
310 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
311 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
312 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
313 : ENABLE_CONTEXT, 1);
314 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
315 : PAGE_TABLE_DEPTH,
316 : num_level);
317 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
318 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
319 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
320 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
321 : 1);
322 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
323 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
324 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
325 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
326 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
327 : READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
328 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
329 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
330 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
331 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
332 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
333 : PAGE_TABLE_BLOCK_SIZE,
334 : block_size);
335 : /* Send no-retry XNACK on fault to suppress VM fault storm. */
336 0 : tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
337 : RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
338 : !adev->gmc.noretry);
339 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
340 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
341 : i * hub->ctx_distance, tmp);
342 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
343 : mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
344 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
345 : i * hub->ctx_addr_distance, 0);
346 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
347 : mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
348 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
349 : i * hub->ctx_addr_distance, 0);
350 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
351 : mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
352 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
353 : i * hub->ctx_addr_distance,
354 : lower_32_bits(adev->vm_manager.max_pfn - 1));
355 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
356 : mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
357 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
358 : i * hub->ctx_addr_distance,
359 : upper_32_bits(adev->vm_manager.max_pfn - 1));
360 : }
361 0 : }
362 :
363 0 : static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
364 : int hubid)
365 : {
366 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
367 : unsigned i;
368 :
369 0 : for (i = 0; i < 18; ++i) {
370 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
371 : mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
372 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
373 : i * hub->eng_addr_distance,
374 : 0xffffffff);
375 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
376 : mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
377 : hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
378 : i * hub->eng_addr_distance,
379 : 0x1f);
380 : }
381 0 : }
382 :
383 0 : static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
384 : {
385 : int i;
386 :
387 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
388 : /* GART Enable. */
389 0 : mmhub_v9_4_init_gart_aperture_regs(adev, i);
390 0 : mmhub_v9_4_init_system_aperture_regs(adev, i);
391 0 : mmhub_v9_4_init_tlb_regs(adev, i);
392 0 : if (!amdgpu_sriov_vf(adev))
393 0 : mmhub_v9_4_init_cache_regs(adev, i);
394 :
395 0 : mmhub_v9_4_enable_system_domain(adev, i);
396 0 : if (!amdgpu_sriov_vf(adev))
397 0 : mmhub_v9_4_disable_identity_aperture(adev, i);
398 0 : mmhub_v9_4_setup_vmid_config(adev, i);
399 0 : mmhub_v9_4_program_invalidation(adev, i);
400 : }
401 :
402 0 : return 0;
403 : }
404 :
405 0 : static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
406 : {
407 0 : struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
408 : u32 tmp;
409 : u32 i, j;
410 :
411 0 : for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
412 : /* Disable all tables */
413 0 : for (i = 0; i < AMDGPU_NUM_VMID; i++)
414 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
415 : mmVML2VC0_VM_CONTEXT0_CNTL,
416 : j * MMHUB_INSTANCE_REGISTER_OFFSET +
417 : i * hub->ctx_distance, 0);
418 :
419 : /* Setup TLB control */
420 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
421 : mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
422 : j * MMHUB_INSTANCE_REGISTER_OFFSET);
423 0 : tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
424 : ENABLE_L1_TLB, 0);
425 0 : tmp = REG_SET_FIELD(tmp,
426 : VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
427 : ENABLE_ADVANCED_DRIVER_MODEL, 0);
428 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
429 : mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
430 : j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
431 :
432 : /* Setup L2 cache */
433 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
434 : j * MMHUB_INSTANCE_REGISTER_OFFSET);
435 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
436 : ENABLE_L2_CACHE, 0);
437 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
438 : j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
439 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
440 : j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
441 : }
442 0 : }
443 :
444 : /**
445 : * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling
446 : *
447 : * @adev: amdgpu_device pointer
448 : * @value: true redirects VM faults to the default page
449 : */
450 0 : static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
451 : {
452 : u32 tmp;
453 : int i;
454 :
455 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
456 0 : tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
457 : mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
458 : i * MMHUB_INSTANCE_REGISTER_OFFSET);
459 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
460 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
461 : value);
462 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
463 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
464 : value);
465 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
466 : PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
467 : value);
468 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
469 : PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
470 : value);
471 0 : tmp = REG_SET_FIELD(tmp,
472 : VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
473 : TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
474 : value);
475 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
476 : NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
477 : value);
478 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
479 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
480 : value);
481 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
482 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
483 : value);
484 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
485 : READ_PROTECTION_FAULT_ENABLE_DEFAULT,
486 : value);
487 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
488 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
489 : value);
490 0 : tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
491 : EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
492 : value);
493 0 : if (!value) {
494 0 : tmp = REG_SET_FIELD(tmp,
495 : VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
496 : CRASH_ON_NO_RETRY_FAULT, 1);
497 0 : tmp = REG_SET_FIELD(tmp,
498 : VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
499 : CRASH_ON_RETRY_FAULT, 1);
500 : }
501 :
502 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
503 : mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
504 : i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
505 : }
506 0 : }
507 :
508 0 : static void mmhub_v9_4_init(struct amdgpu_device *adev)
509 : {
510 0 : struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
511 0 : {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
512 : int i;
513 :
514 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
515 0 : hub[i]->ctx0_ptb_addr_lo32 =
516 0 : SOC15_REG_OFFSET(MMHUB, 0,
517 0 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
518 0 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
519 0 : hub[i]->ctx0_ptb_addr_hi32 =
520 0 : SOC15_REG_OFFSET(MMHUB, 0,
521 0 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
522 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
523 0 : hub[i]->vm_inv_eng0_sem =
524 0 : SOC15_REG_OFFSET(MMHUB, 0,
525 0 : mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
526 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
527 0 : hub[i]->vm_inv_eng0_req =
528 0 : SOC15_REG_OFFSET(MMHUB, 0,
529 0 : mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
530 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
531 0 : hub[i]->vm_inv_eng0_ack =
532 0 : SOC15_REG_OFFSET(MMHUB, 0,
533 0 : mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
534 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
535 0 : hub[i]->vm_context0_cntl =
536 0 : SOC15_REG_OFFSET(MMHUB, 0,
537 0 : mmVML2VC0_VM_CONTEXT0_CNTL) +
538 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
539 0 : hub[i]->vm_l2_pro_fault_status =
540 0 : SOC15_REG_OFFSET(MMHUB, 0,
541 0 : mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
542 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
543 0 : hub[i]->vm_l2_pro_fault_cntl =
544 0 : SOC15_REG_OFFSET(MMHUB, 0,
545 0 : mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
546 : i * MMHUB_INSTANCE_REGISTER_OFFSET;
547 :
548 0 : hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL -
549 : mmVML2VC0_VM_CONTEXT0_CNTL;
550 0 : hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
551 : mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
552 0 : hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ -
553 : mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
554 0 : hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
555 : mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
556 : }
557 0 : }
558 :
559 0 : static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
560 : bool enable)
561 : {
562 : uint32_t def, data, def1, data1;
563 : int i, j;
564 0 : int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
565 :
566 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
567 0 : def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
568 : mmATCL2_0_ATC_L2_MISC_CG,
569 : i * MMHUB_INSTANCE_REGISTER_OFFSET);
570 :
571 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
572 0 : data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
573 : else
574 0 : data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
575 :
576 0 : if (def != data)
577 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
578 : i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
579 :
580 0 : for (j = 0; j < 5; j++) {
581 0 : def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
582 : mmDAGB0_CNTL_MISC2,
583 : i * MMHUB_INSTANCE_REGISTER_OFFSET +
584 : j * dist);
585 0 : if (enable &&
586 0 : (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
587 0 : data1 &=
588 : ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
589 : DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
590 : DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
591 : DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
592 : DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
593 : DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
594 : } else {
595 0 : data1 |=
596 : (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
597 : DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
598 : DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
599 : DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
600 : DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
601 : DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
602 : }
603 :
604 0 : if (def1 != data1)
605 0 : WREG32_SOC15_OFFSET(MMHUB, 0,
606 : mmDAGB0_CNTL_MISC2,
607 : i * MMHUB_INSTANCE_REGISTER_OFFSET +
608 : j * dist, data1);
609 :
610 0 : if (i == 1 && j == 3)
611 : break;
612 : }
613 : }
614 0 : }
615 :
616 0 : static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
617 : bool enable)
618 : {
619 : uint32_t def, data;
620 : int i;
621 :
622 0 : for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
623 0 : def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
624 : mmATCL2_0_ATC_L2_MISC_CG,
625 : i * MMHUB_INSTANCE_REGISTER_OFFSET);
626 :
627 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
628 0 : data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
629 : else
630 0 : data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
631 :
632 0 : if (def != data)
633 0 : WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
634 : i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
635 : }
636 0 : }
637 :
638 0 : static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
639 : enum amd_clockgating_state state)
640 : {
641 0 : if (amdgpu_sriov_vf(adev))
642 : return 0;
643 :
644 0 : switch (adev->asic_type) {
645 : case CHIP_ARCTURUS:
646 0 : mmhub_v9_4_update_medium_grain_clock_gating(adev,
647 : state == AMD_CG_STATE_GATE);
648 0 : mmhub_v9_4_update_medium_grain_light_sleep(adev,
649 : state == AMD_CG_STATE_GATE);
650 0 : break;
651 : default:
652 : break;
653 : }
654 :
655 : return 0;
656 : }
657 :
658 0 : static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags)
659 : {
660 : int data, data1;
661 :
662 0 : if (amdgpu_sriov_vf(adev))
663 0 : *flags = 0;
664 :
665 : /* AMD_CG_SUPPORT_MC_MGCG */
666 0 : data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
667 :
668 0 : data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
669 :
670 0 : if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
671 : !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
672 : DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
673 : DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
674 : DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
675 : DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
676 : DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
677 0 : *flags |= AMD_CG_SUPPORT_MC_MGCG;
678 :
679 : /* AMD_CG_SUPPORT_MC_LS */
680 0 : if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
681 0 : *flags |= AMD_CG_SUPPORT_MC_LS;
682 0 : }
683 :
684 : static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
685 : /* MMHUB Range 0 */
686 : { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
687 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
688 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
689 : },
690 : { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
691 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
692 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
693 : },
694 : { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
695 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
696 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
697 : },
698 : { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
699 : SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
700 : SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
701 : },
702 : { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
703 : SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
704 : SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
705 : },
706 : { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
707 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
708 : 0, 0,
709 : },
710 : { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
711 : SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
712 : 0, 0,
713 : },
714 : { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
715 : SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
716 : 0, 0,
717 : },
718 : { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
719 : SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
720 : 0, 0,
721 : },
722 : { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
723 : SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
724 : 0, 0,
725 : },
726 : { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
727 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
728 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
729 : },
730 : { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
731 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
732 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
733 : },
734 : { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
735 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
736 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
737 : },
738 : { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
739 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
740 : 0, 0,
741 : },
742 : { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
743 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
744 : 0, 0,
745 : },
746 : { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
747 : 0, 0,
748 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
749 : },
750 : { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
751 : 0, 0,
752 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
753 : },
754 : { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
755 : 0, 0,
756 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
757 : },
758 : { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
759 : 0, 0,
760 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
761 : },
762 : { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
763 : 0, 0,
764 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
765 : },
766 : { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
767 : 0, 0,
768 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
769 : },
770 : { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
771 : 0, 0,
772 : SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
773 : },
774 : { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
775 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
776 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
777 : },
778 : { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
779 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
780 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
781 : },
782 : { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
783 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
784 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
785 : },
786 : { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
787 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
788 : SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
789 : },
790 :
791 : /* MMHUB Range 1 */
792 : { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
793 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
794 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
795 : },
796 : { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
797 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
798 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
799 : },
800 : { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
801 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
802 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
803 : },
804 : { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
805 : SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
806 : SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
807 : },
808 : { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
809 : SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
810 : SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
811 : },
812 : { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
813 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
814 : 0, 0,
815 : },
816 : { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
817 : SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
818 : 0, 0,
819 : },
820 : { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
821 : SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
822 : 0, 0,
823 : },
824 : { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
825 : SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
826 : 0, 0,
827 : },
828 : { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
829 : SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
830 : 0, 0,
831 : },
832 : { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
833 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
834 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
835 : },
836 : { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
837 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
838 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
839 : },
840 : { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
841 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
842 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
843 : },
844 : { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
845 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
846 : 0, 0,
847 : },
848 : { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
849 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
850 : 0, 0,
851 : },
852 : { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
853 : 0, 0,
854 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
855 : },
856 : { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
857 : 0, 0,
858 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
859 : },
860 : { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
861 : 0, 0,
862 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
863 : },
864 : { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
865 : 0, 0,
866 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
867 : },
868 : { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
869 : 0, 0,
870 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
871 : },
872 : { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
873 : 0, 0,
874 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
875 : },
876 : { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
877 : 0, 0,
878 : SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
879 : },
880 : { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
881 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
882 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
883 : },
884 : { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
885 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
886 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
887 : },
888 : { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
889 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
890 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
891 : },
892 : { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
893 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
894 : SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
895 : },
896 :
897 : /* MMHAB Range 2*/
898 : { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
899 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
900 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
901 : },
902 : { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
903 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
904 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
905 : },
906 : { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
907 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
908 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
909 : },
910 : { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
911 : SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
912 : SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
913 : },
914 : { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
915 : SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
916 : SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
917 : },
918 : { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
919 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
920 : 0, 0,
921 : },
922 : { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
923 : SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
924 : 0, 0,
925 : },
926 : { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
927 : SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
928 : 0, 0,
929 : },
930 : { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
931 : SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
932 : 0, 0,
933 : },
934 : { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
935 : SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
936 : 0, 0,
937 : },
938 : { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
939 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
940 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
941 : },
942 : { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
943 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
944 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
945 : },
946 : { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
947 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
948 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
949 : },
950 : { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
951 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
952 : 0, 0,
953 : },
954 : { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
955 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
956 : 0, 0,
957 : },
958 : { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
959 : 0, 0,
960 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
961 : },
962 : { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
963 : 0, 0,
964 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
965 : },
966 : { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
967 : 0, 0,
968 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
969 : },
970 : { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
971 : 0, 0,
972 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
973 : },
974 : { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
975 : 0, 0,
976 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
977 : },
978 : { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
979 : 0, 0,
980 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
981 : },
982 : { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
983 : 0, 0,
984 : SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
985 : },
986 : { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
987 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
988 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
989 : },
990 : { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
991 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
992 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
993 : },
994 : { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
995 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
996 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
997 : },
998 : { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
999 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1000 : SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1001 : },
1002 :
1003 : /* MMHUB Rang 3 */
1004 : { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1005 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1006 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1007 : },
1008 : { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1009 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1010 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1011 : },
1012 : { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1013 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1014 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1015 : },
1016 : { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1017 : SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1018 : SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1019 : },
1020 : { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1021 : SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1022 : SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1023 : },
1024 : { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1025 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1026 : 0, 0,
1027 : },
1028 : { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1029 : SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1030 : 0, 0,
1031 : },
1032 : { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1033 : SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1034 : 0, 0,
1035 : },
1036 : { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1037 : SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1038 : 0, 0,
1039 : },
1040 : { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1041 : SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1042 : 0, 0,
1043 : },
1044 : { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1045 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1046 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1047 : },
1048 : { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1049 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1050 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1051 : },
1052 : { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1053 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1054 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1055 : },
1056 : { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1057 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1058 : 0, 0,
1059 : },
1060 : { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1061 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1062 : 0, 0,
1063 : },
1064 : { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1065 : 0, 0,
1066 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1067 : },
1068 : { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1069 : 0, 0,
1070 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1071 : },
1072 : { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1073 : 0, 0,
1074 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1075 : },
1076 : { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1077 : 0, 0,
1078 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1079 : },
1080 : { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1081 : 0, 0,
1082 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1083 : },
1084 : { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1085 : 0, 0,
1086 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1087 : },
1088 : { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1089 : 0, 0,
1090 : SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1091 : },
1092 : { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1093 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1094 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1095 : },
1096 : { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1097 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1098 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1099 : },
1100 : { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1101 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1102 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1103 : },
1104 : { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1105 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1106 : SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1107 : },
1108 :
1109 : /* MMHUB Range 4 */
1110 : { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1111 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1112 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1113 : },
1114 : { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1115 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1116 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1117 : },
1118 : { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1119 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1120 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1121 : },
1122 : { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1123 : SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1124 : SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1125 : },
1126 : { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1127 : SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1128 : SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1129 : },
1130 : { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1131 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1132 : 0, 0,
1133 : },
1134 : { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1135 : SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1136 : 0, 0,
1137 : },
1138 : { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1139 : SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1140 : 0, 0,
1141 : },
1142 : { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1143 : SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1144 : 0, 0,
1145 : },
1146 : { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1147 : SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1148 : 0, 0,
1149 : },
1150 : { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1151 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1152 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1153 : },
1154 : { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1155 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1156 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1157 : },
1158 : { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1159 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1160 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1161 : },
1162 : { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1163 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1164 : 0, 0,
1165 : },
1166 : { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1167 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1168 : 0, 0,
1169 : },
1170 : { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1171 : 0, 0,
1172 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1173 : },
1174 : { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1175 : 0, 0,
1176 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1177 : },
1178 : { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1179 : 0, 0,
1180 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1181 : },
1182 : { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1183 : 0, 0,
1184 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1185 : },
1186 : { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1187 : 0, 0,
1188 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1189 : },
1190 : { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1191 : 0, 0,
1192 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1193 : },
1194 : { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1195 : 0, 0,
1196 : SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1197 : },
1198 : { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1199 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1200 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1201 : },
1202 : { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1203 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1204 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1205 : },
1206 : { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1207 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1208 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1209 : },
1210 : { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1211 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1212 : SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1213 : },
1214 :
1215 : /* MMHUAB Range 5 */
1216 : { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1217 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1218 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1219 : },
1220 : { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1221 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1222 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1223 : },
1224 : { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1225 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1226 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1227 : },
1228 : { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1229 : SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1230 : SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1231 : },
1232 : { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1233 : SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1234 : SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1235 : },
1236 : { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1237 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1238 : 0, 0,
1239 : },
1240 : { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1241 : SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1242 : 0, 0,
1243 : },
1244 : { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1245 : SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1246 : 0, 0,
1247 : },
1248 : { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1249 : SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1250 : 0, 0,
1251 : },
1252 : { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1253 : SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1254 : 0, 0,
1255 : },
1256 : { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1257 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1258 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1259 : },
1260 : { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1261 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1262 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1263 : },
1264 : { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1265 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1266 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1267 : },
1268 : { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1269 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1270 : 0, 0,
1271 : },
1272 : { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1273 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1274 : 0, 0,
1275 : },
1276 : { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1277 : 0, 0,
1278 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1279 : },
1280 : { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1281 : 0, 0,
1282 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1283 : },
1284 : { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1285 : 0, 0,
1286 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1287 : },
1288 : { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1289 : 0, 0,
1290 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1291 : },
1292 : { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1293 : 0, 0,
1294 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1295 : },
1296 : { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1297 : 0, 0,
1298 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1299 : },
1300 : { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1301 : 0, 0,
1302 : SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1303 : },
1304 : { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1305 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1306 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1307 : },
1308 : { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1309 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1310 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1311 : },
1312 : { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1313 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1314 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1315 : },
1316 : { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1317 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1318 : SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1319 : },
1320 :
1321 : /* MMHUB Range 6 */
1322 : { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1323 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1324 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1325 : },
1326 : { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1327 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1328 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1329 : },
1330 : { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1331 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1332 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1333 : },
1334 : { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1335 : SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1336 : SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1337 : },
1338 : { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1339 : SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1340 : SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1341 : },
1342 : { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1343 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1344 : 0, 0,
1345 : },
1346 : { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1347 : SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1348 : 0, 0,
1349 : },
1350 : { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1351 : SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1352 : 0, 0,
1353 : },
1354 : { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1355 : SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1356 : 0, 0,
1357 : },
1358 : { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1359 : SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1360 : 0, 0,
1361 : },
1362 : { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1363 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1364 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1365 : },
1366 : { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1367 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1368 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1369 : },
1370 : { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1371 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1372 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1373 : },
1374 : { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1375 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1376 : 0, 0,
1377 : },
1378 : { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1379 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1380 : 0, 0,
1381 : },
1382 : { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1383 : 0, 0,
1384 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1385 : },
1386 : { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1387 : 0, 0,
1388 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1389 : },
1390 : { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1391 : 0, 0,
1392 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1393 : },
1394 : { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1395 : 0, 0,
1396 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1397 : },
1398 : { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1399 : 0, 0,
1400 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1401 : },
1402 : { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1403 : 0, 0,
1404 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1405 : },
1406 : { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1407 : 0, 0,
1408 : SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1409 : },
1410 : { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1411 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1412 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1413 : },
1414 : { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1415 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1416 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1417 : },
1418 : { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1419 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1420 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1421 : },
1422 : { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1423 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1424 : SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1425 : },
1426 :
1427 : /* MMHUB Range 7*/
1428 : { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1429 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1430 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1431 : },
1432 : { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1433 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1434 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1435 : },
1436 : { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1437 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1438 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1439 : },
1440 : { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1441 : SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1442 : SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1443 : },
1444 : { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1445 : SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1446 : SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1447 : },
1448 : { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1449 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1450 : 0, 0,
1451 : },
1452 : { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1453 : SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1454 : 0, 0,
1455 : },
1456 : { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1457 : SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1458 : 0, 0,
1459 : },
1460 : { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1461 : SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1462 : 0, 0,
1463 : },
1464 : { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1465 : SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1466 : 0, 0,
1467 : },
1468 : { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1469 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1470 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1471 : },
1472 : { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1473 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1474 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1475 : },
1476 : { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1477 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1478 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1479 : },
1480 : { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1481 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1482 : 0, 0,
1483 : },
1484 : { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1485 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1486 : 0, 0,
1487 : },
1488 : { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1489 : 0, 0,
1490 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1491 : },
1492 : { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1493 : 0, 0,
1494 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1495 : },
1496 : { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1497 : 0, 0,
1498 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1499 : },
1500 : { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1501 : 0, 0,
1502 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1503 : },
1504 : { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1505 : 0, 0,
1506 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1507 : },
1508 : { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1509 : 0, 0,
1510 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1511 : },
1512 : { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1513 : 0, 0,
1514 : SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1515 : },
1516 : { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1517 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1518 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1519 : },
1520 : { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1521 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1522 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1523 : },
1524 : { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1525 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1526 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1527 : },
1528 : { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1529 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1530 : SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1531 : }
1532 : };
1533 :
1534 : static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1535 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1536 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1537 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1538 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1539 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1540 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1541 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1542 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1543 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1544 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1545 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1546 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1547 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1548 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1549 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1550 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1551 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1552 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1553 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1554 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1555 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1556 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1557 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1558 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1559 : };
1560 :
1561 0 : static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1562 : const struct soc15_reg_entry *reg,
1563 : uint32_t value,
1564 : uint32_t *sec_count,
1565 : uint32_t *ded_count)
1566 : {
1567 : uint32_t i;
1568 : uint32_t sec_cnt, ded_cnt;
1569 :
1570 0 : for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1571 0 : if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1572 0 : continue;
1573 :
1574 0 : sec_cnt = (value &
1575 0 : mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1576 0 : mmhub_v9_4_ras_fields[i].sec_count_shift;
1577 0 : if (sec_cnt) {
1578 0 : dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1579 : mmhub_v9_4_ras_fields[i].name,
1580 : sec_cnt);
1581 0 : *sec_count += sec_cnt;
1582 : }
1583 :
1584 0 : ded_cnt = (value &
1585 0 : mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1586 0 : mmhub_v9_4_ras_fields[i].ded_count_shift;
1587 0 : if (ded_cnt) {
1588 0 : dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1589 : mmhub_v9_4_ras_fields[i].name,
1590 : ded_cnt);
1591 0 : *ded_count += ded_cnt;
1592 : }
1593 : }
1594 :
1595 0 : return 0;
1596 : }
1597 :
1598 0 : static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1599 : void *ras_error_status)
1600 : {
1601 0 : struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1602 0 : uint32_t sec_count = 0, ded_count = 0;
1603 : uint32_t i;
1604 : uint32_t reg_value;
1605 :
1606 0 : err_data->ue_count = 0;
1607 0 : err_data->ce_count = 0;
1608 :
1609 0 : for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1610 0 : reg_value =
1611 0 : RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1612 0 : if (reg_value)
1613 0 : mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1614 : reg_value, &sec_count, &ded_count);
1615 : }
1616 :
1617 0 : err_data->ce_count += sec_count;
1618 0 : err_data->ue_count += ded_count;
1619 0 : }
1620 :
1621 0 : static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1622 : {
1623 : uint32_t i;
1624 :
1625 : /* read back edc counter registers to reset the counters to 0 */
1626 0 : if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1627 0 : for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1628 0 : RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1629 : }
1630 0 : }
1631 :
1632 : static const struct soc15_reg_entry mmhub_v9_4_err_status_regs[] = {
1633 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_ERR_STATUS), 0, 0, 0 },
1634 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_ERR_STATUS), 0, 0, 0 },
1635 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_ERR_STATUS), 0, 0, 0 },
1636 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_ERR_STATUS), 0, 0, 0 },
1637 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_ERR_STATUS), 0, 0, 0 },
1638 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_ERR_STATUS), 0, 0, 0 },
1639 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_ERR_STATUS), 0, 0, 0 },
1640 : { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_ERR_STATUS), 0, 0, 0 },
1641 : };
1642 :
1643 0 : static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev)
1644 : {
1645 : int i;
1646 : uint32_t reg_value;
1647 :
1648 0 : if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1649 : return;
1650 :
1651 0 : for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) {
1652 0 : reg_value =
1653 0 : RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));
1654 0 : if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1655 0 : REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1656 : REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1657 : /* SDP read/write error/parity error in FUE_IS_FATAL mode
1658 : * can cause system fatal error in arcturas. Harvest the error
1659 : * status before GPU reset */
1660 0 : dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1661 : i, reg_value);
1662 : }
1663 : }
1664 : }
1665 :
1666 : const struct amdgpu_ras_block_hw_ops mmhub_v9_4_ras_hw_ops = {
1667 : .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1668 : .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1669 : .query_ras_error_status = mmhub_v9_4_query_ras_error_status,
1670 : };
1671 :
1672 : struct amdgpu_mmhub_ras mmhub_v9_4_ras = {
1673 : .ras_block = {
1674 : .hw_ops = &mmhub_v9_4_ras_hw_ops,
1675 : },
1676 : };
1677 :
1678 : const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1679 : .get_fb_location = mmhub_v9_4_get_fb_location,
1680 : .init = mmhub_v9_4_init,
1681 : .gart_enable = mmhub_v9_4_gart_enable,
1682 : .set_fault_enable_default = mmhub_v9_4_set_fault_enable_default,
1683 : .gart_disable = mmhub_v9_4_gart_disable,
1684 : .set_clockgating = mmhub_v9_4_set_clockgating,
1685 : .get_clockgating = mmhub_v9_4_get_clockgating,
1686 : .setup_vm_pt_regs = mmhub_v9_4_setup_vm_pt_regs,
1687 : };
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