Line data Source code
1 : /*
2 : * Copyright 2014 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include "amdgpu.h"
25 : #include "nbio/nbio_6_1_offset.h"
26 : #include "nbio/nbio_6_1_sh_mask.h"
27 : #include "gc/gc_9_0_offset.h"
28 : #include "gc/gc_9_0_sh_mask.h"
29 : #include "mp/mp_9_0_offset.h"
30 : #include "soc15.h"
31 : #include "vega10_ih.h"
32 : #include "soc15_common.h"
33 : #include "mxgpu_ai.h"
34 :
35 : #include "amdgpu_reset.h"
36 :
37 : static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
38 : {
39 0 : WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
40 : }
41 :
42 : static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
43 : {
44 0 : WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
45 : }
46 :
47 : /*
48 : * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
49 : * RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1
50 : * by host.
51 : *
52 : * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
53 : * correct value since it doesn't return the RCV_DW0 under the case that
54 : * RCV_MSG_VALID is set by host.
55 : */
56 : static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev)
57 : {
58 0 : return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
59 : mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
60 : }
61 :
62 :
63 0 : static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,
64 : enum idh_event event)
65 : {
66 : u32 reg;
67 :
68 0 : reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
69 : mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
70 0 : if (reg != event)
71 : return -ENOENT;
72 :
73 0 : xgpu_ai_mailbox_send_ack(adev);
74 :
75 0 : return 0;
76 : }
77 :
78 : static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {
79 0 : return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
80 : }
81 :
82 0 : static int xgpu_ai_poll_ack(struct amdgpu_device *adev)
83 : {
84 0 : int timeout = AI_MAILBOX_POLL_ACK_TIMEDOUT;
85 : u8 reg;
86 :
87 : do {
88 0 : reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
89 0 : if (reg & 2)
90 : return 0;
91 :
92 0 : mdelay(5);
93 0 : timeout -= 5;
94 0 : } while (timeout > 1);
95 :
96 0 : pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);
97 :
98 0 : return -ETIME;
99 : }
100 :
101 0 : static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
102 : {
103 0 : int r, timeout = AI_MAILBOX_POLL_MSG_TIMEDOUT;
104 :
105 : do {
106 0 : r = xgpu_ai_mailbox_rcv_msg(adev, event);
107 0 : if (!r)
108 : return 0;
109 :
110 0 : msleep(10);
111 0 : timeout -= 10;
112 0 : } while (timeout > 1);
113 :
114 0 : pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
115 :
116 0 : return -ETIME;
117 : }
118 :
119 0 : static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
120 : enum idh_request req, u32 data1, u32 data2, u32 data3) {
121 : u32 reg;
122 : int r;
123 : uint8_t trn;
124 :
125 : /* IMPORTANT:
126 : * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
127 : * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
128 : * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_ai_poll_ack()
129 : * will return immediatly
130 : */
131 : do {
132 0 : xgpu_ai_mailbox_set_valid(adev, false);
133 0 : trn = xgpu_ai_peek_ack(adev);
134 0 : if (trn) {
135 0 : pr_err("trn=%x ACK should not assert! wait again !\n", trn);
136 0 : msleep(1);
137 : }
138 0 : } while(trn);
139 :
140 0 : reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
141 : mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
142 0 : reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
143 : MSGBUF_DATA, req);
144 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
145 : reg);
146 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
147 : data1);
148 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
149 : data2);
150 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
151 : data3);
152 :
153 0 : xgpu_ai_mailbox_set_valid(adev, true);
154 :
155 : /* start to poll ack */
156 0 : r = xgpu_ai_poll_ack(adev);
157 0 : if (r)
158 0 : pr_err("Doesn't get ack from pf, continue\n");
159 :
160 0 : xgpu_ai_mailbox_set_valid(adev, false);
161 0 : }
162 :
163 0 : static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
164 : enum idh_request req)
165 : {
166 : int r;
167 :
168 0 : xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);
169 :
170 : /* start to check msg if request is idh_req_gpu_init_access */
171 0 : if (req == IDH_REQ_GPU_INIT_ACCESS ||
172 0 : req == IDH_REQ_GPU_FINI_ACCESS ||
173 : req == IDH_REQ_GPU_RESET_ACCESS) {
174 0 : r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
175 0 : if (r) {
176 0 : pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
177 0 : return r;
178 : }
179 : /* Retrieve checksum from mailbox2 */
180 0 : if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
181 0 : adev->virt.fw_reserve.checksum_key =
182 0 : RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
183 : mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
184 : }
185 0 : } else if (req == IDH_REQ_GPU_INIT_DATA){
186 : /* Dummy REQ_GPU_INIT_DATA handling */
187 0 : r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
188 : /* version set to 0 since dummy */
189 0 : adev->virt.req_init_data_ver = 0;
190 : }
191 :
192 : return 0;
193 : }
194 :
195 0 : static int xgpu_ai_request_reset(struct amdgpu_device *adev)
196 : {
197 0 : int ret, i = 0;
198 :
199 0 : while (i < AI_MAILBOX_POLL_MSG_REP_MAX) {
200 0 : ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
201 0 : if (!ret)
202 : break;
203 0 : i++;
204 : }
205 :
206 0 : return ret;
207 : }
208 :
209 0 : static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,
210 : bool init)
211 : {
212 : enum idh_request req;
213 :
214 0 : req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
215 0 : return xgpu_ai_send_access_requests(adev, req);
216 : }
217 :
218 0 : static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,
219 : bool init)
220 : {
221 : enum idh_request req;
222 0 : int r = 0;
223 :
224 0 : req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
225 0 : r = xgpu_ai_send_access_requests(adev, req);
226 :
227 0 : return r;
228 : }
229 :
230 0 : static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
231 : struct amdgpu_irq_src *source,
232 : struct amdgpu_iv_entry *entry)
233 : {
234 0 : DRM_DEBUG("get ack intr and do nothing.\n");
235 0 : return 0;
236 : }
237 :
238 0 : static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,
239 : struct amdgpu_irq_src *source,
240 : unsigned type,
241 : enum amdgpu_interrupt_state state)
242 : {
243 0 : u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
244 :
245 0 : tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
246 : (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
247 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
248 :
249 0 : return 0;
250 : }
251 :
252 0 : static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
253 : {
254 0 : struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
255 0 : struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
256 0 : int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;
257 :
258 : /* block amdgpu_gpu_recover till msg FLR COMPLETE received,
259 : * otherwise the mailbox msg will be ruined/reseted by
260 : * the VF FLR.
261 : */
262 0 : if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
263 : return;
264 :
265 0 : down_write(&adev->reset_domain->sem);
266 :
267 0 : amdgpu_virt_fini_data_exchange(adev);
268 :
269 0 : xgpu_ai_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
270 :
271 : do {
272 0 : if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
273 : goto flr_done;
274 :
275 0 : msleep(10);
276 0 : timeout -= 10;
277 0 : } while (timeout > 1);
278 :
279 : flr_done:
280 0 : atomic_set(&adev->reset_domain->in_gpu_reset, 0);
281 0 : up_write(&adev->reset_domain->sem);
282 :
283 : /* Trigger recovery for world switch failure if no TDR */
284 0 : if (amdgpu_device_should_recover_gpu(adev)
285 0 : && (!amdgpu_device_has_job_running(adev) ||
286 0 : adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)) {
287 : struct amdgpu_reset_context reset_context;
288 0 : memset(&reset_context, 0, sizeof(reset_context));
289 :
290 0 : reset_context.method = AMD_RESET_METHOD_NONE;
291 0 : reset_context.reset_req_dev = adev;
292 0 : clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
293 0 : clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
294 :
295 0 : amdgpu_device_gpu_recover(adev, NULL, &reset_context);
296 : }
297 : }
298 :
299 0 : static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
300 : struct amdgpu_irq_src *src,
301 : unsigned type,
302 : enum amdgpu_interrupt_state state)
303 : {
304 0 : u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
305 :
306 0 : tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
307 : (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
308 0 : WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
309 :
310 0 : return 0;
311 : }
312 :
313 0 : static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
314 : struct amdgpu_irq_src *source,
315 : struct amdgpu_iv_entry *entry)
316 : {
317 0 : enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);
318 :
319 0 : switch (event) {
320 : case IDH_FLR_NOTIFICATION:
321 0 : if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev))
322 0 : WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
323 : &adev->virt.flr_work),
324 : "Failed to queue work! at %s",
325 : __func__);
326 : break;
327 : case IDH_QUERY_ALIVE:
328 : xgpu_ai_mailbox_send_ack(adev);
329 : break;
330 : /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
331 : * it byfar since that polling thread will handle it,
332 : * other msg like flr complete is not handled here.
333 : */
334 : case IDH_CLR_MSG_BUF:
335 : case IDH_FLR_NOTIFICATION_CMPL:
336 : case IDH_READY_TO_ACCESS_GPU:
337 : default:
338 : break;
339 : }
340 :
341 0 : return 0;
342 : }
343 :
344 : static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = {
345 : .set = xgpu_ai_set_mailbox_ack_irq,
346 : .process = xgpu_ai_mailbox_ack_irq,
347 : };
348 :
349 : static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = {
350 : .set = xgpu_ai_set_mailbox_rcv_irq,
351 : .process = xgpu_ai_mailbox_rcv_irq,
352 : };
353 :
354 0 : void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)
355 : {
356 0 : adev->virt.ack_irq.num_types = 1;
357 0 : adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;
358 0 : adev->virt.rcv_irq.num_types = 1;
359 0 : adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;
360 0 : }
361 :
362 0 : int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
363 : {
364 : int r;
365 :
366 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
367 0 : if (r)
368 : return r;
369 :
370 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
371 0 : if (r) {
372 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
373 0 : return r;
374 : }
375 :
376 : return 0;
377 : }
378 :
379 0 : int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)
380 : {
381 : int r;
382 :
383 0 : r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
384 0 : if (r)
385 : return r;
386 0 : r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
387 0 : if (r) {
388 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
389 0 : return r;
390 : }
391 :
392 0 : INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);
393 :
394 0 : return 0;
395 : }
396 :
397 0 : void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
398 : {
399 0 : amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
400 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
401 0 : }
402 :
403 0 : static int xgpu_ai_request_init_data(struct amdgpu_device *adev)
404 : {
405 0 : return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);
406 : }
407 :
408 : const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
409 : .req_full_gpu = xgpu_ai_request_full_gpu_access,
410 : .rel_full_gpu = xgpu_ai_release_full_gpu_access,
411 : .reset_gpu = xgpu_ai_request_reset,
412 : .wait_reset = NULL,
413 : .trans_msg = xgpu_ai_mailbox_trans_msg,
414 : .req_init_data = xgpu_ai_request_init_data,
415 : };
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