Line data Source code
1 : /*
2 : * Copyright 2014 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include "amdgpu.h"
25 : #include "nbio/nbio_2_3_offset.h"
26 : #include "nbio/nbio_2_3_sh_mask.h"
27 : #include "gc/gc_10_1_0_offset.h"
28 : #include "gc/gc_10_1_0_sh_mask.h"
29 : #include "soc15.h"
30 : #include "navi10_ih.h"
31 : #include "soc15_common.h"
32 : #include "mxgpu_nv.h"
33 :
34 : #include "amdgpu_reset.h"
35 :
36 : static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
37 : {
38 0 : WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
39 : }
40 :
41 : static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val)
42 : {
43 0 : WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
44 : }
45 :
46 : /*
47 : * this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
48 : * RCV_MSG_VALID filed of BIF_BX_PF_MAILBOX_CONTROL must already be set to 1
49 : * by host.
50 : *
51 : * if called no in IRQ routine, this peek_msg cannot guaranteed to return the
52 : * correct value since it doesn't return the RCV_DW0 under the case that
53 : * RCV_MSG_VALID is set by host.
54 : */
55 : static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev)
56 : {
57 0 : return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
58 : }
59 :
60 :
61 0 : static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev,
62 : enum idh_event event)
63 : {
64 : u32 reg;
65 :
66 0 : reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);
67 0 : if (reg != event)
68 : return -ENOENT;
69 :
70 0 : xgpu_nv_mailbox_send_ack(adev);
71 :
72 0 : return 0;
73 : }
74 :
75 : static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev)
76 : {
77 0 : return RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
78 : }
79 :
80 0 : static int xgpu_nv_poll_ack(struct amdgpu_device *adev)
81 : {
82 0 : int timeout = NV_MAILBOX_POLL_ACK_TIMEDOUT;
83 : u8 reg;
84 :
85 : do {
86 0 : reg = RREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
87 0 : if (reg & 2)
88 : return 0;
89 :
90 0 : mdelay(5);
91 0 : timeout -= 5;
92 0 : } while (timeout > 1);
93 :
94 0 : pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", NV_MAILBOX_POLL_ACK_TIMEDOUT);
95 :
96 0 : return -ETIME;
97 : }
98 :
99 0 : static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event)
100 : {
101 : int r;
102 : uint64_t timeout, now;
103 :
104 0 : now = (uint64_t)ktime_to_ms(ktime_get());
105 0 : timeout = now + NV_MAILBOX_POLL_MSG_TIMEDOUT;
106 :
107 : do {
108 0 : r = xgpu_nv_mailbox_rcv_msg(adev, event);
109 0 : if (!r)
110 : return 0;
111 :
112 0 : msleep(10);
113 0 : now = (uint64_t)ktime_to_ms(ktime_get());
114 0 : } while (timeout > now);
115 :
116 :
117 : return -ETIME;
118 : }
119 :
120 0 : static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev,
121 : enum idh_request req, u32 data1, u32 data2, u32 data3)
122 : {
123 : int r;
124 : uint8_t trn;
125 :
126 : /* IMPORTANT:
127 : * clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
128 : * and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
129 : * which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_nv_poll_ack()
130 : * will return immediatly
131 : */
132 : do {
133 0 : xgpu_nv_mailbox_set_valid(adev, false);
134 0 : trn = xgpu_nv_peek_ack(adev);
135 0 : if (trn) {
136 0 : pr_err("trn=%x ACK should not assert! wait again !\n", trn);
137 0 : msleep(1);
138 : }
139 0 : } while (trn);
140 :
141 0 : WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);
142 0 : WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);
143 0 : WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);
144 0 : WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3);
145 0 : xgpu_nv_mailbox_set_valid(adev, true);
146 :
147 : /* start to poll ack */
148 0 : r = xgpu_nv_poll_ack(adev);
149 0 : if (r)
150 0 : pr_err("Doesn't get ack from pf, continue\n");
151 :
152 0 : xgpu_nv_mailbox_set_valid(adev, false);
153 0 : }
154 :
155 0 : static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,
156 : enum idh_request req)
157 : {
158 0 : int r, retry = 1;
159 0 : enum idh_event event = -1;
160 :
161 : send_request:
162 0 : xgpu_nv_mailbox_trans_msg(adev, req, 0, 0, 0);
163 :
164 0 : switch (req) {
165 : case IDH_REQ_GPU_INIT_ACCESS:
166 : case IDH_REQ_GPU_FINI_ACCESS:
167 : case IDH_REQ_GPU_RESET_ACCESS:
168 0 : event = IDH_READY_TO_ACCESS_GPU;
169 0 : break;
170 : case IDH_REQ_GPU_INIT_DATA:
171 0 : event = IDH_REQ_GPU_INIT_DATA_READY;
172 0 : break;
173 : default:
174 : break;
175 : }
176 :
177 0 : if (event != -1) {
178 0 : r = xgpu_nv_poll_msg(adev, event);
179 0 : if (r) {
180 0 : if (retry++ < 2)
181 : goto send_request;
182 :
183 0 : if (req != IDH_REQ_GPU_INIT_DATA) {
184 0 : pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
185 0 : return r;
186 : }
187 : else /* host doesn't support REQ_GPU_INIT_DATA handshake */
188 0 : adev->virt.req_init_data_ver = 0;
189 : } else {
190 0 : if (req == IDH_REQ_GPU_INIT_DATA)
191 : {
192 0 : adev->virt.req_init_data_ver =
193 0 : RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);
194 :
195 : /* assume V1 in case host doesn't set version number */
196 0 : if (adev->virt.req_init_data_ver < 1)
197 0 : adev->virt.req_init_data_ver = 1;
198 : }
199 : }
200 :
201 : /* Retrieve checksum from mailbox2 */
202 0 : if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
203 0 : adev->virt.fw_reserve.checksum_key =
204 0 : RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);
205 : }
206 : }
207 :
208 : return 0;
209 : }
210 :
211 0 : static int xgpu_nv_request_reset(struct amdgpu_device *adev)
212 : {
213 0 : int ret, i = 0;
214 :
215 0 : while (i < NV_MAILBOX_POLL_MSG_REP_MAX) {
216 0 : ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
217 0 : if (!ret)
218 : break;
219 0 : i++;
220 : }
221 :
222 0 : return ret;
223 : }
224 :
225 0 : static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,
226 : bool init)
227 : {
228 : enum idh_request req;
229 :
230 0 : req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
231 0 : return xgpu_nv_send_access_requests(adev, req);
232 : }
233 :
234 0 : static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev,
235 : bool init)
236 : {
237 : enum idh_request req;
238 0 : int r = 0;
239 :
240 0 : req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
241 0 : r = xgpu_nv_send_access_requests(adev, req);
242 :
243 0 : return r;
244 : }
245 :
246 0 : static int xgpu_nv_request_init_data(struct amdgpu_device *adev)
247 : {
248 0 : return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);
249 : }
250 :
251 0 : static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,
252 : struct amdgpu_irq_src *source,
253 : struct amdgpu_iv_entry *entry)
254 : {
255 0 : DRM_DEBUG("get ack intr and do nothing.\n");
256 0 : return 0;
257 : }
258 :
259 0 : static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev,
260 : struct amdgpu_irq_src *source,
261 : unsigned type,
262 : enum amdgpu_interrupt_state state)
263 : {
264 0 : u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
265 :
266 0 : if (state == AMDGPU_IRQ_STATE_ENABLE)
267 0 : tmp |= 2;
268 : else
269 0 : tmp &= ~2;
270 :
271 0 : WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
272 :
273 0 : return 0;
274 : }
275 :
276 0 : static void xgpu_nv_mailbox_flr_work(struct work_struct *work)
277 : {
278 0 : struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
279 0 : struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
280 0 : int timeout = NV_MAILBOX_POLL_FLR_TIMEDOUT;
281 :
282 : /* block amdgpu_gpu_recover till msg FLR COMPLETE received,
283 : * otherwise the mailbox msg will be ruined/reseted by
284 : * the VF FLR.
285 : */
286 0 : if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
287 : return;
288 :
289 0 : down_write(&adev->reset_domain->sem);
290 :
291 0 : amdgpu_virt_fini_data_exchange(adev);
292 :
293 0 : xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0);
294 :
295 : do {
296 0 : if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
297 : goto flr_done;
298 :
299 0 : msleep(10);
300 0 : timeout -= 10;
301 0 : } while (timeout > 1);
302 :
303 : flr_done:
304 0 : atomic_set(&adev->reset_domain->in_gpu_reset, 0);
305 0 : up_write(&adev->reset_domain->sem);
306 :
307 : /* Trigger recovery for world switch failure if no TDR */
308 0 : if (amdgpu_device_should_recover_gpu(adev)
309 0 : && (!amdgpu_device_has_job_running(adev) ||
310 0 : adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT ||
311 0 : adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
312 0 : adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
313 0 : adev->video_timeout == MAX_SCHEDULE_TIMEOUT)) {
314 : struct amdgpu_reset_context reset_context;
315 0 : memset(&reset_context, 0, sizeof(reset_context));
316 :
317 0 : reset_context.method = AMD_RESET_METHOD_NONE;
318 0 : reset_context.reset_req_dev = adev;
319 0 : clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
320 0 : clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
321 :
322 0 : amdgpu_device_gpu_recover(adev, NULL, &reset_context);
323 : }
324 : }
325 :
326 0 : static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
327 : struct amdgpu_irq_src *src,
328 : unsigned type,
329 : enum amdgpu_interrupt_state state)
330 : {
331 0 : u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
332 :
333 0 : if (state == AMDGPU_IRQ_STATE_ENABLE)
334 0 : tmp |= 1;
335 : else
336 0 : tmp &= ~1;
337 :
338 0 : WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
339 :
340 0 : return 0;
341 : }
342 :
343 0 : static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev,
344 : struct amdgpu_irq_src *source,
345 : struct amdgpu_iv_entry *entry)
346 : {
347 0 : enum idh_event event = xgpu_nv_mailbox_peek_msg(adev);
348 :
349 0 : switch (event) {
350 : case IDH_FLR_NOTIFICATION:
351 0 : if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev))
352 0 : WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
353 : &adev->virt.flr_work),
354 : "Failed to queue work! at %s",
355 : __func__);
356 : break;
357 : /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
358 : * it byfar since that polling thread will handle it,
359 : * other msg like flr complete is not handled here.
360 : */
361 : case IDH_CLR_MSG_BUF:
362 : case IDH_FLR_NOTIFICATION_CMPL:
363 : case IDH_READY_TO_ACCESS_GPU:
364 : default:
365 : break;
366 : }
367 :
368 0 : return 0;
369 : }
370 :
371 : static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_ack_irq_funcs = {
372 : .set = xgpu_nv_set_mailbox_ack_irq,
373 : .process = xgpu_nv_mailbox_ack_irq,
374 : };
375 :
376 : static const struct amdgpu_irq_src_funcs xgpu_nv_mailbox_rcv_irq_funcs = {
377 : .set = xgpu_nv_set_mailbox_rcv_irq,
378 : .process = xgpu_nv_mailbox_rcv_irq,
379 : };
380 :
381 0 : void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev)
382 : {
383 0 : adev->virt.ack_irq.num_types = 1;
384 0 : adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;
385 0 : adev->virt.rcv_irq.num_types = 1;
386 0 : adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;
387 0 : }
388 :
389 0 : int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev)
390 : {
391 : int r;
392 :
393 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
394 0 : if (r)
395 : return r;
396 :
397 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
398 0 : if (r) {
399 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
400 0 : return r;
401 : }
402 :
403 : return 0;
404 : }
405 :
406 0 : int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev)
407 : {
408 : int r;
409 :
410 0 : r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
411 0 : if (r)
412 : return r;
413 0 : r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
414 0 : if (r) {
415 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
416 0 : return r;
417 : }
418 :
419 0 : INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);
420 :
421 0 : return 0;
422 : }
423 :
424 0 : void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev)
425 : {
426 0 : amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
427 0 : amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
428 0 : }
429 :
430 : const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
431 : .req_full_gpu = xgpu_nv_request_full_gpu_access,
432 : .rel_full_gpu = xgpu_nv_release_full_gpu_access,
433 : .req_init_data = xgpu_nv_request_init_data,
434 : .reset_gpu = xgpu_nv_request_reset,
435 : .wait_reset = NULL,
436 : .trans_msg = xgpu_nv_mailbox_trans_msg,
437 : };
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