Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_atombios.h"
25 : #include "nbio_v2_3.h"
26 :
27 : #include "nbio/nbio_2_3_default.h"
28 : #include "nbio/nbio_2_3_offset.h"
29 : #include "nbio/nbio_2_3_sh_mask.h"
30 : #include <uapi/linux/kfd_ioctl.h>
31 : #include <linux/pci.h>
32 :
33 : #define smnPCIE_CONFIG_CNTL 0x11180044
34 : #define smnCPM_CONTROL 0x11180460
35 : #define smnPCIE_CNTL2 0x11180070
36 : #define smnPCIE_LC_CNTL 0x11140280
37 : #define smnPCIE_LC_CNTL3 0x111402d4
38 : #define smnPCIE_LC_CNTL6 0x111402ec
39 : #define smnPCIE_LC_CNTL7 0x111402f0
40 : #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
41 : #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
42 : #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
43 : #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
44 : #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
45 :
46 : #define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6
47 : #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2
48 : #define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7
49 : #define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2
50 :
51 : #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8
52 : #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
53 :
54 : #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
55 :
56 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */
57 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
58 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
59 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
60 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
61 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
62 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
63 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
64 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
65 :
66 0 : static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
67 : {
68 0 : WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
69 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
70 0 : WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
71 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
72 0 : }
73 :
74 0 : static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
75 : {
76 : u32 tmp;
77 :
78 : /*
79 : * guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
80 : * therefore we force rev_id to 0 (which is the default value)
81 : */
82 0 : if (amdgpu_sriov_vf(adev)) {
83 : return 0;
84 : }
85 :
86 0 : tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
87 0 : tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
88 0 : tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
89 :
90 0 : return tmp;
91 : }
92 :
93 0 : static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
94 : {
95 0 : if (enable)
96 0 : WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
97 : BIF_FB_EN__FB_READ_EN_MASK |
98 : BIF_FB_EN__FB_WRITE_EN_MASK);
99 : else
100 0 : WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
101 0 : }
102 :
103 0 : static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
104 : {
105 0 : return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
106 : }
107 :
108 0 : static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
109 : bool use_doorbell, int doorbell_index,
110 : int doorbell_size)
111 : {
112 0 : u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
113 0 : instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) :
114 0 : instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) :
115 0 : SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE);
116 :
117 0 : u32 doorbell_range = RREG32(reg);
118 :
119 0 : if (use_doorbell) {
120 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
121 : BIF_SDMA0_DOORBELL_RANGE, OFFSET,
122 : doorbell_index);
123 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
124 : BIF_SDMA0_DOORBELL_RANGE, SIZE,
125 : doorbell_size);
126 : } else
127 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
128 : BIF_SDMA0_DOORBELL_RANGE, SIZE,
129 : 0);
130 :
131 0 : WREG32(reg, doorbell_range);
132 0 : }
133 :
134 0 : static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
135 : int doorbell_index, int instance)
136 : {
137 0 : u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) :
138 0 : SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
139 :
140 0 : u32 doorbell_range = RREG32(reg);
141 :
142 0 : if (use_doorbell) {
143 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
144 : BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
145 : doorbell_index);
146 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
147 : BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
148 : } else
149 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
150 : BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
151 :
152 0 : WREG32(reg, doorbell_range);
153 0 : }
154 :
155 0 : static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev,
156 : bool enable)
157 : {
158 0 : WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN,
159 : enable ? 1 : 0);
160 0 : }
161 :
162 0 : static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
163 : bool enable)
164 : {
165 0 : u32 tmp = 0;
166 :
167 0 : if (enable) {
168 0 : tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
169 : DOORBELL_SELFRING_GPA_APER_EN, 1) |
170 : REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
171 : DOORBELL_SELFRING_GPA_APER_MODE, 1) |
172 : REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
173 : DOORBELL_SELFRING_GPA_APER_SIZE, 0);
174 :
175 0 : WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
176 : lower_32_bits(adev->doorbell.base));
177 0 : WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
178 : upper_32_bits(adev->doorbell.base));
179 : }
180 :
181 0 : WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
182 : tmp);
183 0 : }
184 :
185 :
186 0 : static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev,
187 : bool use_doorbell, int doorbell_index)
188 : {
189 0 : u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
190 :
191 0 : if (use_doorbell) {
192 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
193 : BIF_IH_DOORBELL_RANGE, OFFSET,
194 : doorbell_index);
195 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
196 : BIF_IH_DOORBELL_RANGE, SIZE,
197 : 2);
198 : } else
199 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
200 : BIF_IH_DOORBELL_RANGE, SIZE,
201 : 0);
202 :
203 0 : WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
204 0 : }
205 :
206 0 : static void nbio_v2_3_ih_control(struct amdgpu_device *adev)
207 : {
208 : u32 interrupt_cntl;
209 :
210 : /* setup interrupt control */
211 0 : WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
212 :
213 0 : interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
214 : /*
215 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
216 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
217 : */
218 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
219 : IH_DUMMY_RD_OVERRIDE, 0);
220 :
221 : /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
222 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
223 : IH_REQ_NONSNOOP_EN, 0);
224 :
225 0 : WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
226 0 : }
227 :
228 0 : static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
229 : bool enable)
230 : {
231 : uint32_t def, data;
232 :
233 0 : if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
234 : return;
235 :
236 0 : def = data = RREG32_PCIE(smnCPM_CONTROL);
237 0 : if (enable) {
238 0 : data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
239 : CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
240 : CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
241 : CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
242 : CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
243 : CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
244 : } else {
245 0 : data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
246 : CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
247 : CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
248 : CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
249 : CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
250 : CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
251 : }
252 :
253 0 : if (def != data)
254 0 : WREG32_PCIE(smnCPM_CONTROL, data);
255 : }
256 :
257 0 : static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
258 : bool enable)
259 : {
260 : uint32_t def, data;
261 :
262 0 : if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
263 : return;
264 :
265 0 : def = data = RREG32_PCIE(smnPCIE_CNTL2);
266 0 : if (enable) {
267 0 : data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
268 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
269 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
270 : } else {
271 0 : data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
272 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
273 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
274 : }
275 :
276 0 : if (def != data)
277 0 : WREG32_PCIE(smnPCIE_CNTL2, data);
278 : }
279 :
280 0 : static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev,
281 : u64 *flags)
282 : {
283 : int data;
284 :
285 : /* AMD_CG_SUPPORT_BIF_MGCG */
286 0 : data = RREG32_PCIE(smnCPM_CONTROL);
287 0 : if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
288 0 : *flags |= AMD_CG_SUPPORT_BIF_MGCG;
289 :
290 : /* AMD_CG_SUPPORT_BIF_LS */
291 0 : data = RREG32_PCIE(smnPCIE_CNTL2);
292 0 : if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
293 0 : *flags |= AMD_CG_SUPPORT_BIF_LS;
294 0 : }
295 :
296 0 : static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
297 : {
298 0 : return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
299 : }
300 :
301 0 : static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
302 : {
303 0 : return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
304 : }
305 :
306 0 : static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)
307 : {
308 0 : return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
309 : }
310 :
311 0 : static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
312 : {
313 0 : return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
314 : }
315 :
316 : const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = {
317 : .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
318 : .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
319 : .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
320 : .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
321 : .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
322 : .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
323 : .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
324 : .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
325 : .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
326 : .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
327 : .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
328 : .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
329 : };
330 :
331 0 : static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
332 : {
333 : uint32_t def, data;
334 :
335 0 : def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
336 0 : data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
337 0 : data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
338 :
339 0 : if (def != data)
340 0 : WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
341 :
342 0 : if (amdgpu_sriov_vf(adev))
343 0 : adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
344 0 : mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
345 0 : }
346 :
347 : #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
348 : #define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x00000009 // 1=1us, 9=1ms
349 : #define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 4ms
350 :
351 0 : static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
352 : bool enable)
353 : {
354 : uint32_t def, data;
355 :
356 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
357 :
358 0 : if (enable) {
359 : /* Disable ASPM L0s/L1 first */
360 0 : data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
361 :
362 0 : data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
363 :
364 0 : if (pci_is_thunderbolt_attached(adev->pdev))
365 0 : data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
366 : else
367 0 : data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
368 :
369 0 : data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
370 : } else {
371 : /* Disbale ASPM L1 */
372 0 : data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
373 : /* Disable ASPM TxL0s */
374 0 : data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
375 : /* Disable ACPI L1 */
376 0 : data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
377 : }
378 :
379 0 : if (def != data)
380 0 : WREG32_PCIE(smnPCIE_LC_CNTL, data);
381 0 : }
382 :
383 : #ifdef CONFIG_PCIEASPM
384 0 : static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
385 : {
386 : uint32_t def, data;
387 :
388 0 : WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
389 :
390 0 : def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);
391 0 : data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
392 0 : if (def != data)
393 0 : WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data);
394 :
395 0 : def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
396 0 : data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
397 0 : if (def != data)
398 0 : WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
399 :
400 0 : def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
401 0 : data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
402 0 : if (def != data)
403 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
404 0 : }
405 : #endif
406 :
407 0 : static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
408 : {
409 : #ifdef CONFIG_PCIEASPM
410 : uint32_t def, data;
411 :
412 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
413 0 : data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
414 0 : data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
415 0 : data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
416 0 : if (def != data)
417 0 : WREG32_PCIE(smnPCIE_LC_CNTL, data);
418 :
419 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
420 0 : data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
421 0 : if (def != data)
422 0 : WREG32_PCIE(smnPCIE_LC_CNTL7, data);
423 :
424 0 : def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
425 0 : data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
426 0 : if (def != data)
427 0 : WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
428 :
429 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
430 0 : data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
431 0 : if (def != data)
432 0 : WREG32_PCIE(smnPCIE_LC_CNTL3, data);
433 :
434 0 : def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
435 0 : data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
436 0 : data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
437 0 : if (def != data)
438 0 : WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
439 :
440 0 : def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
441 0 : data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
442 0 : if (def != data)
443 0 : WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
444 :
445 0 : def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
446 0 : data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
447 0 : if (def != data)
448 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
449 :
450 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
451 :
452 0 : def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
453 0 : data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
454 : PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
455 0 : data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
456 0 : if (def != data)
457 0 : WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
458 :
459 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
460 0 : data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
461 : PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
462 0 : if (def != data)
463 0 : WREG32_PCIE(smnPCIE_LC_CNTL6, data);
464 :
465 : /* Don't bother about LTR if LTR is not enabled
466 : * in the path */
467 0 : if (adev->pdev->ltr_path)
468 0 : nbio_v2_3_program_ltr(adev);
469 :
470 0 : def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
471 0 : data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
472 0 : data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
473 0 : if (def != data)
474 0 : WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);
475 :
476 0 : def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);
477 0 : data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
478 0 : if (def != data)
479 0 : WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
480 :
481 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
482 0 : data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
483 0 : data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
484 0 : data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
485 0 : if (def != data)
486 0 : WREG32_PCIE(smnPCIE_LC_CNTL, data);
487 :
488 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
489 0 : data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
490 0 : if (def != data)
491 0 : WREG32_PCIE(smnPCIE_LC_CNTL3, data);
492 : #endif
493 0 : }
494 :
495 0 : static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
496 : {
497 0 : uint32_t reg_data = 0;
498 0 : uint32_t link_width = 0;
499 :
500 0 : if (!((adev->asic_type >= CHIP_NAVI10) &&
501 : (adev->asic_type <= CHIP_NAVI12)))
502 : return;
503 :
504 0 : reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
505 0 : link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
506 0 : >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
507 :
508 : /*
509 : * Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data)
510 : * if link_width is 0x3 (x4)
511 : */
512 0 : if (0x3 == link_width) {
513 0 : reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6);
514 0 : reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK;
515 0 : reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT);
516 0 : WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data);
517 : }
518 : }
519 :
520 0 : static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev)
521 : {
522 0 : uint32_t reg_data = 0;
523 :
524 0 : if (adev->asic_type != CHIP_NAVI10)
525 : return;
526 :
527 0 : reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
528 0 : reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK;
529 0 : WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data);
530 : }
531 :
532 0 : static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev)
533 : {
534 : uint32_t reg, reg_data;
535 :
536 0 : if (adev->ip_versions[NBIO_HWIP][0] != IP_VERSION(3, 3, 0))
537 : return;
538 :
539 0 : reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);
540 :
541 : /* Clear Interrupt Status
542 : */
543 0 : if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) {
544 0 : reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
545 0 : if (reg & BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) {
546 0 : reg_data = 1 << BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT;
547 0 : WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, reg_data);
548 : }
549 : }
550 : }
551 :
552 : const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
553 : .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
554 : .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
555 : .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
556 : .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset,
557 : .get_rev_id = nbio_v2_3_get_rev_id,
558 : .mc_access_enable = nbio_v2_3_mc_access_enable,
559 : .get_memsize = nbio_v2_3_get_memsize,
560 : .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range,
561 : .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range,
562 : .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture,
563 : .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture,
564 : .ih_doorbell_range = nbio_v2_3_ih_doorbell_range,
565 : .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating,
566 : .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep,
567 : .get_clockgating_state = nbio_v2_3_get_clockgating_state,
568 : .ih_control = nbio_v2_3_ih_control,
569 : .init_registers = nbio_v2_3_init_registers,
570 : .remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
571 : .enable_aspm = nbio_v2_3_enable_aspm,
572 : .program_aspm = nbio_v2_3_program_aspm,
573 : .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
574 : .apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa,
575 : .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt,
576 : };
|
