Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_atombios.h"
25 : #include "nbio_v7_2.h"
26 :
27 : #include "nbio/nbio_7_2_0_offset.h"
28 : #include "nbio/nbio_7_2_0_sh_mask.h"
29 : #include <uapi/linux/kfd_ioctl.h>
30 :
31 : #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015
32 : #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2
33 : #define regBIF_BX0_BIF_FB_EN_YC 0x0100
34 : #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2
35 : #define regBIF1_PCIE_MST_CTRL_3 0x4601c6
36 : #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5
37 : #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
38 : 0x1b
39 : #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
40 : 0x1c
41 : #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
42 : 0x08000000L
43 : #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
44 : 0x30000000L
45 : #define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187
46 : #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
47 : #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
48 : #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
49 :
50 0 : static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
51 : {
52 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
53 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
54 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
55 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
56 0 : }
57 :
58 0 : static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
59 : {
60 : u32 tmp;
61 :
62 0 : switch (adev->ip_versions[NBIO_HWIP][0]) {
63 : case IP_VERSION(7, 2, 1):
64 : case IP_VERSION(7, 3, 0):
65 : case IP_VERSION(7, 5, 0):
66 0 : tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
67 : break;
68 : default:
69 0 : tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
70 : break;
71 : }
72 :
73 0 : tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
74 0 : tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
75 :
76 0 : return tmp;
77 : }
78 :
79 0 : static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
80 : {
81 0 : switch (adev->ip_versions[NBIO_HWIP][0]) {
82 : case IP_VERSION(7, 2, 1):
83 : case IP_VERSION(7, 3, 0):
84 : case IP_VERSION(7, 5, 0):
85 0 : if (enable)
86 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
87 : BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
88 : BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
89 : else
90 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
91 : break;
92 : default:
93 0 : if (enable)
94 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
95 : BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
96 : BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
97 : else
98 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
99 : break;
100 : }
101 0 : }
102 :
103 0 : static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
104 : {
105 0 : return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
106 : }
107 :
108 0 : static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
109 : bool use_doorbell, int doorbell_index,
110 : int doorbell_size)
111 : {
112 0 : u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
113 0 : u32 doorbell_range = RREG32_PCIE_PORT(reg);
114 :
115 0 : if (use_doorbell) {
116 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
117 : GDC0_BIF_SDMA0_DOORBELL_RANGE,
118 : OFFSET, doorbell_index);
119 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
120 : GDC0_BIF_SDMA0_DOORBELL_RANGE,
121 : SIZE, doorbell_size);
122 : } else {
123 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
124 : GDC0_BIF_SDMA0_DOORBELL_RANGE,
125 : SIZE, 0);
126 : }
127 :
128 0 : WREG32_PCIE_PORT(reg, doorbell_range);
129 0 : }
130 :
131 0 : static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
132 : int doorbell_index, int instance)
133 : {
134 0 : u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
135 0 : u32 doorbell_range = RREG32_PCIE_PORT(reg);
136 :
137 0 : if (use_doorbell) {
138 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
139 : GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
140 : doorbell_index);
141 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
142 : GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
143 : } else {
144 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
145 : GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
146 : }
147 :
148 0 : WREG32_PCIE_PORT(reg, doorbell_range);
149 0 : }
150 :
151 0 : static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
152 : bool enable)
153 : {
154 : u32 reg;
155 :
156 0 : reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
157 0 : reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
158 : BIF_DOORBELL_APER_EN, enable ? 1 : 0);
159 :
160 0 : WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
161 0 : }
162 :
163 0 : static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
164 : bool enable)
165 : {
166 0 : u32 tmp = 0;
167 :
168 0 : if (enable) {
169 0 : tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
170 : DOORBELL_SELFRING_GPA_APER_EN, 1) |
171 : REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
172 : DOORBELL_SELFRING_GPA_APER_MODE, 1) |
173 : REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
174 : DOORBELL_SELFRING_GPA_APER_SIZE, 0);
175 :
176 0 : WREG32_SOC15(NBIO, 0,
177 : regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
178 : lower_32_bits(adev->doorbell.base));
179 0 : WREG32_SOC15(NBIO, 0,
180 : regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
181 : upper_32_bits(adev->doorbell.base));
182 : }
183 :
184 0 : WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
185 : tmp);
186 0 : }
187 :
188 :
189 0 : static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
190 : bool use_doorbell, int doorbell_index)
191 : {
192 0 : u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
193 :
194 0 : if (use_doorbell) {
195 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
196 : GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
197 : doorbell_index);
198 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
199 : GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
200 : 2);
201 : } else {
202 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
203 : GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
204 : 0);
205 : }
206 :
207 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
208 : ih_doorbell_range);
209 0 : }
210 :
211 0 : static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
212 : {
213 : u32 interrupt_cntl;
214 :
215 : /* setup interrupt control */
216 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
217 : adev->dummy_page_addr >> 8);
218 :
219 0 : interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
220 : /*
221 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
222 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
223 : */
224 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
225 : IH_DUMMY_RD_OVERRIDE, 0);
226 :
227 : /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
228 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
229 : IH_REQ_NONSNOOP_EN, 0);
230 :
231 0 : WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
232 0 : }
233 :
234 0 : static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
235 : bool enable)
236 : {
237 : uint32_t def, data;
238 :
239 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
240 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
241 0 : data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
242 : CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
243 : CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
244 : CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
245 : CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
246 : CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
247 : } else {
248 0 : data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
249 : CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
250 : CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
251 : CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
252 : CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
253 : CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
254 : }
255 :
256 0 : if (def != data)
257 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
258 0 : }
259 :
260 0 : static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
261 : bool enable)
262 : {
263 : uint32_t def, data;
264 :
265 0 : switch (adev->ip_versions[NBIO_HWIP][0]) {
266 : case IP_VERSION(7, 2, 1):
267 : case IP_VERSION(7, 3, 0):
268 : case IP_VERSION(7, 5, 0):
269 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
270 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
271 0 : data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
272 : else
273 0 : data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
274 :
275 0 : if (def != data)
276 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
277 :
278 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
279 : regBIF1_PCIE_TX_POWER_CTRL_1));
280 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
281 0 : data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
282 : BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
283 : else
284 0 : data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
285 : BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
286 :
287 0 : if (def != data)
288 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
289 : data);
290 : break;
291 : default:
292 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
293 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
294 0 : data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
295 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
296 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
297 : else
298 0 : data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
299 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
300 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
301 :
302 0 : if (def != data)
303 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
304 : break;
305 : }
306 0 : }
307 :
308 0 : static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
309 : u64 *flags)
310 : {
311 : int data;
312 :
313 : /* AMD_CG_SUPPORT_BIF_MGCG */
314 0 : data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
315 0 : if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
316 0 : *flags |= AMD_CG_SUPPORT_BIF_MGCG;
317 :
318 : /* AMD_CG_SUPPORT_BIF_LS */
319 0 : data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
320 0 : if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
321 0 : *flags |= AMD_CG_SUPPORT_BIF_LS;
322 0 : }
323 :
324 0 : static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
325 : {
326 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
327 : }
328 :
329 0 : static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
330 : {
331 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
332 : }
333 :
334 0 : static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
335 : {
336 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
337 : }
338 :
339 0 : static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
340 : {
341 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
342 : }
343 :
344 0 : static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
345 : {
346 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
347 : }
348 :
349 0 : static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
350 : {
351 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
352 : }
353 :
354 : const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
355 : .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
356 : .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
357 : .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
358 : .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
359 : .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
360 : .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
361 : .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
362 : .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
363 : .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
364 : .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
365 : .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
366 : .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
367 : };
368 :
369 0 : static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
370 : {
371 : uint32_t def, data;
372 0 : switch (adev->ip_versions[NBIO_HWIP][0]) {
373 : case IP_VERSION(7, 2, 1):
374 : case IP_VERSION(7, 3, 0):
375 : case IP_VERSION(7, 5, 0):
376 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
377 0 : data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
378 : CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
379 0 : data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
380 : CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
381 :
382 0 : if (def != data)
383 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
384 : break;
385 : default:
386 0 : def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
387 0 : data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
388 : CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
389 0 : data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
390 : CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
391 :
392 0 : if (def != data)
393 0 : WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
394 : break;
395 : }
396 :
397 0 : if (amdgpu_sriov_vf(adev))
398 0 : adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
399 0 : regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
400 0 : }
401 :
402 : const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
403 : .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
404 : .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
405 : .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
406 : .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
407 : .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
408 : .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
409 : .get_rev_id = nbio_v7_2_get_rev_id,
410 : .mc_access_enable = nbio_v7_2_mc_access_enable,
411 : .get_memsize = nbio_v7_2_get_memsize,
412 : .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
413 : .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
414 : .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
415 : .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
416 : .ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
417 : .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
418 : .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
419 : .get_clockgating_state = nbio_v7_2_get_clockgating_state,
420 : .ih_control = nbio_v7_2_ih_control,
421 : .init_registers = nbio_v7_2_init_registers,
422 : .remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
423 : };
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