Line data Source code
1 : /*
2 : * Copyright 2018 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_atombios.h"
25 : #include "nbio_v7_4.h"
26 : #include "amdgpu_ras.h"
27 :
28 : #include "nbio/nbio_7_4_offset.h"
29 : #include "nbio/nbio_7_4_sh_mask.h"
30 : #include "nbio/nbio_7_4_0_smn.h"
31 : #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
32 : #include <uapi/linux/kfd_ioctl.h>
33 :
34 : #define smnPCIE_LC_CNTL 0x11140280
35 : #define smnPCIE_LC_CNTL3 0x111402d4
36 : #define smnPCIE_LC_CNTL6 0x111402ec
37 : #define smnPCIE_LC_CNTL7 0x111402f0
38 : #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
39 : #define smnRCC_BIF_STRAP3 0x1012348c
40 : #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
41 : #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
42 : #define smnRCC_BIF_STRAP5 0x10123494
43 : #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
44 : #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
45 : #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
46 : #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
47 : #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
48 : #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
49 : #define smnRCC_BIF_STRAP2 0x10123488
50 : #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
51 : #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
52 : #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
53 : #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
54 :
55 : /*
56 : * These are nbio v7_4_1 registers mask. Temporarily define these here since
57 : * nbio v7_4_1 header is incomplete.
58 : */
59 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */
60 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
61 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
62 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
63 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
64 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
65 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
66 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
67 : #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
68 :
69 : #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
70 : #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
71 : //BIF_MMSCH1_DOORBELL_RANGE
72 : #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
73 : #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
74 : #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
75 : #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
76 :
77 : #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
78 : #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
79 :
80 : #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8
81 : #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2
82 : //BIF_MMSCH1_DOORBELL_ALDE_RANGE
83 : #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2
84 : #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10
85 : #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL
86 : #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L
87 :
88 : #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015
89 : #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2
90 :
91 : #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe
92 : #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2
93 : #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
94 : #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
95 :
96 : #define mmBIF_INTR_CNTL_ALDE 0x0101
97 : #define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2
98 :
99 : static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
100 : void *ras_error_status);
101 :
102 0 : static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
103 : {
104 0 : WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
105 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
106 0 : WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
107 : adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
108 0 : }
109 :
110 0 : static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
111 : {
112 : u32 tmp;
113 :
114 0 : if (adev->asic_type == CHIP_ALDEBARAN)
115 0 : tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
116 : else
117 0 : tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
118 :
119 0 : tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
120 0 : tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
121 :
122 0 : return tmp;
123 : }
124 :
125 0 : static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
126 : {
127 0 : if (enable)
128 0 : WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
129 : BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
130 : else
131 0 : WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
132 0 : }
133 :
134 0 : static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
135 : {
136 0 : return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
137 : }
138 :
139 0 : static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
140 : bool use_doorbell, int doorbell_index, int doorbell_size)
141 : {
142 : u32 reg, doorbell_range;
143 :
144 0 : if (instance < 2) {
145 0 : reg = instance +
146 0 : SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
147 : } else {
148 : /*
149 : * These registers address of SDMA2~7 is not consecutive
150 : * from SDMA0~1. Need plus 4 dwords offset.
151 : *
152 : * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0
153 : * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4
154 : * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8
155 : + * BIF_SDMA4_DOORBELL_RANGE:
156 : + * ARCTURUS: 0x3be0
157 : + * ALDEBARAN: 0x3be4
158 : */
159 0 : if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
160 0 : reg = instance + 0x4 + 0x1 +
161 0 : SOC15_REG_OFFSET(NBIO, 0,
162 : mmBIF_SDMA0_DOORBELL_RANGE);
163 : else
164 0 : reg = instance + 0x4 +
165 0 : SOC15_REG_OFFSET(NBIO, 0,
166 : mmBIF_SDMA0_DOORBELL_RANGE);
167 : }
168 :
169 0 : doorbell_range = RREG32(reg);
170 :
171 0 : if (use_doorbell) {
172 0 : doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
173 0 : doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
174 : } else
175 0 : doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
176 :
177 0 : WREG32(reg, doorbell_range);
178 0 : }
179 :
180 0 : static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
181 : int doorbell_index, int instance)
182 : {
183 : u32 reg;
184 : u32 doorbell_range;
185 :
186 0 : if (instance) {
187 0 : if (adev->asic_type == CHIP_ALDEBARAN)
188 0 : reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
189 : else
190 0 : reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
191 : } else
192 0 : reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
193 :
194 0 : doorbell_range = RREG32(reg);
195 :
196 0 : if (use_doorbell) {
197 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
198 : BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
199 : doorbell_index);
200 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
201 : BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
202 : } else
203 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
204 : BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
205 :
206 0 : WREG32(reg, doorbell_range);
207 0 : }
208 :
209 0 : static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
210 : bool enable)
211 : {
212 0 : WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
213 0 : }
214 :
215 0 : static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
216 : bool enable)
217 : {
218 0 : u32 tmp = 0;
219 :
220 0 : if (enable) {
221 0 : tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
222 : REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
223 : REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
224 :
225 0 : WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
226 : lower_32_bits(adev->doorbell.base));
227 0 : WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
228 : upper_32_bits(adev->doorbell.base));
229 : }
230 :
231 0 : WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
232 0 : }
233 :
234 0 : static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
235 : bool use_doorbell, int doorbell_index)
236 : {
237 0 : u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
238 :
239 0 : if (use_doorbell) {
240 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
241 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
242 : } else
243 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
244 :
245 0 : WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
246 0 : }
247 :
248 :
249 0 : static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
250 : bool enable)
251 : {
252 : //TODO: Add support for v7.4
253 0 : }
254 :
255 0 : static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
256 : bool enable)
257 : {
258 : uint32_t def, data;
259 :
260 0 : def = data = RREG32_PCIE(smnPCIE_CNTL2);
261 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
262 0 : data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
263 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
264 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
265 : } else {
266 0 : data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
267 : PCIE_CNTL2__MST_MEM_LS_EN_MASK |
268 : PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
269 : }
270 :
271 0 : if (def != data)
272 0 : WREG32_PCIE(smnPCIE_CNTL2, data);
273 0 : }
274 :
275 0 : static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
276 : u64 *flags)
277 : {
278 : int data;
279 :
280 : /* AMD_CG_SUPPORT_BIF_MGCG */
281 0 : data = RREG32_PCIE(smnCPM_CONTROL);
282 0 : if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
283 0 : *flags |= AMD_CG_SUPPORT_BIF_MGCG;
284 :
285 : /* AMD_CG_SUPPORT_BIF_LS */
286 0 : data = RREG32_PCIE(smnPCIE_CNTL2);
287 0 : if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
288 0 : *flags |= AMD_CG_SUPPORT_BIF_LS;
289 0 : }
290 :
291 0 : static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
292 : {
293 : u32 interrupt_cntl;
294 :
295 : /* setup interrupt control */
296 0 : WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
297 0 : interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
298 : /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
299 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
300 : */
301 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
302 : /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
303 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
304 0 : WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
305 0 : }
306 :
307 0 : static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
308 : {
309 0 : return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
310 : }
311 :
312 0 : static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
313 : {
314 0 : return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
315 : }
316 :
317 0 : static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
318 : {
319 0 : return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
320 : }
321 :
322 0 : static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
323 : {
324 0 : return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
325 : }
326 :
327 : const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
328 : .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
329 : .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
330 : .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
331 : .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
332 : .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
333 : .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
334 : .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
335 : .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
336 : .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
337 : .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
338 : .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
339 : .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
340 : };
341 :
342 0 : static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
343 : {
344 : uint32_t baco_cntl;
345 :
346 0 : if (amdgpu_sriov_vf(adev))
347 0 : adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
348 0 : mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
349 :
350 0 : if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4) &&
351 : !amdgpu_sriov_vf(adev)) {
352 0 : baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);
353 0 : if (baco_cntl &
354 : (BACO_CNTL__BACO_DUMMY_EN_MASK | BACO_CNTL__BACO_EN_MASK)) {
355 0 : baco_cntl &= ~(BACO_CNTL__BACO_DUMMY_EN_MASK |
356 : BACO_CNTL__BACO_EN_MASK);
357 : dev_dbg(adev->dev, "Unsetting baco dummy mode %x",
358 : baco_cntl);
359 0 : WREG32_SOC15(NBIO, 0, mmBACO_CNTL, baco_cntl);
360 : }
361 : }
362 0 : }
363 :
364 0 : static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
365 : {
366 : uint32_t bif_doorbell_intr_cntl;
367 0 : struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
368 0 : struct ras_err_data err_data = {0, 0, 0, NULL};
369 0 : struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
370 :
371 0 : if (adev->asic_type == CHIP_ALDEBARAN)
372 0 : bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
373 : else
374 0 : bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
375 :
376 0 : if (REG_GET_FIELD(bif_doorbell_intr_cntl,
377 : BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
378 : /* driver has to clear the interrupt status when bif ring is disabled */
379 0 : bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
380 : BIF_DOORBELL_INT_CNTL,
381 : RAS_CNTLR_INTERRUPT_CLEAR, 1);
382 0 : if (adev->asic_type == CHIP_ALDEBARAN)
383 0 : WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
384 : else
385 0 : WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
386 :
387 0 : if (!ras->disable_ras_err_cnt_harvest) {
388 : /*
389 : * clear error status after ras_controller_intr
390 : * according to hw team and count ue number
391 : * for query
392 : */
393 0 : nbio_v7_4_query_ras_error_count(adev, &err_data);
394 :
395 : /* logging on error cnt and printing for awareness */
396 0 : obj->err_data.ue_count += err_data.ue_count;
397 0 : obj->err_data.ce_count += err_data.ce_count;
398 :
399 0 : if (err_data.ce_count)
400 0 : dev_info(adev->dev, "%ld correctable hardware "
401 : "errors detected in %s block, "
402 : "no user action is needed.\n",
403 : obj->err_data.ce_count,
404 : get_ras_block_str(adev->nbio.ras_if));
405 :
406 0 : if (err_data.ue_count)
407 0 : dev_info(adev->dev, "%ld uncorrectable hardware "
408 : "errors detected in %s block\n",
409 : obj->err_data.ue_count,
410 : get_ras_block_str(adev->nbio.ras_if));
411 : }
412 :
413 0 : dev_info(adev->dev, "RAS controller interrupt triggered "
414 : "by NBIF error\n");
415 :
416 : /* ras_controller_int is dedicated for nbif ras error,
417 : * not the global interrupt for sync flood
418 : */
419 0 : amdgpu_ras_reset_gpu(adev);
420 : }
421 0 : }
422 :
423 0 : static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
424 : {
425 : uint32_t bif_doorbell_intr_cntl;
426 :
427 0 : if (adev->asic_type == CHIP_ALDEBARAN)
428 0 : bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
429 : else
430 0 : bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
431 :
432 0 : if (REG_GET_FIELD(bif_doorbell_intr_cntl,
433 : BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
434 : /* driver has to clear the interrupt status when bif ring is disabled */
435 0 : bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
436 : BIF_DOORBELL_INT_CNTL,
437 : RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
438 :
439 0 : if (adev->asic_type == CHIP_ALDEBARAN)
440 0 : WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
441 : else
442 0 : WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
443 :
444 0 : amdgpu_ras_global_ras_isr(adev);
445 : }
446 0 : }
447 :
448 :
449 0 : static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
450 : struct amdgpu_irq_src *src,
451 : unsigned type,
452 : enum amdgpu_interrupt_state state)
453 : {
454 : /* The ras_controller_irq enablement should be done in psp bl when it
455 : * tries to enable ras feature. Driver only need to set the correct interrupt
456 : * vector for bare-metal and sriov use case respectively
457 : */
458 : uint32_t bif_intr_cntl;
459 :
460 0 : if (adev->asic_type == CHIP_ALDEBARAN)
461 0 : bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
462 : else
463 0 : bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
464 :
465 0 : if (state == AMDGPU_IRQ_STATE_ENABLE) {
466 : /* set interrupt vector select bit to 0 to select
467 : * vetcor 1 for bare metal case */
468 0 : bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
469 : BIF_INTR_CNTL,
470 : RAS_INTR_VEC_SEL, 0);
471 :
472 0 : if (adev->asic_type == CHIP_ALDEBARAN)
473 0 : WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
474 : else
475 0 : WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
476 :
477 : }
478 :
479 0 : return 0;
480 : }
481 :
482 0 : static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
483 : struct amdgpu_irq_src *source,
484 : struct amdgpu_iv_entry *entry)
485 : {
486 : /* By design, the ih cookie for ras_controller_irq should be written
487 : * to BIFring instead of general iv ring. However, due to known bif ring
488 : * hw bug, it has to be disabled. There is no chance the process function
489 : * will be involked. Just left it as a dummy one.
490 : */
491 0 : return 0;
492 : }
493 :
494 0 : static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
495 : struct amdgpu_irq_src *src,
496 : unsigned type,
497 : enum amdgpu_interrupt_state state)
498 : {
499 : /* The ras_controller_irq enablement should be done in psp bl when it
500 : * tries to enable ras feature. Driver only need to set the correct interrupt
501 : * vector for bare-metal and sriov use case respectively
502 : */
503 : uint32_t bif_intr_cntl;
504 :
505 0 : if (adev->asic_type == CHIP_ALDEBARAN)
506 0 : bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
507 : else
508 0 : bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
509 :
510 0 : if (state == AMDGPU_IRQ_STATE_ENABLE) {
511 : /* set interrupt vector select bit to 0 to select
512 : * vetcor 1 for bare metal case */
513 0 : bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
514 : BIF_INTR_CNTL,
515 : RAS_INTR_VEC_SEL, 0);
516 :
517 0 : if (adev->asic_type == CHIP_ALDEBARAN)
518 0 : WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
519 : else
520 0 : WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
521 : }
522 :
523 0 : return 0;
524 : }
525 :
526 0 : static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
527 : struct amdgpu_irq_src *source,
528 : struct amdgpu_iv_entry *entry)
529 : {
530 : /* By design, the ih cookie for err_event_athub_irq should be written
531 : * to BIFring instead of general iv ring. However, due to known bif ring
532 : * hw bug, it has to be disabled. There is no chance the process function
533 : * will be involked. Just left it as a dummy one.
534 : */
535 0 : return 0;
536 : }
537 :
538 : static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
539 : .set = nbio_v7_4_set_ras_controller_irq_state,
540 : .process = nbio_v7_4_process_ras_controller_irq,
541 : };
542 :
543 : static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
544 : .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
545 : .process = nbio_v7_4_process_err_event_athub_irq,
546 : };
547 :
548 0 : static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
549 : {
550 : int r;
551 :
552 : /* init the irq funcs */
553 0 : adev->nbio.ras_controller_irq.funcs =
554 : &nbio_v7_4_ras_controller_irq_funcs;
555 0 : adev->nbio.ras_controller_irq.num_types = 1;
556 :
557 : /* register ras controller interrupt */
558 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
559 : NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
560 : &adev->nbio.ras_controller_irq);
561 :
562 0 : return r;
563 : }
564 :
565 0 : static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
566 : {
567 :
568 : int r;
569 :
570 : /* init the irq funcs */
571 0 : adev->nbio.ras_err_event_athub_irq.funcs =
572 : &nbio_v7_4_ras_err_event_athub_irq_funcs;
573 0 : adev->nbio.ras_err_event_athub_irq.num_types = 1;
574 :
575 : /* register ras err event athub interrupt */
576 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
577 : NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
578 : &adev->nbio.ras_err_event_athub_irq);
579 :
580 0 : return r;
581 : }
582 :
583 : #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030
584 : #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE 0x13b20030
585 : #define smnRAS_GLOBAL_STATUS_LO_ALDE 0x13b20020
586 :
587 0 : static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
588 : void *ras_error_status)
589 : {
590 : uint32_t global_sts, central_sts, int_eoi, parity_sts;
591 : uint32_t corr, fatal, non_fatal;
592 0 : struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
593 :
594 0 : if (adev->asic_type == CHIP_ALDEBARAN)
595 0 : global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE);
596 : else
597 0 : global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
598 :
599 0 : corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
600 0 : fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
601 0 : non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
602 : ParityErrNonFatal);
603 :
604 0 : if (adev->asic_type == CHIP_ALDEBARAN)
605 0 : parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE);
606 : else
607 0 : parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
608 :
609 0 : if (corr)
610 0 : err_data->ce_count++;
611 0 : if (fatal)
612 0 : err_data->ue_count++;
613 :
614 0 : if (corr || fatal || non_fatal) {
615 0 : central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
616 :
617 : /* clear error status register */
618 0 : if (adev->asic_type == CHIP_ALDEBARAN)
619 0 : WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts);
620 : else
621 0 : WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
622 :
623 0 : if (fatal)
624 : {
625 : /* clear parity fatal error indication field */
626 0 : if (adev->asic_type == CHIP_ALDEBARAN)
627 0 : WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts);
628 : else
629 0 : WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts);
630 : }
631 :
632 0 : if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
633 : BIFL_RasContller_Intr_Recv)) {
634 : /* clear interrupt status register */
635 0 : WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
636 0 : int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
637 0 : int_eoi = REG_SET_FIELD(int_eoi,
638 : IOHC_INTERRUPT_EOI, SMI_EOI, 1);
639 0 : WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
640 : }
641 : }
642 0 : }
643 :
644 0 : static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
645 : bool enable)
646 : {
647 0 : if (adev->asic_type == CHIP_ALDEBARAN)
648 0 : WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE,
649 : DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
650 : else
651 0 : WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
652 : DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
653 0 : }
654 :
655 : const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = {
656 : .query_ras_error_count = nbio_v7_4_query_ras_error_count,
657 : };
658 :
659 : struct amdgpu_nbio_ras nbio_v7_4_ras = {
660 : .ras_block = {
661 : .ras_comm = {
662 : .name = "pcie_bif",
663 : .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
664 : .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
665 : },
666 : .hw_ops = &nbio_v7_4_ras_hw_ops,
667 : .ras_late_init = amdgpu_nbio_ras_late_init,
668 : },
669 : .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
670 : .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
671 : .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
672 : .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
673 : };
674 :
675 :
676 : #ifdef CONFIG_PCIEASPM
677 0 : static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
678 : {
679 : uint32_t def, data;
680 :
681 0 : WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
682 :
683 0 : def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
684 0 : data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
685 0 : if (def != data)
686 0 : WREG32_PCIE(smnRCC_BIF_STRAP2, data);
687 :
688 0 : def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
689 0 : data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
690 0 : if (def != data)
691 0 : WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
692 :
693 0 : def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
694 0 : data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
695 0 : if (def != data)
696 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
697 0 : }
698 : #endif
699 :
700 0 : static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
701 : {
702 : #ifdef CONFIG_PCIEASPM
703 : uint32_t def, data;
704 :
705 0 : if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4))
706 : return;
707 :
708 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
709 0 : data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
710 0 : data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
711 0 : data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
712 0 : if (def != data)
713 0 : WREG32_PCIE(smnPCIE_LC_CNTL, data);
714 :
715 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
716 0 : data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
717 0 : if (def != data)
718 0 : WREG32_PCIE(smnPCIE_LC_CNTL7, data);
719 :
720 0 : def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
721 0 : data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
722 0 : if (def != data)
723 0 : WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
724 :
725 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
726 0 : data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
727 0 : if (def != data)
728 0 : WREG32_PCIE(smnPCIE_LC_CNTL3, data);
729 :
730 0 : def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
731 0 : data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
732 0 : data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
733 0 : if (def != data)
734 0 : WREG32_PCIE(smnRCC_BIF_STRAP3, data);
735 :
736 0 : def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
737 0 : data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
738 0 : if (def != data)
739 0 : WREG32_PCIE(smnRCC_BIF_STRAP5, data);
740 :
741 0 : def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
742 0 : data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
743 0 : if (def != data)
744 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
745 :
746 0 : WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
747 :
748 0 : def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
749 0 : data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
750 : PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
751 0 : data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
752 0 : if (def != data)
753 0 : WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
754 :
755 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
756 0 : data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
757 : PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
758 0 : if (def != data)
759 0 : WREG32_PCIE(smnPCIE_LC_CNTL6, data);
760 :
761 : /* Don't bother about LTR if LTR is not enabled
762 : * in the path */
763 0 : if (adev->pdev->ltr_path)
764 0 : nbio_v7_4_program_ltr(adev);
765 :
766 0 : def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
767 0 : data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
768 0 : data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
769 0 : if (def != data)
770 0 : WREG32_PCIE(smnRCC_BIF_STRAP3, data);
771 :
772 0 : def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
773 0 : data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
774 0 : if (def != data)
775 0 : WREG32_PCIE(smnRCC_BIF_STRAP5, data);
776 :
777 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
778 0 : data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
779 0 : data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
780 0 : data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
781 0 : if (def != data)
782 0 : WREG32_PCIE(smnPCIE_LC_CNTL, data);
783 :
784 0 : def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
785 0 : data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
786 0 : if (def != data)
787 0 : WREG32_PCIE(smnPCIE_LC_CNTL3, data);
788 : #endif
789 : }
790 :
791 : const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
792 : .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
793 : .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
794 : .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
795 : .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
796 : .get_rev_id = nbio_v7_4_get_rev_id,
797 : .mc_access_enable = nbio_v7_4_mc_access_enable,
798 : .get_memsize = nbio_v7_4_get_memsize,
799 : .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
800 : .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
801 : .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
802 : .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
803 : .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
804 : .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
805 : .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
806 : .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
807 : .get_clockgating_state = nbio_v7_4_get_clockgating_state,
808 : .ih_control = nbio_v7_4_ih_control,
809 : .init_registers = nbio_v7_4_init_registers,
810 : .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
811 : .program_aspm = nbio_v7_4_program_aspm,
812 : };
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