Line data Source code
1 : /*
2 : * Copyright 2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_atombios.h"
25 : #include "nbio_v7_7.h"
26 :
27 : #include "nbio/nbio_7_7_0_offset.h"
28 : #include "nbio/nbio_7_7_0_sh_mask.h"
29 : #include <uapi/linux/kfd_ioctl.h>
30 :
31 0 : static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
32 : {
33 : u32 tmp;
34 :
35 0 : tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
36 0 : tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
37 0 : tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
38 :
39 0 : return tmp;
40 : }
41 :
42 0 : static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
43 : {
44 0 : if (enable)
45 0 : WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
46 : BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
47 : BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
48 : else
49 0 : WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
50 0 : }
51 :
52 0 : static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)
53 : {
54 0 : return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
55 : }
56 :
57 0 : static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
58 : bool use_doorbell, int doorbell_index,
59 : int doorbell_size)
60 : {
61 0 : u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
62 0 : u32 doorbell_range = RREG32_PCIE_PORT(reg);
63 :
64 0 : if (use_doorbell) {
65 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
66 : GDC0_BIF_CSDMA_DOORBELL_RANGE,
67 : OFFSET, doorbell_index);
68 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
69 : GDC0_BIF_CSDMA_DOORBELL_RANGE,
70 : SIZE, doorbell_size);
71 : } else {
72 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
73 : GDC0_BIF_SDMA0_DOORBELL_RANGE,
74 : SIZE, 0);
75 : }
76 :
77 0 : WREG32_PCIE_PORT(reg, doorbell_range);
78 0 : }
79 :
80 0 : static void nbio_v7_7_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
81 : int doorbell_index, int instance)
82 : {
83 0 : u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
84 0 : u32 doorbell_range = RREG32_PCIE_PORT(reg);
85 :
86 0 : if (use_doorbell) {
87 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
88 : GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
89 : doorbell_index);
90 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
91 : GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
92 : } else {
93 0 : doorbell_range = REG_SET_FIELD(doorbell_range,
94 : GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
95 : }
96 :
97 0 : WREG32_PCIE_PORT(reg, doorbell_range);
98 0 : }
99 :
100 0 : static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
101 : bool enable)
102 : {
103 : u32 reg;
104 :
105 0 : reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
106 0 : reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
107 : BIF_DOORBELL_APER_EN, enable ? 1 : 0);
108 :
109 0 : WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
110 0 : }
111 :
112 0 : static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
113 : bool enable)
114 : {
115 0 : u32 tmp = 0;
116 :
117 0 : if (enable) {
118 0 : tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
119 : DOORBELL_SELFRING_GPA_APER_EN, 1) |
120 : REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
121 : DOORBELL_SELFRING_GPA_APER_MODE, 1) |
122 : REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
123 : DOORBELL_SELFRING_GPA_APER_SIZE, 0);
124 :
125 0 : WREG32_SOC15(NBIO, 0,
126 : regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
127 : lower_32_bits(adev->doorbell.base));
128 0 : WREG32_SOC15(NBIO, 0,
129 : regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
130 : upper_32_bits(adev->doorbell.base));
131 : }
132 :
133 0 : WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
134 : tmp);
135 0 : }
136 :
137 :
138 0 : static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev,
139 : bool use_doorbell, int doorbell_index)
140 : {
141 0 : u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,
142 : regGDC0_BIF_IH_DOORBELL_RANGE);
143 :
144 0 : if (use_doorbell) {
145 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
146 : GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
147 : doorbell_index);
148 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
149 : GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
150 : 2);
151 : } else {
152 0 : ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
153 : GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
154 : 0);
155 : }
156 :
157 0 : WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
158 : ih_doorbell_range);
159 0 : }
160 :
161 0 : static void nbio_v7_7_ih_control(struct amdgpu_device *adev)
162 : {
163 : u32 interrupt_cntl;
164 :
165 : /* setup interrupt control */
166 0 : WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
167 : adev->dummy_page_addr >> 8);
168 :
169 0 : interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
170 : /*
171 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
172 : * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
173 : */
174 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
175 : IH_DUMMY_RD_OVERRIDE, 0);
176 :
177 : /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
178 0 : interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
179 : IH_REQ_NONSNOOP_EN, 0);
180 :
181 0 : WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
182 0 : }
183 :
184 0 : static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)
185 : {
186 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
187 : }
188 :
189 0 : static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)
190 : {
191 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
192 : }
193 :
194 0 : static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)
195 : {
196 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
197 : }
198 :
199 0 : static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)
200 : {
201 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
202 : }
203 :
204 0 : static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)
205 : {
206 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
207 : }
208 :
209 0 : static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)
210 : {
211 0 : return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
212 : }
213 :
214 : const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = {
215 : .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
216 : .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
217 : .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
218 : .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
219 : .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
220 : .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
221 : .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
222 : .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
223 : .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
224 : .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
225 : .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
226 : .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
227 : };
228 :
229 0 : static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
230 : {
231 : uint32_t def, data;
232 :
233 0 : def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
234 0 : data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
235 : CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
236 0 : data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
237 : CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
238 :
239 0 : if (def != data)
240 0 : WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
241 :
242 0 : }
243 :
244 0 : static void nbio_v7_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
245 : bool enable)
246 : {
247 : uint32_t def, data;
248 :
249 0 : if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
250 : return;
251 :
252 0 : def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
253 0 : if (enable) {
254 0 : data |= (BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
255 : BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
256 : BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
257 : BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
258 : BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
259 : BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
260 : } else {
261 0 : data &= ~(BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
262 : BIF0_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
263 : BIF0_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
264 : BIF0_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
265 : BIF0_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
266 : BIF0_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
267 : }
268 :
269 0 : if (def != data)
270 0 : WREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL, data);
271 : }
272 :
273 0 : static void nbio_v7_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
274 : bool enable)
275 : {
276 : uint32_t def, data;
277 :
278 0 : if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
279 : return;
280 :
281 0 : def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
282 0 : if (enable)
283 0 : data |= BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
284 : else
285 0 : data &= ~BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
286 :
287 0 : if (def != data)
288 0 : WREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2, data);
289 :
290 0 : def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);
291 0 : if (enable) {
292 0 : data |= (BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
293 : BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
294 : } else {
295 0 : data &= ~(BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
296 : BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
297 : }
298 :
299 0 : if (def != data)
300 0 : WREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1, data);
301 : }
302 :
303 0 : static void nbio_v7_7_get_clockgating_state(struct amdgpu_device *adev,
304 : u64 *flags)
305 : {
306 : uint32_t data;
307 :
308 : /* AMD_CG_SUPPORT_BIF_MGCG */
309 0 : data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);
310 0 : if (data & BIF0_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
311 0 : *flags |= AMD_CG_SUPPORT_BIF_MGCG;
312 :
313 : /* AMD_CG_SUPPORT_BIF_LS */
314 0 : data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);
315 0 : if (data & BIF0_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
316 0 : *flags |= AMD_CG_SUPPORT_BIF_LS;
317 0 : }
318 :
319 : const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
320 : .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
321 : .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
322 : .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset,
323 : .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset,
324 : .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset,
325 : .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset,
326 : .get_rev_id = nbio_v7_7_get_rev_id,
327 : .mc_access_enable = nbio_v7_7_mc_access_enable,
328 : .get_memsize = nbio_v7_7_get_memsize,
329 : .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
330 : .vcn_doorbell_range = nbio_v7_7_vcn_doorbell_range,
331 : .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
332 : .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
333 : .ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
334 : .update_medium_grain_clock_gating = nbio_v7_7_update_medium_grain_clock_gating,
335 : .update_medium_grain_light_sleep = nbio_v7_7_update_medium_grain_light_sleep,
336 : .get_clockgating_state = nbio_v7_7_get_clockgating_state,
337 : .ih_control = nbio_v7_7_ih_control,
338 : .init_registers = nbio_v7_7_init_registers,
339 : };
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