Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include "amdgpu.h"
24 : #include "amdgpu_psp.h"
25 : #include "amdgpu_ucode.h"
26 : #include "soc15_common.h"
27 : #include "psp_v13_0_4.h"
28 :
29 : #include "mp/mp_13_0_4_offset.h"
30 : #include "mp/mp_13_0_4_sh_mask.h"
31 :
32 : MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
33 : MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
34 :
35 0 : static int psp_v13_0_4_init_microcode(struct psp_context *psp)
36 : {
37 0 : struct amdgpu_device *adev = psp->adev;
38 : const char *chip_name;
39 : char ucode_prefix[30];
40 0 : int err = 0;
41 :
42 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
43 : case IP_VERSION(13, 0, 4):
44 0 : amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
45 0 : chip_name = ucode_prefix;
46 : break;
47 : default:
48 0 : BUG();
49 : }
50 :
51 0 : switch (adev->ip_versions[MP0_HWIP][0]) {
52 : case IP_VERSION(13, 0, 4):
53 0 : err = psp_init_toc_microcode(psp, chip_name);
54 0 : if (err)
55 : return err;
56 0 : err = psp_init_ta_microcode(psp, chip_name);
57 0 : if (err)
58 : return err;
59 : break;
60 : default:
61 0 : BUG();
62 : }
63 :
64 0 : return 0;
65 : }
66 :
67 0 : static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
68 : {
69 0 : struct amdgpu_device *adev = psp->adev;
70 : uint32_t sol_reg;
71 :
72 0 : sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
73 :
74 0 : return sol_reg != 0x0;
75 : }
76 :
77 0 : static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
78 : {
79 0 : struct amdgpu_device *adev = psp->adev;
80 :
81 : int ret;
82 : int retry_loop;
83 :
84 0 : for (retry_loop = 0; retry_loop < 10; retry_loop++) {
85 : /* Wait for bootloader to signify that is
86 : ready having bit 31 of C2PMSG_35 set to 1 */
87 0 : ret = psp_wait_for(psp,
88 0 : SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
89 : 0x80000000,
90 : 0x80000000,
91 : false);
92 :
93 0 : if (ret == 0)
94 : return 0;
95 : }
96 :
97 : return ret;
98 : }
99 :
100 0 : static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
101 : struct psp_bin_desc *bin_desc,
102 : enum psp_bootloader_cmd bl_cmd)
103 : {
104 : int ret;
105 0 : uint32_t psp_gfxdrv_command_reg = 0;
106 0 : struct amdgpu_device *adev = psp->adev;
107 :
108 : /* Check tOS sign of life register to confirm sys driver and sOS
109 : * are already been loaded.
110 : */
111 0 : if (psp_v13_0_4_is_sos_alive(psp))
112 : return 0;
113 :
114 0 : ret = psp_v13_0_4_wait_for_bootloader(psp);
115 0 : if (ret)
116 : return ret;
117 :
118 0 : memset(psp->fw_pri_buf, 0, PSP_1_MEG);
119 :
120 : /* Copy PSP KDB binary to memory */
121 0 : memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
122 :
123 : /* Provide the PSP KDB to bootloader */
124 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
125 : (uint32_t)(psp->fw_pri_mc_addr >> 20));
126 0 : psp_gfxdrv_command_reg = bl_cmd;
127 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
128 : psp_gfxdrv_command_reg);
129 :
130 0 : ret = psp_v13_0_4_wait_for_bootloader(psp);
131 :
132 : return ret;
133 : }
134 :
135 0 : static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
136 : {
137 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
138 : }
139 :
140 0 : static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
141 : {
142 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
143 : }
144 :
145 0 : static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
146 : {
147 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
148 : }
149 :
150 0 : static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
151 : {
152 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
153 : }
154 :
155 0 : static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
156 : {
157 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
158 : }
159 :
160 0 : static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
161 : {
162 0 : return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
163 : }
164 :
165 0 : static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
166 : {
167 : int ret;
168 0 : unsigned int psp_gfxdrv_command_reg = 0;
169 0 : struct amdgpu_device *adev = psp->adev;
170 :
171 : /* Check sOS sign of life register to confirm sys driver and sOS
172 : * are already been loaded.
173 : */
174 0 : if (psp_v13_0_4_is_sos_alive(psp))
175 : return 0;
176 :
177 0 : ret = psp_v13_0_4_wait_for_bootloader(psp);
178 0 : if (ret)
179 : return ret;
180 :
181 0 : memset(psp->fw_pri_buf, 0, PSP_1_MEG);
182 :
183 : /* Copy Secure OS binary to PSP memory */
184 0 : memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
185 :
186 : /* Provide the PSP secure OS to bootloader */
187 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
188 : (uint32_t)(psp->fw_pri_mc_addr >> 20));
189 0 : psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
190 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
191 : psp_gfxdrv_command_reg);
192 :
193 : /* there might be handshake issue with hardware which needs delay */
194 0 : mdelay(20);
195 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
196 0 : RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
197 : 0, true);
198 :
199 0 : return ret;
200 : }
201 :
202 0 : static int psp_v13_0_4_ring_init(struct psp_context *psp,
203 : enum psp_ring_type ring_type)
204 : {
205 0 : int ret = 0;
206 : struct psp_ring *ring;
207 0 : struct amdgpu_device *adev = psp->adev;
208 :
209 0 : ring = &psp->km_ring;
210 :
211 0 : ring->ring_type = ring_type;
212 :
213 : /* allocate 4k Page of Local Frame Buffer memory for ring */
214 0 : ring->ring_size = 0x1000;
215 0 : ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
216 : AMDGPU_GEM_DOMAIN_VRAM,
217 : &adev->firmware.rbuf,
218 0 : &ring->ring_mem_mc_addr,
219 0 : (void **)&ring->ring_mem);
220 0 : if (ret) {
221 0 : ring->ring_size = 0;
222 0 : return ret;
223 : }
224 :
225 : return 0;
226 : }
227 :
228 0 : static int psp_v13_0_4_ring_stop(struct psp_context *psp,
229 : enum psp_ring_type ring_type)
230 : {
231 0 : int ret = 0;
232 0 : struct amdgpu_device *adev = psp->adev;
233 :
234 0 : if (amdgpu_sriov_vf(adev)) {
235 : /* Write the ring destroy command*/
236 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
237 : GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
238 : /* there might be handshake issue with hardware which needs delay */
239 0 : mdelay(20);
240 : /* Wait for response flag (bit 31) */
241 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
242 : 0x80000000, 0x80000000, false);
243 : } else {
244 : /* Write the ring destroy command*/
245 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
246 : GFX_CTRL_CMD_ID_DESTROY_RINGS);
247 : /* there might be handshake issue with hardware which needs delay */
248 0 : mdelay(20);
249 : /* Wait for response flag (bit 31) */
250 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
251 : 0x80000000, 0x80000000, false);
252 : }
253 :
254 0 : return ret;
255 : }
256 :
257 0 : static int psp_v13_0_4_ring_create(struct psp_context *psp,
258 : enum psp_ring_type ring_type)
259 : {
260 0 : int ret = 0;
261 0 : unsigned int psp_ring_reg = 0;
262 0 : struct psp_ring *ring = &psp->km_ring;
263 0 : struct amdgpu_device *adev = psp->adev;
264 :
265 0 : if (amdgpu_sriov_vf(adev)) {
266 0 : ret = psp_v13_0_4_ring_stop(psp, ring_type);
267 0 : if (ret) {
268 0 : DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
269 0 : return ret;
270 : }
271 :
272 : /* Write low address of the ring to C2PMSG_102 */
273 0 : psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
274 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
275 : /* Write high address of the ring to C2PMSG_103 */
276 0 : psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
277 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
278 :
279 : /* Write the ring initialization command to C2PMSG_101 */
280 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
281 : GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
282 :
283 : /* there might be handshake issue with hardware which needs delay */
284 0 : mdelay(20);
285 :
286 : /* Wait for response flag (bit 31) in C2PMSG_101 */
287 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
288 : 0x80000000, 0x8000FFFF, false);
289 :
290 : } else {
291 : /* Wait for sOS ready for ring creation */
292 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
293 : 0x80000000, 0x80000000, false);
294 0 : if (ret) {
295 0 : DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
296 0 : return ret;
297 : }
298 :
299 : /* Write low address of the ring to C2PMSG_69 */
300 0 : psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
301 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
302 : /* Write high address of the ring to C2PMSG_70 */
303 0 : psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
304 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
305 : /* Write size of ring to C2PMSG_71 */
306 0 : psp_ring_reg = ring->ring_size;
307 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
308 : /* Write the ring initialization command to C2PMSG_64 */
309 0 : psp_ring_reg = ring_type;
310 0 : psp_ring_reg = psp_ring_reg << 16;
311 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
312 :
313 : /* there might be handshake issue with hardware which needs delay */
314 0 : mdelay(20);
315 :
316 : /* Wait for response flag (bit 31) in C2PMSG_64 */
317 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
318 : 0x80000000, 0x8000FFFF, false);
319 : }
320 :
321 : return ret;
322 : }
323 :
324 0 : static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
325 : enum psp_ring_type ring_type)
326 : {
327 0 : int ret = 0;
328 0 : struct psp_ring *ring = &psp->km_ring;
329 0 : struct amdgpu_device *adev = psp->adev;
330 :
331 0 : ret = psp_v13_0_4_ring_stop(psp, ring_type);
332 0 : if (ret)
333 0 : DRM_ERROR("Fail to stop psp ring\n");
334 :
335 0 : amdgpu_bo_free_kernel(&adev->firmware.rbuf,
336 0 : &ring->ring_mem_mc_addr,
337 0 : (void **)&ring->ring_mem);
338 :
339 0 : return ret;
340 : }
341 :
342 0 : static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
343 : {
344 : uint32_t data;
345 0 : struct amdgpu_device *adev = psp->adev;
346 :
347 0 : if (amdgpu_sriov_vf(adev))
348 0 : data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
349 : else
350 0 : data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
351 :
352 0 : return data;
353 : }
354 :
355 0 : static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
356 : {
357 0 : struct amdgpu_device *adev = psp->adev;
358 :
359 0 : if (amdgpu_sriov_vf(adev)) {
360 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
361 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
362 : GFX_CTRL_CMD_ID_CONSUME_CMD);
363 : } else
364 0 : WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
365 0 : }
366 :
367 : static const struct psp_funcs psp_v13_0_4_funcs = {
368 : .init_microcode = psp_v13_0_4_init_microcode,
369 : .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
370 : .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
371 : .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
372 : .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
373 : .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
374 : .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
375 : .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
376 : .ring_init = psp_v13_0_4_ring_init,
377 : .ring_create = psp_v13_0_4_ring_create,
378 : .ring_stop = psp_v13_0_4_ring_stop,
379 : .ring_destroy = psp_v13_0_4_ring_destroy,
380 : .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
381 : .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
382 : };
383 :
384 0 : void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
385 : {
386 0 : psp->funcs = &psp_v13_0_4_funcs;
387 0 : }
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