Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Author: Huang Rui
23 : *
24 : */
25 :
26 : #include <linux/firmware.h>
27 : #include <linux/module.h>
28 : #include <linux/pci.h>
29 :
30 : #include "amdgpu.h"
31 : #include "amdgpu_psp.h"
32 : #include "amdgpu_ucode.h"
33 : #include "soc15_common.h"
34 : #include "psp_v3_1.h"
35 :
36 : #include "mp/mp_9_0_offset.h"
37 : #include "mp/mp_9_0_sh_mask.h"
38 : #include "gc/gc_9_0_offset.h"
39 : #include "sdma0/sdma0_4_0_offset.h"
40 : #include "nbio/nbio_6_1_offset.h"
41 :
42 : #include "oss/osssys_4_0_offset.h"
43 : #include "oss/osssys_4_0_sh_mask.h"
44 :
45 : MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
46 : MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
47 : MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
48 : MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
49 : MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
50 :
51 :
52 : #define smnMP1_FIRMWARE_FLAGS 0x3010028
53 :
54 : static int psp_v3_1_ring_stop(struct psp_context *psp,
55 : enum psp_ring_type ring_type);
56 :
57 0 : static int psp_v3_1_init_microcode(struct psp_context *psp)
58 : {
59 0 : struct amdgpu_device *adev = psp->adev;
60 : const char *chip_name;
61 0 : int err = 0;
62 :
63 0 : DRM_DEBUG("\n");
64 :
65 0 : switch (adev->asic_type) {
66 : case CHIP_VEGA10:
67 : chip_name = "vega10";
68 : break;
69 : case CHIP_VEGA12:
70 0 : chip_name = "vega12";
71 0 : break;
72 0 : default: BUG();
73 : }
74 :
75 0 : err = psp_init_sos_microcode(psp, chip_name);
76 0 : if (err)
77 : return err;
78 :
79 0 : err = psp_init_asd_microcode(psp, chip_name);
80 0 : if (err)
81 : return err;
82 :
83 0 : return 0;
84 : }
85 :
86 0 : static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
87 : {
88 : int ret;
89 0 : uint32_t psp_gfxdrv_command_reg = 0;
90 0 : struct amdgpu_device *adev = psp->adev;
91 : uint32_t sol_reg;
92 :
93 : /* Check sOS sign of life register to confirm sys driver and sOS
94 : * are already been loaded.
95 : */
96 0 : sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
97 0 : if (sol_reg)
98 : return 0;
99 :
100 : /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
101 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
102 : 0x80000000, 0x80000000, false);
103 0 : if (ret)
104 : return ret;
105 :
106 : /* Copy PSP System Driver binary to memory */
107 0 : psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
108 :
109 : /* Provide the sys driver to bootloader */
110 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
111 : (uint32_t)(psp->fw_pri_mc_addr >> 20));
112 0 : psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
113 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
114 : psp_gfxdrv_command_reg);
115 :
116 : /* there might be handshake issue with hardware which needs delay */
117 0 : mdelay(20);
118 :
119 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
120 : 0x80000000, 0x80000000, false);
121 :
122 0 : return ret;
123 : }
124 :
125 0 : static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
126 : {
127 : int ret;
128 0 : unsigned int psp_gfxdrv_command_reg = 0;
129 0 : struct amdgpu_device *adev = psp->adev;
130 : uint32_t sol_reg;
131 :
132 : /* Check sOS sign of life register to confirm sys driver and sOS
133 : * are already been loaded.
134 : */
135 0 : sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
136 0 : if (sol_reg)
137 : return 0;
138 :
139 : /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
140 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
141 : 0x80000000, 0x80000000, false);
142 0 : if (ret)
143 : return ret;
144 :
145 : /* Copy Secure OS binary to PSP memory */
146 0 : psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
147 :
148 : /* Provide the PSP secure OS to bootloader */
149 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
150 : (uint32_t)(psp->fw_pri_mc_addr >> 20));
151 0 : psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
152 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
153 : psp_gfxdrv_command_reg);
154 :
155 : /* there might be handshake issue with hardware which needs delay */
156 0 : mdelay(20);
157 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
158 0 : RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
159 : 0, true);
160 0 : return ret;
161 : }
162 :
163 0 : static int psp_v3_1_ring_init(struct psp_context *psp,
164 : enum psp_ring_type ring_type)
165 : {
166 0 : int ret = 0;
167 : struct psp_ring *ring;
168 0 : struct amdgpu_device *adev = psp->adev;
169 :
170 0 : ring = &psp->km_ring;
171 :
172 0 : ring->ring_type = ring_type;
173 :
174 : /* allocate 4k Page of Local Frame Buffer memory for ring */
175 0 : ring->ring_size = 0x1000;
176 0 : ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
177 : AMDGPU_GEM_DOMAIN_VRAM,
178 : &adev->firmware.rbuf,
179 0 : &ring->ring_mem_mc_addr,
180 0 : (void **)&ring->ring_mem);
181 0 : if (ret) {
182 0 : ring->ring_size = 0;
183 0 : return ret;
184 : }
185 :
186 : return 0;
187 : }
188 :
189 0 : static void psp_v3_1_reroute_ih(struct psp_context *psp)
190 : {
191 0 : struct amdgpu_device *adev = psp->adev;
192 : uint32_t tmp;
193 :
194 : /* Change IH ring for VMC */
195 0 : tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
196 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
197 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
198 :
199 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
200 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
201 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
202 :
203 0 : mdelay(20);
204 0 : psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
205 : 0x80000000, 0x8000FFFF, false);
206 :
207 : /* Change IH ring for UMC */
208 0 : tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
209 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
210 :
211 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
212 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
213 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
214 :
215 0 : mdelay(20);
216 0 : psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
217 : 0x80000000, 0x8000FFFF, false);
218 0 : }
219 :
220 0 : static int psp_v3_1_ring_create(struct psp_context *psp,
221 : enum psp_ring_type ring_type)
222 : {
223 0 : int ret = 0;
224 0 : unsigned int psp_ring_reg = 0;
225 0 : struct psp_ring *ring = &psp->km_ring;
226 0 : struct amdgpu_device *adev = psp->adev;
227 :
228 0 : psp_v3_1_reroute_ih(psp);
229 :
230 0 : if (amdgpu_sriov_vf(adev)) {
231 0 : ring->ring_wptr = 0;
232 0 : ret = psp_v3_1_ring_stop(psp, ring_type);
233 0 : if (ret) {
234 0 : DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
235 0 : return ret;
236 : }
237 :
238 : /* Write low address of the ring to C2PMSG_102 */
239 0 : psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
240 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
241 : /* Write high address of the ring to C2PMSG_103 */
242 0 : psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
243 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
244 : /* No size initialization for sriov */
245 : /* Write the ring initialization command to C2PMSG_101 */
246 0 : psp_ring_reg = ring_type;
247 0 : psp_ring_reg = psp_ring_reg << 16;
248 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
249 :
250 : /* there might be hardware handshake issue which needs delay */
251 0 : mdelay(20);
252 :
253 : /* Wait for response flag (bit 31) in C2PMSG_101 */
254 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
255 : mmMP0_SMN_C2PMSG_101), 0x80000000,
256 : 0x8000FFFF, false);
257 : } else {
258 :
259 : /* Write low address of the ring to C2PMSG_69 */
260 0 : psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
261 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
262 : /* Write high address of the ring to C2PMSG_70 */
263 0 : psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
264 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
265 : /* Write size of ring to C2PMSG_71 */
266 0 : psp_ring_reg = ring->ring_size;
267 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
268 : /* Write the ring initialization command to C2PMSG_64 */
269 0 : psp_ring_reg = ring_type;
270 0 : psp_ring_reg = psp_ring_reg << 16;
271 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
272 :
273 : /* there might be hardware handshake issue which needs delay */
274 0 : mdelay(20);
275 :
276 : /* Wait for response flag (bit 31) in C2PMSG_64 */
277 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
278 : mmMP0_SMN_C2PMSG_64), 0x80000000,
279 : 0x8000FFFF, false);
280 :
281 : }
282 : return ret;
283 : }
284 :
285 0 : static int psp_v3_1_ring_stop(struct psp_context *psp,
286 : enum psp_ring_type ring_type)
287 : {
288 0 : int ret = 0;
289 0 : struct amdgpu_device *adev = psp->adev;
290 :
291 : /* Write the ring destroy command*/
292 0 : if (amdgpu_sriov_vf(adev))
293 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
294 : GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
295 : else
296 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
297 : GFX_CTRL_CMD_ID_DESTROY_RINGS);
298 :
299 : /* there might be handshake issue with hardware which needs delay */
300 0 : mdelay(20);
301 :
302 : /* Wait for response flag (bit 31) */
303 0 : if (amdgpu_sriov_vf(adev))
304 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
305 : 0x80000000, 0x80000000, false);
306 : else
307 0 : ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
308 : 0x80000000, 0x80000000, false);
309 :
310 0 : return ret;
311 : }
312 :
313 0 : static int psp_v3_1_ring_destroy(struct psp_context *psp,
314 : enum psp_ring_type ring_type)
315 : {
316 0 : int ret = 0;
317 0 : struct psp_ring *ring = &psp->km_ring;
318 0 : struct amdgpu_device *adev = psp->adev;
319 :
320 0 : ret = psp_v3_1_ring_stop(psp, ring_type);
321 0 : if (ret)
322 0 : DRM_ERROR("Fail to stop psp ring\n");
323 :
324 0 : amdgpu_bo_free_kernel(&adev->firmware.rbuf,
325 0 : &ring->ring_mem_mc_addr,
326 0 : (void **)&ring->ring_mem);
327 :
328 0 : return ret;
329 : }
330 :
331 0 : static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
332 : {
333 0 : struct amdgpu_device *adev = psp->adev;
334 : uint32_t reg;
335 :
336 0 : reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
337 0 : return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
338 : }
339 :
340 0 : static int psp_v3_1_mode1_reset(struct psp_context *psp)
341 : {
342 : int ret;
343 : uint32_t offset;
344 0 : struct amdgpu_device *adev = psp->adev;
345 :
346 0 : offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
347 :
348 0 : ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
349 :
350 0 : if (ret) {
351 0 : DRM_INFO("psp is not working correctly before mode1 reset!\n");
352 0 : return -EINVAL;
353 : }
354 :
355 : /*send the mode 1 reset command*/
356 0 : WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
357 :
358 0 : msleep(500);
359 :
360 0 : offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
361 :
362 0 : ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
363 :
364 0 : if (ret) {
365 0 : DRM_INFO("psp mode 1 reset failed!\n");
366 0 : return -EINVAL;
367 : }
368 :
369 0 : DRM_INFO("psp mode1 reset succeed \n");
370 :
371 0 : return 0;
372 : }
373 :
374 0 : static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
375 : {
376 : uint32_t data;
377 0 : struct amdgpu_device *adev = psp->adev;
378 :
379 0 : if (amdgpu_sriov_vf(adev))
380 0 : data = psp->km_ring.ring_wptr;
381 : else
382 0 : data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
383 0 : return data;
384 : }
385 :
386 0 : static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
387 : {
388 0 : struct amdgpu_device *adev = psp->adev;
389 :
390 0 : if (amdgpu_sriov_vf(adev)) {
391 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
392 : /* send interrupt to PSP for SRIOV ring write pointer update */
393 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
394 : GFX_CTRL_CMD_ID_CONSUME_CMD);
395 0 : psp->km_ring.ring_wptr = value;
396 : } else
397 0 : WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
398 0 : }
399 :
400 : static const struct psp_funcs psp_v3_1_funcs = {
401 : .init_microcode = psp_v3_1_init_microcode,
402 : .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
403 : .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
404 : .ring_init = psp_v3_1_ring_init,
405 : .ring_create = psp_v3_1_ring_create,
406 : .ring_stop = psp_v3_1_ring_stop,
407 : .ring_destroy = psp_v3_1_ring_destroy,
408 : .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
409 : .mode1_reset = psp_v3_1_mode1_reset,
410 : .ring_get_wptr = psp_v3_1_ring_get_wptr,
411 : .ring_set_wptr = psp_v3_1_ring_set_wptr,
412 : };
413 :
414 0 : void psp_v3_1_set_psp_funcs(struct psp_context *psp)
415 : {
416 0 : psp->funcs = &psp_v3_1_funcs;
417 0 : }
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