Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/delay.h>
25 : #include <linux/firmware.h>
26 : #include <linux/module.h>
27 : #include <linux/pci.h>
28 :
29 : #include "amdgpu.h"
30 : #include "amdgpu_ucode.h"
31 : #include "amdgpu_trace.h"
32 :
33 : #include "sdma0/sdma0_4_2_offset.h"
34 : #include "sdma0/sdma0_4_2_sh_mask.h"
35 : #include "sdma1/sdma1_4_2_offset.h"
36 : #include "sdma1/sdma1_4_2_sh_mask.h"
37 : #include "sdma2/sdma2_4_2_2_offset.h"
38 : #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 : #include "sdma3/sdma3_4_2_2_offset.h"
40 : #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 : #include "sdma4/sdma4_4_2_2_offset.h"
42 : #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 : #include "sdma5/sdma5_4_2_2_offset.h"
44 : #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 : #include "sdma6/sdma6_4_2_2_offset.h"
46 : #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 : #include "sdma7/sdma7_4_2_2_offset.h"
48 : #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 : #include "sdma0/sdma0_4_1_default.h"
50 :
51 : #include "soc15_common.h"
52 : #include "soc15.h"
53 : #include "vega10_sdma_pkt_open.h"
54 :
55 : #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
56 : #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
57 :
58 : #include "amdgpu_ras.h"
59 : #include "sdma_v4_4.h"
60 :
61 : MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 : MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 : MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 : MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 : MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 : MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 : MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 : MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 : MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 : MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 : MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72 : MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
73 : MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
74 :
75 : #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
76 : #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
77 :
78 : #define WREG32_SDMA(instance, offset, value) \
79 : WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
80 : #define RREG32_SDMA(instance, offset) \
81 : RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
82 :
83 : static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
84 : static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
85 : static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
86 : static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
87 : static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
88 :
89 : static const struct soc15_reg_golden golden_settings_sdma_4[] = {
90 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
100 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
102 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
103 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
104 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
105 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
107 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
109 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
110 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
112 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
114 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 : };
116 :
117 : static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
118 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
120 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
121 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
122 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
123 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
124 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
125 : };
126 :
127 : static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
128 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
129 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
130 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
131 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
133 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
134 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
135 : };
136 :
137 : static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
138 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
139 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
140 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
141 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
143 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
144 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
146 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
148 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
149 : };
150 :
151 : static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
152 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
153 : };
154 :
155 : static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
156 : {
157 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
158 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
160 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
161 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
166 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
183 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
184 : };
185 :
186 : static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
187 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
188 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
189 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
190 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
191 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
196 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
198 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
211 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
213 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
214 : };
215 :
216 : static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
217 : {
218 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
219 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
220 : };
221 :
222 : static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
223 : {
224 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
225 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
226 : };
227 :
228 : static const struct soc15_reg_golden golden_settings_sdma_arct[] =
229 : {
230 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
234 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
238 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
239 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
240 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
241 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
242 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
245 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
246 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
247 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
248 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
249 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
250 : SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
251 : SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
252 : SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
253 : SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
254 : SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
255 : SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
256 : SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
257 : SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
258 : SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
259 : SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
260 : SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
261 : SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
262 : };
263 :
264 : static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
265 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
266 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
267 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
268 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
269 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
270 : SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
271 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
272 : SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
273 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
274 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
275 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
276 : SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
277 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
278 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
279 : SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
280 : };
281 :
282 : static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
283 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
284 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
285 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
286 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
287 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
288 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
289 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
290 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
291 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
292 : SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
293 : };
294 :
295 : static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
296 : { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
297 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
298 : 0, 0,
299 : },
300 : { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
301 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
302 : 0, 0,
303 : },
304 : { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
305 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
306 : 0, 0,
307 : },
308 : { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
309 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
310 : 0, 0,
311 : },
312 : { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
313 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
314 : 0, 0,
315 : },
316 : { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
317 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
318 : 0, 0,
319 : },
320 : { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
321 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
322 : 0, 0,
323 : },
324 : { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
325 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
326 : 0, 0,
327 : },
328 : { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
329 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
330 : 0, 0,
331 : },
332 : { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
333 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
334 : 0, 0,
335 : },
336 : { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
337 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
338 : 0, 0,
339 : },
340 : { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
341 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
342 : 0, 0,
343 : },
344 : { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
345 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
346 : 0, 0,
347 : },
348 : { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
349 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
350 : 0, 0,
351 : },
352 : { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
353 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
354 : 0, 0,
355 : },
356 : { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
357 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
358 : 0, 0,
359 : },
360 : { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
361 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
362 : 0, 0,
363 : },
364 : { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
365 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
366 : 0, 0,
367 : },
368 : { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
369 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
370 : 0, 0,
371 : },
372 : { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
373 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
374 : 0, 0,
375 : },
376 : { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
377 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
378 : 0, 0,
379 : },
380 : { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
381 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
382 : 0, 0,
383 : },
384 : { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
385 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
386 : 0, 0,
387 : },
388 : { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
389 : SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
390 : 0, 0,
391 : },
392 : };
393 :
394 0 : static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
395 : u32 instance, u32 offset)
396 : {
397 0 : switch (instance) {
398 : case 0:
399 0 : return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
400 : case 1:
401 0 : return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
402 : case 2:
403 0 : return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
404 : case 3:
405 0 : return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
406 : case 4:
407 0 : return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
408 : case 5:
409 0 : return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
410 : case 6:
411 0 : return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
412 : case 7:
413 0 : return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
414 : default:
415 : break;
416 : }
417 : return 0;
418 : }
419 :
420 : static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
421 : {
422 : switch (seq_num) {
423 : case 0:
424 : return SOC15_IH_CLIENTID_SDMA0;
425 : case 1:
426 : return SOC15_IH_CLIENTID_SDMA1;
427 : case 2:
428 : return SOC15_IH_CLIENTID_SDMA2;
429 : case 3:
430 : return SOC15_IH_CLIENTID_SDMA3;
431 : case 4:
432 : return SOC15_IH_CLIENTID_SDMA4;
433 : case 5:
434 : return SOC15_IH_CLIENTID_SDMA5;
435 : case 6:
436 : return SOC15_IH_CLIENTID_SDMA6;
437 : case 7:
438 : return SOC15_IH_CLIENTID_SDMA7;
439 : default:
440 : break;
441 : }
442 : return -EINVAL;
443 : }
444 :
445 : static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
446 : {
447 : switch (client_id) {
448 : case SOC15_IH_CLIENTID_SDMA0:
449 : return 0;
450 : case SOC15_IH_CLIENTID_SDMA1:
451 : return 1;
452 : case SOC15_IH_CLIENTID_SDMA2:
453 : return 2;
454 : case SOC15_IH_CLIENTID_SDMA3:
455 : return 3;
456 : case SOC15_IH_CLIENTID_SDMA4:
457 : return 4;
458 : case SOC15_IH_CLIENTID_SDMA5:
459 : return 5;
460 : case SOC15_IH_CLIENTID_SDMA6:
461 : return 6;
462 : case SOC15_IH_CLIENTID_SDMA7:
463 : return 7;
464 : default:
465 : break;
466 : }
467 : return -EINVAL;
468 : }
469 :
470 0 : static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
471 : {
472 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
473 : case IP_VERSION(4, 0, 0):
474 0 : soc15_program_register_sequence(adev,
475 : golden_settings_sdma_4,
476 : ARRAY_SIZE(golden_settings_sdma_4));
477 0 : soc15_program_register_sequence(adev,
478 : golden_settings_sdma_vg10,
479 : ARRAY_SIZE(golden_settings_sdma_vg10));
480 0 : break;
481 : case IP_VERSION(4, 0, 1):
482 0 : soc15_program_register_sequence(adev,
483 : golden_settings_sdma_4,
484 : ARRAY_SIZE(golden_settings_sdma_4));
485 0 : soc15_program_register_sequence(adev,
486 : golden_settings_sdma_vg12,
487 : ARRAY_SIZE(golden_settings_sdma_vg12));
488 0 : break;
489 : case IP_VERSION(4, 2, 0):
490 0 : soc15_program_register_sequence(adev,
491 : golden_settings_sdma0_4_2_init,
492 : ARRAY_SIZE(golden_settings_sdma0_4_2_init));
493 0 : soc15_program_register_sequence(adev,
494 : golden_settings_sdma0_4_2,
495 : ARRAY_SIZE(golden_settings_sdma0_4_2));
496 0 : soc15_program_register_sequence(adev,
497 : golden_settings_sdma1_4_2,
498 : ARRAY_SIZE(golden_settings_sdma1_4_2));
499 0 : break;
500 : case IP_VERSION(4, 2, 2):
501 0 : soc15_program_register_sequence(adev,
502 : golden_settings_sdma_arct,
503 : ARRAY_SIZE(golden_settings_sdma_arct));
504 0 : break;
505 : case IP_VERSION(4, 4, 0):
506 0 : soc15_program_register_sequence(adev,
507 : golden_settings_sdma_aldebaran,
508 : ARRAY_SIZE(golden_settings_sdma_aldebaran));
509 0 : break;
510 : case IP_VERSION(4, 1, 0):
511 : case IP_VERSION(4, 1, 1):
512 0 : soc15_program_register_sequence(adev,
513 : golden_settings_sdma_4_1,
514 : ARRAY_SIZE(golden_settings_sdma_4_1));
515 0 : if (adev->apu_flags & AMD_APU_IS_RAVEN2)
516 0 : soc15_program_register_sequence(adev,
517 : golden_settings_sdma_rv2,
518 : ARRAY_SIZE(golden_settings_sdma_rv2));
519 : else
520 0 : soc15_program_register_sequence(adev,
521 : golden_settings_sdma_rv1,
522 : ARRAY_SIZE(golden_settings_sdma_rv1));
523 : break;
524 : case IP_VERSION(4, 1, 2):
525 0 : soc15_program_register_sequence(adev,
526 : golden_settings_sdma_4_3,
527 : ARRAY_SIZE(golden_settings_sdma_4_3));
528 0 : break;
529 : default:
530 : break;
531 : }
532 0 : }
533 :
534 0 : static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
535 : {
536 : int i;
537 :
538 : /*
539 : * The only chips with SDMAv4 and ULV are VG10 and VG20.
540 : * Server SKUs take a different hysteresis setting from other SKUs.
541 : */
542 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
543 : case IP_VERSION(4, 0, 0):
544 0 : if (adev->pdev->device == 0x6860)
545 : break;
546 : return;
547 : case IP_VERSION(4, 2, 0):
548 0 : if (adev->pdev->device == 0x66a1)
549 : break;
550 : return;
551 : default:
552 : return;
553 : }
554 :
555 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
556 : uint32_t temp;
557 :
558 0 : temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
559 0 : temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
560 0 : WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
561 : }
562 : }
563 :
564 0 : static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
565 : {
566 0 : int err = 0;
567 : const struct sdma_firmware_header_v1_0 *hdr;
568 :
569 0 : err = amdgpu_ucode_validate(sdma_inst->fw);
570 0 : if (err)
571 : return err;
572 :
573 0 : hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
574 0 : sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
575 0 : sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
576 :
577 0 : if (sdma_inst->feature_version >= 20)
578 0 : sdma_inst->burst_nop = true;
579 :
580 : return 0;
581 : }
582 :
583 0 : static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
584 : {
585 : int i;
586 :
587 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
588 0 : release_firmware(adev->sdma.instance[i].fw);
589 0 : adev->sdma.instance[i].fw = NULL;
590 :
591 : /* arcturus shares the same FW memory across
592 : all SDMA isntances */
593 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
594 : adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
595 : break;
596 : }
597 :
598 0 : memset((void *)adev->sdma.instance, 0,
599 : sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
600 0 : }
601 :
602 : /**
603 : * sdma_v4_0_init_microcode - load ucode images from disk
604 : *
605 : * @adev: amdgpu_device pointer
606 : *
607 : * Use the firmware interface to load the ucode images into
608 : * the driver (not loaded into hw).
609 : * Returns 0 on success, error on failure.
610 : */
611 :
612 : // emulation only, won't work on real chip
613 : // vega10 real chip need to use PSP to load firmware
614 0 : static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
615 : {
616 : const char *chip_name;
617 : char fw_name[30];
618 0 : int err = 0, i;
619 0 : struct amdgpu_firmware_info *info = NULL;
620 0 : const struct common_firmware_header *header = NULL;
621 :
622 0 : DRM_DEBUG("\n");
623 :
624 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
625 : case IP_VERSION(4, 0, 0):
626 : chip_name = "vega10";
627 : break;
628 : case IP_VERSION(4, 0, 1):
629 0 : chip_name = "vega12";
630 0 : break;
631 : case IP_VERSION(4, 2, 0):
632 0 : chip_name = "vega20";
633 0 : break;
634 : case IP_VERSION(4, 1, 0):
635 : case IP_VERSION(4, 1, 1):
636 0 : if (adev->apu_flags & AMD_APU_IS_RAVEN2)
637 : chip_name = "raven2";
638 0 : else if (adev->apu_flags & AMD_APU_IS_PICASSO)
639 : chip_name = "picasso";
640 : else
641 0 : chip_name = "raven";
642 : break;
643 : case IP_VERSION(4, 2, 2):
644 0 : chip_name = "arcturus";
645 0 : break;
646 : case IP_VERSION(4, 1, 2):
647 0 : if (adev->apu_flags & AMD_APU_IS_RENOIR)
648 : chip_name = "renoir";
649 : else
650 0 : chip_name = "green_sardine";
651 : break;
652 : case IP_VERSION(4, 4, 0):
653 0 : chip_name = "aldebaran";
654 0 : break;
655 : default:
656 0 : BUG();
657 : }
658 :
659 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
660 :
661 0 : err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
662 0 : if (err)
663 : goto out;
664 :
665 0 : err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
666 0 : if (err)
667 : goto out;
668 :
669 0 : for (i = 1; i < adev->sdma.num_instances; i++) {
670 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
671 : adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
672 : /* Acturus & Aldebaran will leverage the same FW memory
673 : for every SDMA instance */
674 0 : memcpy((void *)&adev->sdma.instance[i],
675 : (void *)&adev->sdma.instance[0],
676 : sizeof(struct amdgpu_sdma_instance));
677 : }
678 : else {
679 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
680 :
681 0 : err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
682 0 : if (err)
683 : goto out;
684 :
685 0 : err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
686 0 : if (err)
687 : goto out;
688 : }
689 : }
690 :
691 0 : DRM_DEBUG("psp_load == '%s'\n",
692 : adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
693 :
694 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
695 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
696 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
697 0 : info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
698 0 : info->fw = adev->sdma.instance[i].fw;
699 0 : header = (const struct common_firmware_header *)info->fw->data;
700 0 : adev->firmware.fw_size +=
701 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
702 : }
703 : }
704 :
705 : out:
706 0 : if (err) {
707 0 : DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
708 0 : sdma_v4_0_destroy_inst_ctx(adev);
709 : }
710 0 : return err;
711 : }
712 :
713 : /**
714 : * sdma_v4_0_ring_get_rptr - get the current read pointer
715 : *
716 : * @ring: amdgpu ring pointer
717 : *
718 : * Get the current rptr from the hardware (VEGA10+).
719 : */
720 0 : static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
721 : {
722 : u64 *rptr;
723 :
724 : /* XXX check if swapping is necessary on BE */
725 0 : rptr = ((u64 *)ring->rptr_cpu_addr);
726 :
727 0 : DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
728 0 : return ((*rptr) >> 2);
729 : }
730 :
731 : /**
732 : * sdma_v4_0_ring_get_wptr - get the current write pointer
733 : *
734 : * @ring: amdgpu ring pointer
735 : *
736 : * Get the current wptr from the hardware (VEGA10+).
737 : */
738 0 : static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
739 : {
740 0 : struct amdgpu_device *adev = ring->adev;
741 : u64 wptr;
742 :
743 0 : if (ring->use_doorbell) {
744 : /* XXX check if swapping is necessary on BE */
745 0 : wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
746 0 : DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
747 : } else {
748 0 : wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
749 0 : wptr = wptr << 32;
750 0 : wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
751 0 : DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
752 : ring->me, wptr);
753 : }
754 :
755 0 : return wptr >> 2;
756 : }
757 :
758 : /**
759 : * sdma_v4_0_ring_set_wptr - commit the write pointer
760 : *
761 : * @ring: amdgpu ring pointer
762 : *
763 : * Write the wptr back to the hardware (VEGA10+).
764 : */
765 0 : static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
766 : {
767 0 : struct amdgpu_device *adev = ring->adev;
768 :
769 0 : DRM_DEBUG("Setting write pointer\n");
770 0 : if (ring->use_doorbell) {
771 0 : u64 *wb = (u64 *)ring->wptr_cpu_addr;
772 :
773 0 : DRM_DEBUG("Using doorbell -- "
774 : "wptr_offs == 0x%08x "
775 : "lower_32_bits(ring->wptr << 2) == 0x%08x "
776 : "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
777 : ring->wptr_offs,
778 : lower_32_bits(ring->wptr << 2),
779 : upper_32_bits(ring->wptr << 2));
780 : /* XXX check if swapping is necessary on BE */
781 0 : WRITE_ONCE(*wb, (ring->wptr << 2));
782 0 : DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
783 : ring->doorbell_index, ring->wptr << 2);
784 0 : WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
785 : } else {
786 0 : DRM_DEBUG("Not using doorbell -- "
787 : "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
788 : "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
789 : ring->me,
790 : lower_32_bits(ring->wptr << 2),
791 : ring->me,
792 : upper_32_bits(ring->wptr << 2));
793 0 : WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
794 : lower_32_bits(ring->wptr << 2));
795 0 : WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
796 : upper_32_bits(ring->wptr << 2));
797 : }
798 0 : }
799 :
800 : /**
801 : * sdma_v4_0_page_ring_get_wptr - get the current write pointer
802 : *
803 : * @ring: amdgpu ring pointer
804 : *
805 : * Get the current wptr from the hardware (VEGA10+).
806 : */
807 0 : static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
808 : {
809 0 : struct amdgpu_device *adev = ring->adev;
810 : u64 wptr;
811 :
812 0 : if (ring->use_doorbell) {
813 : /* XXX check if swapping is necessary on BE */
814 0 : wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
815 : } else {
816 0 : wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
817 0 : wptr = wptr << 32;
818 0 : wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
819 : }
820 :
821 0 : return wptr >> 2;
822 : }
823 :
824 : /**
825 : * sdma_v4_0_page_ring_set_wptr - commit the write pointer
826 : *
827 : * @ring: amdgpu ring pointer
828 : *
829 : * Write the wptr back to the hardware (VEGA10+).
830 : */
831 0 : static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
832 : {
833 0 : struct amdgpu_device *adev = ring->adev;
834 :
835 0 : if (ring->use_doorbell) {
836 0 : u64 *wb = (u64 *)ring->wptr_cpu_addr;
837 :
838 : /* XXX check if swapping is necessary on BE */
839 0 : WRITE_ONCE(*wb, (ring->wptr << 2));
840 0 : WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
841 : } else {
842 0 : uint64_t wptr = ring->wptr << 2;
843 :
844 0 : WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
845 : lower_32_bits(wptr));
846 0 : WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
847 : upper_32_bits(wptr));
848 : }
849 0 : }
850 :
851 0 : static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
852 : {
853 0 : struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
854 : int i;
855 :
856 0 : for (i = 0; i < count; i++)
857 0 : if (sdma && sdma->burst_nop && (i == 0))
858 0 : amdgpu_ring_write(ring, ring->funcs->nop |
859 0 : SDMA_PKT_NOP_HEADER_COUNT(count - 1));
860 : else
861 0 : amdgpu_ring_write(ring, ring->funcs->nop);
862 0 : }
863 :
864 : /**
865 : * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
866 : *
867 : * @ring: amdgpu ring pointer
868 : * @job: job to retrieve vmid from
869 : * @ib: IB object to schedule
870 : * @flags: unused
871 : *
872 : * Schedule an IB in the DMA ring (VEGA10).
873 : */
874 0 : static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
875 : struct amdgpu_job *job,
876 : struct amdgpu_ib *ib,
877 : uint32_t flags)
878 : {
879 0 : unsigned vmid = AMDGPU_JOB_GET_VMID(job);
880 :
881 : /* IB packet must end on a 8 DW boundary */
882 0 : sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
883 :
884 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
885 0 : SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
886 : /* base must be 32 byte aligned */
887 0 : amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
888 0 : amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
889 0 : amdgpu_ring_write(ring, ib->length_dw);
890 0 : amdgpu_ring_write(ring, 0);
891 0 : amdgpu_ring_write(ring, 0);
892 :
893 0 : }
894 :
895 0 : static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
896 : int mem_space, int hdp,
897 : uint32_t addr0, uint32_t addr1,
898 : uint32_t ref, uint32_t mask,
899 : uint32_t inv)
900 : {
901 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
902 0 : SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
903 0 : SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
904 : SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
905 0 : if (mem_space) {
906 : /* memory */
907 0 : amdgpu_ring_write(ring, addr0);
908 0 : amdgpu_ring_write(ring, addr1);
909 : } else {
910 : /* registers */
911 0 : amdgpu_ring_write(ring, addr0 << 2);
912 0 : amdgpu_ring_write(ring, addr1 << 2);
913 : }
914 0 : amdgpu_ring_write(ring, ref); /* reference */
915 0 : amdgpu_ring_write(ring, mask); /* mask */
916 0 : amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
917 0 : SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
918 0 : }
919 :
920 : /**
921 : * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
922 : *
923 : * @ring: amdgpu ring pointer
924 : *
925 : * Emit an hdp flush packet on the requested DMA ring.
926 : */
927 0 : static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
928 : {
929 0 : struct amdgpu_device *adev = ring->adev;
930 0 : u32 ref_and_mask = 0;
931 0 : const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
932 :
933 0 : ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
934 :
935 0 : sdma_v4_0_wait_reg_mem(ring, 0, 1,
936 0 : adev->nbio.funcs->get_hdp_flush_done_offset(adev),
937 0 : adev->nbio.funcs->get_hdp_flush_req_offset(adev),
938 : ref_and_mask, ref_and_mask, 10);
939 0 : }
940 :
941 : /**
942 : * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
943 : *
944 : * @ring: amdgpu ring pointer
945 : * @addr: address
946 : * @seq: sequence number
947 : * @flags: fence related flags
948 : *
949 : * Add a DMA fence packet to the ring to write
950 : * the fence seq number and DMA trap packet to generate
951 : * an interrupt if needed (VEGA10).
952 : */
953 0 : static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
954 : unsigned flags)
955 : {
956 0 : bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
957 : /* write the fence */
958 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
959 : /* zero in first two bits */
960 0 : BUG_ON(addr & 0x3);
961 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
962 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
963 0 : amdgpu_ring_write(ring, lower_32_bits(seq));
964 :
965 : /* optionally write high bits as well */
966 0 : if (write64bit) {
967 0 : addr += 4;
968 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
969 : /* zero in first two bits */
970 0 : BUG_ON(addr & 0x3);
971 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
972 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
973 0 : amdgpu_ring_write(ring, upper_32_bits(seq));
974 : }
975 :
976 : /* generate an interrupt */
977 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
978 0 : amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
979 0 : }
980 :
981 :
982 : /**
983 : * sdma_v4_0_gfx_stop - stop the gfx async dma engines
984 : *
985 : * @adev: amdgpu_device pointer
986 : *
987 : * Stop the gfx async dma ring buffers (VEGA10).
988 : */
989 0 : static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
990 : {
991 : struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
992 : u32 rb_cntl, ib_cntl;
993 0 : int i, unset = 0;
994 :
995 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
996 0 : sdma[i] = &adev->sdma.instance[i].ring;
997 :
998 0 : if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
999 0 : amdgpu_ttm_set_buffer_funcs_status(adev, false);
1000 0 : unset = 1;
1001 : }
1002 :
1003 0 : rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1004 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
1005 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1006 0 : ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1007 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
1008 0 : WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1009 : }
1010 0 : }
1011 :
1012 : /**
1013 : * sdma_v4_0_rlc_stop - stop the compute async dma engines
1014 : *
1015 : * @adev: amdgpu_device pointer
1016 : *
1017 : * Stop the compute async dma queues (VEGA10).
1018 : */
1019 : static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
1020 : {
1021 : /* XXX todo */
1022 : }
1023 :
1024 : /**
1025 : * sdma_v4_0_page_stop - stop the page async dma engines
1026 : *
1027 : * @adev: amdgpu_device pointer
1028 : *
1029 : * Stop the page async dma ring buffers (VEGA10).
1030 : */
1031 0 : static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1032 : {
1033 : struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1034 : u32 rb_cntl, ib_cntl;
1035 : int i;
1036 0 : bool unset = false;
1037 :
1038 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1039 0 : sdma[i] = &adev->sdma.instance[i].page;
1040 :
1041 0 : if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1042 : (!unset)) {
1043 0 : amdgpu_ttm_set_buffer_funcs_status(adev, false);
1044 0 : unset = true;
1045 : }
1046 :
1047 0 : rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1048 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1049 : RB_ENABLE, 0);
1050 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1051 0 : ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1052 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1053 : IB_ENABLE, 0);
1054 0 : WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1055 : }
1056 0 : }
1057 :
1058 : /**
1059 : * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1060 : *
1061 : * @adev: amdgpu_device pointer
1062 : * @enable: enable/disable the DMA MEs context switch.
1063 : *
1064 : * Halt or unhalt the async dma engines context switch (VEGA10).
1065 : */
1066 0 : static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1067 : {
1068 0 : u32 f32_cntl, phase_quantum = 0;
1069 : int i;
1070 :
1071 0 : if (amdgpu_sdma_phase_quantum) {
1072 : unsigned value = amdgpu_sdma_phase_quantum;
1073 : unsigned unit = 0;
1074 :
1075 0 : while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1076 : SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1077 0 : value = (value + 1) >> 1;
1078 0 : unit++;
1079 : }
1080 0 : if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1081 : SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1082 0 : value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1083 : SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1084 0 : unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1085 : SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1086 0 : WARN_ONCE(1,
1087 : "clamping sdma_phase_quantum to %uK clock cycles\n",
1088 : value << unit);
1089 : }
1090 0 : phase_quantum =
1091 0 : value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1092 : unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1093 : }
1094 :
1095 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1096 0 : f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1097 0 : f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1098 : AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1099 0 : if (enable && amdgpu_sdma_phase_quantum) {
1100 0 : WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1101 0 : WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1102 0 : WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1103 : }
1104 0 : WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1105 :
1106 : /*
1107 : * Enable SDMA utilization. Its only supported on
1108 : * Arcturus for the moment and firmware version 14
1109 : * and above.
1110 : */
1111 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
1112 0 : adev->sdma.instance[i].fw_version >= 14)
1113 0 : WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1114 : /* Extend page fault timeout to avoid interrupt storm */
1115 0 : WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
1116 : }
1117 :
1118 0 : }
1119 :
1120 : /**
1121 : * sdma_v4_0_enable - stop the async dma engines
1122 : *
1123 : * @adev: amdgpu_device pointer
1124 : * @enable: enable/disable the DMA MEs.
1125 : *
1126 : * Halt or unhalt the async dma engines (VEGA10).
1127 : */
1128 0 : static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1129 : {
1130 : u32 f32_cntl;
1131 : int i;
1132 :
1133 0 : if (!enable) {
1134 0 : sdma_v4_0_gfx_stop(adev);
1135 0 : sdma_v4_0_rlc_stop(adev);
1136 0 : if (adev->sdma.has_page_queue)
1137 0 : sdma_v4_0_page_stop(adev);
1138 : }
1139 :
1140 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1141 0 : f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1142 0 : f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1143 0 : WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1144 : }
1145 0 : }
1146 :
1147 : /*
1148 : * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1149 : */
1150 0 : static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1151 : {
1152 : /* Set ring buffer size in dwords */
1153 0 : uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1154 :
1155 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1156 : #ifdef __BIG_ENDIAN
1157 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1158 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1159 : RPTR_WRITEBACK_SWAP_ENABLE, 1);
1160 : #endif
1161 0 : return rb_cntl;
1162 : }
1163 :
1164 : /**
1165 : * sdma_v4_0_gfx_resume - setup and start the async dma engines
1166 : *
1167 : * @adev: amdgpu_device pointer
1168 : * @i: instance to resume
1169 : *
1170 : * Set up the gfx DMA ring buffers and enable them (VEGA10).
1171 : * Returns 0 for success, error for failure.
1172 : */
1173 0 : static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1174 : {
1175 0 : struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1176 : u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1177 : u32 doorbell;
1178 : u32 doorbell_offset;
1179 : u64 wptr_gpu_addr;
1180 :
1181 0 : rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1182 0 : rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1183 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1184 :
1185 : /* Initialize the ring buffer's read and write pointers */
1186 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1187 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1188 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1189 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1190 :
1191 : /* set the wb address whether it's enabled or not */
1192 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1193 : upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1194 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1195 : lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1196 :
1197 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1198 : RPTR_WRITEBACK_ENABLE, 1);
1199 :
1200 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1201 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1202 :
1203 0 : ring->wptr = 0;
1204 :
1205 : /* before programing wptr to a less value, need set minor_ptr_update first */
1206 0 : WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1207 :
1208 0 : doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1209 0 : doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1210 :
1211 0 : doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1212 : ring->use_doorbell);
1213 0 : doorbell_offset = REG_SET_FIELD(doorbell_offset,
1214 : SDMA0_GFX_DOORBELL_OFFSET,
1215 : OFFSET, ring->doorbell_index);
1216 0 : WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1217 0 : WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1218 :
1219 0 : sdma_v4_0_ring_set_wptr(ring);
1220 :
1221 : /* set minor_ptr_update to 0 after wptr programed */
1222 0 : WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1223 :
1224 : /* setup the wptr shadow polling */
1225 0 : wptr_gpu_addr = ring->wptr_gpu_addr;
1226 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1227 : lower_32_bits(wptr_gpu_addr));
1228 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1229 : upper_32_bits(wptr_gpu_addr));
1230 0 : wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1231 0 : wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1232 : SDMA0_GFX_RB_WPTR_POLL_CNTL,
1233 : F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1234 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1235 :
1236 : /* enable DMA RB */
1237 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1238 0 : WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1239 :
1240 0 : ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1241 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1242 : #ifdef __BIG_ENDIAN
1243 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1244 : #endif
1245 : /* enable DMA IBs */
1246 0 : WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1247 :
1248 0 : ring->sched.ready = true;
1249 0 : }
1250 :
1251 : /**
1252 : * sdma_v4_0_page_resume - setup and start the async dma engines
1253 : *
1254 : * @adev: amdgpu_device pointer
1255 : * @i: instance to resume
1256 : *
1257 : * Set up the page DMA ring buffers and enable them (VEGA10).
1258 : * Returns 0 for success, error for failure.
1259 : */
1260 0 : static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1261 : {
1262 0 : struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1263 : u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1264 : u32 doorbell;
1265 : u32 doorbell_offset;
1266 : u64 wptr_gpu_addr;
1267 :
1268 0 : rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1269 0 : rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1270 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1271 :
1272 : /* Initialize the ring buffer's read and write pointers */
1273 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1274 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1275 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1276 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1277 :
1278 : /* set the wb address whether it's enabled or not */
1279 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1280 : upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1281 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1282 : lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1283 :
1284 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1285 : RPTR_WRITEBACK_ENABLE, 1);
1286 :
1287 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1288 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1289 :
1290 0 : ring->wptr = 0;
1291 :
1292 : /* before programing wptr to a less value, need set minor_ptr_update first */
1293 0 : WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1294 :
1295 0 : doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1296 0 : doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1297 :
1298 0 : doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1299 : ring->use_doorbell);
1300 0 : doorbell_offset = REG_SET_FIELD(doorbell_offset,
1301 : SDMA0_PAGE_DOORBELL_OFFSET,
1302 : OFFSET, ring->doorbell_index);
1303 0 : WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1304 0 : WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1305 :
1306 : /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1307 0 : sdma_v4_0_page_ring_set_wptr(ring);
1308 :
1309 : /* set minor_ptr_update to 0 after wptr programed */
1310 0 : WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1311 :
1312 : /* setup the wptr shadow polling */
1313 0 : wptr_gpu_addr = ring->wptr_gpu_addr;
1314 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1315 : lower_32_bits(wptr_gpu_addr));
1316 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1317 : upper_32_bits(wptr_gpu_addr));
1318 0 : wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1319 0 : wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1320 : SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1321 : F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1322 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1323 :
1324 : /* enable DMA RB */
1325 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1326 0 : WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1327 :
1328 0 : ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1329 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1330 : #ifdef __BIG_ENDIAN
1331 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1332 : #endif
1333 : /* enable DMA IBs */
1334 0 : WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1335 :
1336 0 : ring->sched.ready = true;
1337 0 : }
1338 :
1339 : static void
1340 0 : sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1341 : {
1342 : uint32_t def, data;
1343 :
1344 0 : if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1345 : /* enable idle interrupt */
1346 0 : def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1347 0 : data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1348 :
1349 0 : if (data != def)
1350 0 : WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1351 : } else {
1352 : /* disable idle interrupt */
1353 0 : def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1354 0 : data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1355 0 : if (data != def)
1356 0 : WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1357 : }
1358 0 : }
1359 :
1360 0 : static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1361 : {
1362 : uint32_t def, data;
1363 :
1364 : /* Enable HW based PG. */
1365 0 : def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1366 0 : data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1367 0 : if (data != def)
1368 0 : WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1369 :
1370 : /* enable interrupt */
1371 0 : def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1372 0 : data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1373 0 : if (data != def)
1374 0 : WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1375 :
1376 : /* Configure hold time to filter in-valid power on/off request. Use default right now */
1377 0 : def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1378 0 : data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1379 0 : data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1380 : /* Configure switch time for hysteresis purpose. Use default right now */
1381 0 : data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1382 0 : data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1383 0 : if(data != def)
1384 0 : WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1385 0 : }
1386 :
1387 0 : static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1388 : {
1389 0 : if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1390 : return;
1391 :
1392 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
1393 : case IP_VERSION(4, 1, 0):
1394 : case IP_VERSION(4, 1, 1):
1395 : case IP_VERSION(4, 1, 2):
1396 0 : sdma_v4_1_init_power_gating(adev);
1397 0 : sdma_v4_1_update_power_gating(adev, true);
1398 0 : break;
1399 : default:
1400 : break;
1401 : }
1402 : }
1403 :
1404 : /**
1405 : * sdma_v4_0_rlc_resume - setup and start the async dma engines
1406 : *
1407 : * @adev: amdgpu_device pointer
1408 : *
1409 : * Set up the compute DMA queues and enable them (VEGA10).
1410 : * Returns 0 for success, error for failure.
1411 : */
1412 : static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1413 : {
1414 0 : sdma_v4_0_init_pg(adev);
1415 :
1416 : return 0;
1417 : }
1418 :
1419 : /**
1420 : * sdma_v4_0_load_microcode - load the sDMA ME ucode
1421 : *
1422 : * @adev: amdgpu_device pointer
1423 : *
1424 : * Loads the sDMA0/1 ucode.
1425 : * Returns 0 for success, -EINVAL if the ucode is not available.
1426 : */
1427 0 : static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1428 : {
1429 : const struct sdma_firmware_header_v1_0 *hdr;
1430 : const __le32 *fw_data;
1431 : u32 fw_size;
1432 : int i, j;
1433 :
1434 : /* halt the MEs */
1435 0 : sdma_v4_0_enable(adev, false);
1436 :
1437 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1438 0 : if (!adev->sdma.instance[i].fw)
1439 : return -EINVAL;
1440 :
1441 0 : hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1442 0 : amdgpu_ucode_print_sdma_hdr(&hdr->header);
1443 0 : fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1444 :
1445 0 : fw_data = (const __le32 *)
1446 0 : (adev->sdma.instance[i].fw->data +
1447 0 : le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1448 :
1449 0 : WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1450 :
1451 0 : for (j = 0; j < fw_size; j++)
1452 0 : WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1453 : le32_to_cpup(fw_data++));
1454 :
1455 0 : WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1456 : adev->sdma.instance[i].fw_version);
1457 : }
1458 :
1459 : return 0;
1460 : }
1461 :
1462 : /**
1463 : * sdma_v4_0_start - setup and start the async dma engines
1464 : *
1465 : * @adev: amdgpu_device pointer
1466 : *
1467 : * Set up the DMA engines and enable them (VEGA10).
1468 : * Returns 0 for success, error for failure.
1469 : */
1470 0 : static int sdma_v4_0_start(struct amdgpu_device *adev)
1471 : {
1472 : struct amdgpu_ring *ring;
1473 0 : int i, r = 0;
1474 :
1475 0 : if (amdgpu_sriov_vf(adev)) {
1476 0 : sdma_v4_0_ctx_switch_enable(adev, false);
1477 0 : sdma_v4_0_enable(adev, false);
1478 : } else {
1479 :
1480 0 : if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1481 0 : r = sdma_v4_0_load_microcode(adev);
1482 0 : if (r)
1483 : return r;
1484 : }
1485 :
1486 : /* unhalt the MEs */
1487 0 : sdma_v4_0_enable(adev, true);
1488 : /* enable sdma ring preemption */
1489 0 : sdma_v4_0_ctx_switch_enable(adev, true);
1490 : }
1491 :
1492 : /* start the gfx rings and rlc compute queues */
1493 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1494 : uint32_t temp;
1495 :
1496 0 : WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1497 0 : sdma_v4_0_gfx_resume(adev, i);
1498 0 : if (adev->sdma.has_page_queue)
1499 0 : sdma_v4_0_page_resume(adev, i);
1500 :
1501 : /* set utc l1 enable flag always to 1 */
1502 0 : temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1503 0 : temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1504 0 : WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1505 :
1506 0 : if (!amdgpu_sriov_vf(adev)) {
1507 : /* unhalt engine */
1508 0 : temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1509 0 : temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1510 0 : WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1511 : }
1512 : }
1513 :
1514 0 : if (amdgpu_sriov_vf(adev)) {
1515 0 : sdma_v4_0_ctx_switch_enable(adev, true);
1516 0 : sdma_v4_0_enable(adev, true);
1517 : } else {
1518 0 : r = sdma_v4_0_rlc_resume(adev);
1519 : if (r)
1520 : return r;
1521 : }
1522 :
1523 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1524 0 : ring = &adev->sdma.instance[i].ring;
1525 :
1526 0 : r = amdgpu_ring_test_helper(ring);
1527 0 : if (r)
1528 : return r;
1529 :
1530 0 : if (adev->sdma.has_page_queue) {
1531 0 : struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1532 :
1533 0 : r = amdgpu_ring_test_helper(page);
1534 0 : if (r)
1535 : return r;
1536 :
1537 0 : if (adev->mman.buffer_funcs_ring == page)
1538 0 : amdgpu_ttm_set_buffer_funcs_status(adev, true);
1539 : }
1540 :
1541 0 : if (adev->mman.buffer_funcs_ring == ring)
1542 0 : amdgpu_ttm_set_buffer_funcs_status(adev, true);
1543 : }
1544 :
1545 : return r;
1546 : }
1547 :
1548 : /**
1549 : * sdma_v4_0_ring_test_ring - simple async dma engine test
1550 : *
1551 : * @ring: amdgpu_ring structure holding ring information
1552 : *
1553 : * Test the DMA engine by writing using it to write an
1554 : * value to memory. (VEGA10).
1555 : * Returns 0 for success, error for failure.
1556 : */
1557 0 : static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1558 : {
1559 0 : struct amdgpu_device *adev = ring->adev;
1560 : unsigned i;
1561 : unsigned index;
1562 : int r;
1563 : u32 tmp;
1564 : u64 gpu_addr;
1565 :
1566 0 : r = amdgpu_device_wb_get(adev, &index);
1567 0 : if (r)
1568 : return r;
1569 :
1570 0 : gpu_addr = adev->wb.gpu_addr + (index * 4);
1571 0 : tmp = 0xCAFEDEAD;
1572 0 : adev->wb.wb[index] = cpu_to_le32(tmp);
1573 :
1574 0 : r = amdgpu_ring_alloc(ring, 5);
1575 0 : if (r)
1576 : goto error_free_wb;
1577 :
1578 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1579 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1580 0 : amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1581 0 : amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1582 0 : amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1583 0 : amdgpu_ring_write(ring, 0xDEADBEEF);
1584 0 : amdgpu_ring_commit(ring);
1585 :
1586 0 : for (i = 0; i < adev->usec_timeout; i++) {
1587 0 : tmp = le32_to_cpu(adev->wb.wb[index]);
1588 0 : if (tmp == 0xDEADBEEF)
1589 : break;
1590 0 : udelay(1);
1591 : }
1592 :
1593 0 : if (i >= adev->usec_timeout)
1594 0 : r = -ETIMEDOUT;
1595 :
1596 : error_free_wb:
1597 0 : amdgpu_device_wb_free(adev, index);
1598 0 : return r;
1599 : }
1600 :
1601 : /**
1602 : * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1603 : *
1604 : * @ring: amdgpu_ring structure holding ring information
1605 : * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1606 : *
1607 : * Test a simple IB in the DMA ring (VEGA10).
1608 : * Returns 0 on success, error on failure.
1609 : */
1610 0 : static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1611 : {
1612 0 : struct amdgpu_device *adev = ring->adev;
1613 : struct amdgpu_ib ib;
1614 0 : struct dma_fence *f = NULL;
1615 : unsigned index;
1616 : long r;
1617 0 : u32 tmp = 0;
1618 : u64 gpu_addr;
1619 :
1620 0 : r = amdgpu_device_wb_get(adev, &index);
1621 0 : if (r)
1622 : return r;
1623 :
1624 0 : gpu_addr = adev->wb.gpu_addr + (index * 4);
1625 0 : tmp = 0xCAFEDEAD;
1626 0 : adev->wb.wb[index] = cpu_to_le32(tmp);
1627 0 : memset(&ib, 0, sizeof(ib));
1628 0 : r = amdgpu_ib_get(adev, NULL, 256,
1629 : AMDGPU_IB_POOL_DIRECT, &ib);
1630 0 : if (r)
1631 : goto err0;
1632 :
1633 0 : ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1634 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1635 0 : ib.ptr[1] = lower_32_bits(gpu_addr);
1636 0 : ib.ptr[2] = upper_32_bits(gpu_addr);
1637 0 : ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1638 0 : ib.ptr[4] = 0xDEADBEEF;
1639 0 : ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1640 0 : ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1641 0 : ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1642 0 : ib.length_dw = 8;
1643 :
1644 0 : r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1645 0 : if (r)
1646 : goto err1;
1647 :
1648 0 : r = dma_fence_wait_timeout(f, false, timeout);
1649 0 : if (r == 0) {
1650 : r = -ETIMEDOUT;
1651 : goto err1;
1652 0 : } else if (r < 0) {
1653 : goto err1;
1654 : }
1655 0 : tmp = le32_to_cpu(adev->wb.wb[index]);
1656 0 : if (tmp == 0xDEADBEEF)
1657 : r = 0;
1658 : else
1659 0 : r = -EINVAL;
1660 :
1661 : err1:
1662 0 : amdgpu_ib_free(adev, &ib, NULL);
1663 0 : dma_fence_put(f);
1664 : err0:
1665 0 : amdgpu_device_wb_free(adev, index);
1666 0 : return r;
1667 : }
1668 :
1669 :
1670 : /**
1671 : * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1672 : *
1673 : * @ib: indirect buffer to fill with commands
1674 : * @pe: addr of the page entry
1675 : * @src: src addr to copy from
1676 : * @count: number of page entries to update
1677 : *
1678 : * Update PTEs by copying them from the GART using sDMA (VEGA10).
1679 : */
1680 0 : static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1681 : uint64_t pe, uint64_t src,
1682 : unsigned count)
1683 : {
1684 0 : unsigned bytes = count * 8;
1685 :
1686 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1687 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1688 0 : ib->ptr[ib->length_dw++] = bytes - 1;
1689 0 : ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1690 0 : ib->ptr[ib->length_dw++] = lower_32_bits(src);
1691 0 : ib->ptr[ib->length_dw++] = upper_32_bits(src);
1692 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1693 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1694 :
1695 0 : }
1696 :
1697 : /**
1698 : * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1699 : *
1700 : * @ib: indirect buffer to fill with commands
1701 : * @pe: addr of the page entry
1702 : * @value: dst addr to write into pe
1703 : * @count: number of page entries to update
1704 : * @incr: increase next addr by incr bytes
1705 : *
1706 : * Update PTEs by writing them manually using sDMA (VEGA10).
1707 : */
1708 0 : static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1709 : uint64_t value, unsigned count,
1710 : uint32_t incr)
1711 : {
1712 0 : unsigned ndw = count * 2;
1713 :
1714 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1715 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1716 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1717 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1718 0 : ib->ptr[ib->length_dw++] = ndw - 1;
1719 0 : for (; ndw > 0; ndw -= 2) {
1720 0 : ib->ptr[ib->length_dw++] = lower_32_bits(value);
1721 0 : ib->ptr[ib->length_dw++] = upper_32_bits(value);
1722 0 : value += incr;
1723 : }
1724 0 : }
1725 :
1726 : /**
1727 : * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1728 : *
1729 : * @ib: indirect buffer to fill with commands
1730 : * @pe: addr of the page entry
1731 : * @addr: dst addr to write into pe
1732 : * @count: number of page entries to update
1733 : * @incr: increase next addr by incr bytes
1734 : * @flags: access flags
1735 : *
1736 : * Update the page tables using sDMA (VEGA10).
1737 : */
1738 0 : static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1739 : uint64_t pe,
1740 : uint64_t addr, unsigned count,
1741 : uint32_t incr, uint64_t flags)
1742 : {
1743 : /* for physically contiguous pages (vram) */
1744 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1745 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1746 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1747 0 : ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1748 0 : ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1749 0 : ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1750 0 : ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1751 0 : ib->ptr[ib->length_dw++] = incr; /* increment size */
1752 0 : ib->ptr[ib->length_dw++] = 0;
1753 0 : ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1754 0 : }
1755 :
1756 : /**
1757 : * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1758 : *
1759 : * @ring: amdgpu_ring structure holding ring information
1760 : * @ib: indirect buffer to fill with padding
1761 : */
1762 0 : static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1763 : {
1764 0 : struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1765 : u32 pad_count;
1766 : int i;
1767 :
1768 0 : pad_count = (-ib->length_dw) & 7;
1769 0 : for (i = 0; i < pad_count; i++)
1770 0 : if (sdma && sdma->burst_nop && (i == 0))
1771 0 : ib->ptr[ib->length_dw++] =
1772 0 : SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1773 0 : SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1774 : else
1775 0 : ib->ptr[ib->length_dw++] =
1776 : SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1777 0 : }
1778 :
1779 :
1780 : /**
1781 : * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1782 : *
1783 : * @ring: amdgpu_ring pointer
1784 : *
1785 : * Make sure all previous operations are completed (CIK).
1786 : */
1787 0 : static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1788 : {
1789 0 : uint32_t seq = ring->fence_drv.sync_seq;
1790 0 : uint64_t addr = ring->fence_drv.gpu_addr;
1791 :
1792 : /* wait for idle */
1793 0 : sdma_v4_0_wait_reg_mem(ring, 1, 0,
1794 : addr & 0xfffffffc,
1795 0 : upper_32_bits(addr) & 0xffffffff,
1796 : seq, 0xffffffff, 4);
1797 0 : }
1798 :
1799 :
1800 : /**
1801 : * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1802 : *
1803 : * @ring: amdgpu_ring pointer
1804 : * @vmid: vmid number to use
1805 : * @pd_addr: address
1806 : *
1807 : * Update the page table base and flush the VM TLB
1808 : * using sDMA (VEGA10).
1809 : */
1810 0 : static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1811 : unsigned vmid, uint64_t pd_addr)
1812 : {
1813 0 : amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1814 0 : }
1815 :
1816 0 : static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1817 : uint32_t reg, uint32_t val)
1818 : {
1819 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1820 : SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1821 0 : amdgpu_ring_write(ring, reg);
1822 0 : amdgpu_ring_write(ring, val);
1823 0 : }
1824 :
1825 0 : static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1826 : uint32_t val, uint32_t mask)
1827 : {
1828 0 : sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1829 0 : }
1830 :
1831 : static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1832 : {
1833 0 : uint fw_version = adev->sdma.instance[0].fw_version;
1834 :
1835 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
1836 : case IP_VERSION(4, 0, 0):
1837 0 : return fw_version >= 430;
1838 : case IP_VERSION(4, 0, 1):
1839 : /*return fw_version >= 31;*/
1840 : return false;
1841 : case IP_VERSION(4, 2, 0):
1842 0 : return fw_version >= 123;
1843 : default:
1844 : return false;
1845 : }
1846 : }
1847 :
1848 0 : static int sdma_v4_0_early_init(void *handle)
1849 : {
1850 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1851 : int r;
1852 :
1853 0 : r = sdma_v4_0_init_microcode(adev);
1854 0 : if (r) {
1855 0 : DRM_ERROR("Failed to load sdma firmware!\n");
1856 0 : return r;
1857 : }
1858 :
1859 : /* TODO: Page queue breaks driver reload under SRIOV */
1860 0 : if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
1861 0 : amdgpu_sriov_vf((adev)))
1862 0 : adev->sdma.has_page_queue = false;
1863 0 : else if (sdma_v4_0_fw_support_paging_queue(adev))
1864 0 : adev->sdma.has_page_queue = true;
1865 :
1866 0 : sdma_v4_0_set_ring_funcs(adev);
1867 0 : sdma_v4_0_set_buffer_funcs(adev);
1868 0 : sdma_v4_0_set_vm_pte_funcs(adev);
1869 0 : sdma_v4_0_set_irq_funcs(adev);
1870 0 : sdma_v4_0_set_ras_funcs(adev);
1871 :
1872 0 : return 0;
1873 : }
1874 :
1875 : static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1876 : void *err_data,
1877 : struct amdgpu_iv_entry *entry);
1878 :
1879 0 : static int sdma_v4_0_late_init(void *handle)
1880 : {
1881 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1882 :
1883 0 : sdma_v4_0_setup_ulv(adev);
1884 :
1885 0 : if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1886 0 : if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1887 0 : adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1888 0 : adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1889 : }
1890 :
1891 0 : return 0;
1892 : }
1893 :
1894 0 : static int sdma_v4_0_sw_init(void *handle)
1895 : {
1896 : struct amdgpu_ring *ring;
1897 : int r, i;
1898 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1899 :
1900 : /* SDMA trap event */
1901 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1902 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1903 : SDMA0_4_0__SRCID__SDMA_TRAP,
1904 : &adev->sdma.trap_irq);
1905 0 : if (r)
1906 : return r;
1907 : }
1908 :
1909 : /* SDMA SRAM ECC event */
1910 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1911 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1912 : SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1913 : &adev->sdma.ecc_irq);
1914 0 : if (r)
1915 : return r;
1916 : }
1917 :
1918 : /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1919 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1920 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1921 : SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1922 : &adev->sdma.vm_hole_irq);
1923 0 : if (r)
1924 : return r;
1925 :
1926 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1927 : SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1928 : &adev->sdma.doorbell_invalid_irq);
1929 0 : if (r)
1930 : return r;
1931 :
1932 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1933 : SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1934 : &adev->sdma.pool_timeout_irq);
1935 0 : if (r)
1936 : return r;
1937 :
1938 0 : r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1939 : SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1940 : &adev->sdma.srbm_write_irq);
1941 0 : if (r)
1942 : return r;
1943 : }
1944 :
1945 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1946 0 : ring = &adev->sdma.instance[i].ring;
1947 0 : ring->ring_obj = NULL;
1948 0 : ring->use_doorbell = true;
1949 :
1950 0 : DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1951 : ring->use_doorbell?"true":"false");
1952 :
1953 : /* doorbell size is 2 dwords, get DWORD offset */
1954 0 : ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1955 :
1956 0 : sprintf(ring->name, "sdma%d", i);
1957 0 : r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1958 : AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1959 : AMDGPU_RING_PRIO_DEFAULT, NULL);
1960 0 : if (r)
1961 : return r;
1962 :
1963 0 : if (adev->sdma.has_page_queue) {
1964 0 : ring = &adev->sdma.instance[i].page;
1965 0 : ring->ring_obj = NULL;
1966 0 : ring->use_doorbell = true;
1967 :
1968 : /* paging queue use same doorbell index/routing as gfx queue
1969 : * with 0x400 (4096 dwords) offset on second doorbell page
1970 : */
1971 0 : ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1972 0 : ring->doorbell_index += 0x400;
1973 :
1974 0 : sprintf(ring->name, "page%d", i);
1975 0 : r = amdgpu_ring_init(adev, ring, 1024,
1976 : &adev->sdma.trap_irq,
1977 : AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1978 : AMDGPU_RING_PRIO_DEFAULT, NULL);
1979 0 : if (r)
1980 : return r;
1981 : }
1982 : }
1983 :
1984 : return r;
1985 : }
1986 :
1987 0 : static int sdma_v4_0_sw_fini(void *handle)
1988 : {
1989 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1990 : int i;
1991 :
1992 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1993 0 : amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1994 0 : if (adev->sdma.has_page_queue)
1995 0 : amdgpu_ring_fini(&adev->sdma.instance[i].page);
1996 : }
1997 :
1998 0 : sdma_v4_0_destroy_inst_ctx(adev);
1999 :
2000 0 : return 0;
2001 : }
2002 :
2003 0 : static int sdma_v4_0_hw_init(void *handle)
2004 : {
2005 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2006 :
2007 0 : if (adev->flags & AMD_IS_APU)
2008 0 : amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
2009 :
2010 0 : if (!amdgpu_sriov_vf(adev))
2011 0 : sdma_v4_0_init_golden_registers(adev);
2012 :
2013 0 : return sdma_v4_0_start(adev);
2014 : }
2015 :
2016 0 : static int sdma_v4_0_hw_fini(void *handle)
2017 : {
2018 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2019 : int i;
2020 :
2021 0 : if (amdgpu_sriov_vf(adev))
2022 : return 0;
2023 :
2024 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2025 0 : amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2026 : AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2027 : }
2028 :
2029 0 : sdma_v4_0_ctx_switch_enable(adev, false);
2030 0 : sdma_v4_0_enable(adev, false);
2031 :
2032 0 : if (adev->flags & AMD_IS_APU)
2033 0 : amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
2034 :
2035 : return 0;
2036 : }
2037 :
2038 0 : static int sdma_v4_0_suspend(void *handle)
2039 : {
2040 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2041 :
2042 : /* SMU saves SDMA state for us */
2043 0 : if (adev->in_s0ix)
2044 : return 0;
2045 :
2046 0 : return sdma_v4_0_hw_fini(adev);
2047 : }
2048 :
2049 0 : static int sdma_v4_0_resume(void *handle)
2050 : {
2051 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2052 :
2053 : /* SMU restores SDMA state for us */
2054 0 : if (adev->in_s0ix)
2055 : return 0;
2056 :
2057 0 : return sdma_v4_0_hw_init(adev);
2058 : }
2059 :
2060 0 : static bool sdma_v4_0_is_idle(void *handle)
2061 : {
2062 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2063 : u32 i;
2064 :
2065 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2066 0 : u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2067 :
2068 0 : if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2069 : return false;
2070 : }
2071 :
2072 : return true;
2073 : }
2074 :
2075 0 : static int sdma_v4_0_wait_for_idle(void *handle)
2076 : {
2077 : unsigned i, j;
2078 : u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2079 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2080 :
2081 0 : for (i = 0; i < adev->usec_timeout; i++) {
2082 0 : for (j = 0; j < adev->sdma.num_instances; j++) {
2083 0 : sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2084 0 : if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2085 : break;
2086 : }
2087 0 : if (j == adev->sdma.num_instances)
2088 : return 0;
2089 0 : udelay(1);
2090 : }
2091 : return -ETIMEDOUT;
2092 : }
2093 :
2094 0 : static int sdma_v4_0_soft_reset(void *handle)
2095 : {
2096 : /* todo */
2097 :
2098 0 : return 0;
2099 : }
2100 :
2101 0 : static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2102 : struct amdgpu_irq_src *source,
2103 : unsigned type,
2104 : enum amdgpu_interrupt_state state)
2105 : {
2106 : u32 sdma_cntl;
2107 :
2108 0 : sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2109 0 : sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2110 : state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2111 0 : WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2112 :
2113 0 : return 0;
2114 : }
2115 :
2116 0 : static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2117 : struct amdgpu_irq_src *source,
2118 : struct amdgpu_iv_entry *entry)
2119 : {
2120 : uint32_t instance;
2121 :
2122 0 : DRM_DEBUG("IH: SDMA trap\n");
2123 0 : instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2124 0 : switch (entry->ring_id) {
2125 : case 0:
2126 0 : amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2127 0 : break;
2128 : case 1:
2129 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
2130 0 : amdgpu_fence_process(&adev->sdma.instance[instance].page);
2131 : break;
2132 : case 2:
2133 : /* XXX compute */
2134 : break;
2135 : case 3:
2136 0 : if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
2137 0 : amdgpu_fence_process(&adev->sdma.instance[instance].page);
2138 : break;
2139 : }
2140 0 : return 0;
2141 : }
2142 :
2143 0 : static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2144 : void *err_data,
2145 : struct amdgpu_iv_entry *entry)
2146 : {
2147 : int instance;
2148 :
2149 : /* When “Full RAS” is enabled, the per-IP interrupt sources should
2150 : * be disabled and the driver should only look for the aggregated
2151 : * interrupt via sync flood
2152 : */
2153 0 : if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2154 : goto out;
2155 :
2156 0 : instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2157 0 : if (instance < 0)
2158 : goto out;
2159 :
2160 0 : amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2161 :
2162 : out:
2163 0 : return AMDGPU_RAS_SUCCESS;
2164 : }
2165 :
2166 0 : static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2167 : struct amdgpu_irq_src *source,
2168 : struct amdgpu_iv_entry *entry)
2169 : {
2170 : int instance;
2171 :
2172 0 : DRM_ERROR("Illegal instruction in SDMA command stream\n");
2173 :
2174 0 : instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2175 0 : if (instance < 0)
2176 : return 0;
2177 :
2178 0 : switch (entry->ring_id) {
2179 : case 0:
2180 0 : drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2181 0 : break;
2182 : }
2183 : return 0;
2184 : }
2185 :
2186 0 : static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2187 : struct amdgpu_irq_src *source,
2188 : unsigned type,
2189 : enum amdgpu_interrupt_state state)
2190 : {
2191 : u32 sdma_edc_config;
2192 :
2193 0 : sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2194 0 : sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2195 : state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2196 0 : WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2197 :
2198 0 : return 0;
2199 : }
2200 :
2201 0 : static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2202 : struct amdgpu_iv_entry *entry)
2203 : {
2204 : int instance;
2205 : struct amdgpu_task_info task_info;
2206 : u64 addr;
2207 :
2208 0 : instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2209 0 : if (instance < 0 || instance >= adev->sdma.num_instances) {
2210 0 : dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2211 : return -EINVAL;
2212 : }
2213 :
2214 0 : addr = (u64)entry->src_data[0] << 12;
2215 0 : addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2216 :
2217 0 : memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2218 0 : amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2219 :
2220 : dev_dbg_ratelimited(adev->dev,
2221 : "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2222 : "pasid:%u, for process %s pid %d thread %s pid %d\n",
2223 : instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2224 : entry->pasid, task_info.process_name, task_info.tgid,
2225 : task_info.task_name, task_info.pid);
2226 : return 0;
2227 : }
2228 :
2229 0 : static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2230 : struct amdgpu_irq_src *source,
2231 : struct amdgpu_iv_entry *entry)
2232 : {
2233 : dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
2234 0 : sdma_v4_0_print_iv_entry(adev, entry);
2235 0 : return 0;
2236 : }
2237 :
2238 0 : static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2239 : struct amdgpu_irq_src *source,
2240 : struct amdgpu_iv_entry *entry)
2241 : {
2242 : dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2243 0 : sdma_v4_0_print_iv_entry(adev, entry);
2244 0 : return 0;
2245 : }
2246 :
2247 0 : static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2248 : struct amdgpu_irq_src *source,
2249 : struct amdgpu_iv_entry *entry)
2250 : {
2251 : dev_dbg_ratelimited(adev->dev,
2252 : "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2253 0 : sdma_v4_0_print_iv_entry(adev, entry);
2254 0 : return 0;
2255 : }
2256 :
2257 0 : static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2258 : struct amdgpu_irq_src *source,
2259 : struct amdgpu_iv_entry *entry)
2260 : {
2261 : dev_dbg_ratelimited(adev->dev,
2262 : "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2263 0 : sdma_v4_0_print_iv_entry(adev, entry);
2264 0 : return 0;
2265 : }
2266 :
2267 0 : static void sdma_v4_0_update_medium_grain_clock_gating(
2268 : struct amdgpu_device *adev,
2269 : bool enable)
2270 : {
2271 : uint32_t data, def;
2272 : int i;
2273 :
2274 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2275 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2276 0 : def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2277 0 : data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2278 : SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2279 : SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2280 : SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2281 : SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2282 : SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2283 : SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2284 : SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2285 0 : if (def != data)
2286 0 : WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2287 : }
2288 : } else {
2289 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2290 0 : def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2291 0 : data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2292 : SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2293 : SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2294 : SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2295 : SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2296 : SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2297 : SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2298 : SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2299 0 : if (def != data)
2300 0 : WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2301 : }
2302 : }
2303 0 : }
2304 :
2305 :
2306 0 : static void sdma_v4_0_update_medium_grain_light_sleep(
2307 : struct amdgpu_device *adev,
2308 : bool enable)
2309 : {
2310 : uint32_t data, def;
2311 : int i;
2312 :
2313 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2314 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2315 : /* 1-not override: enable sdma mem light sleep */
2316 0 : def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2317 0 : data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2318 0 : if (def != data)
2319 0 : WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2320 : }
2321 : } else {
2322 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2323 : /* 0-override:disable sdma mem light sleep */
2324 0 : def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2325 0 : data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2326 0 : if (def != data)
2327 0 : WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2328 : }
2329 : }
2330 0 : }
2331 :
2332 0 : static int sdma_v4_0_set_clockgating_state(void *handle,
2333 : enum amd_clockgating_state state)
2334 : {
2335 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2336 :
2337 0 : if (amdgpu_sriov_vf(adev))
2338 : return 0;
2339 :
2340 0 : sdma_v4_0_update_medium_grain_clock_gating(adev,
2341 : state == AMD_CG_STATE_GATE);
2342 0 : sdma_v4_0_update_medium_grain_light_sleep(adev,
2343 : state == AMD_CG_STATE_GATE);
2344 0 : return 0;
2345 : }
2346 :
2347 0 : static int sdma_v4_0_set_powergating_state(void *handle,
2348 : enum amd_powergating_state state)
2349 : {
2350 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2351 :
2352 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
2353 : case IP_VERSION(4, 1, 0):
2354 : case IP_VERSION(4, 1, 1):
2355 : case IP_VERSION(4, 1, 2):
2356 0 : sdma_v4_1_update_power_gating(adev,
2357 : state == AMD_PG_STATE_GATE);
2358 0 : break;
2359 : default:
2360 : break;
2361 : }
2362 :
2363 0 : return 0;
2364 : }
2365 :
2366 0 : static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags)
2367 : {
2368 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2369 : int data;
2370 :
2371 0 : if (amdgpu_sriov_vf(adev))
2372 0 : *flags = 0;
2373 :
2374 : /* AMD_CG_SUPPORT_SDMA_MGCG */
2375 0 : data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2376 0 : if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2377 0 : *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2378 :
2379 : /* AMD_CG_SUPPORT_SDMA_LS */
2380 0 : data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2381 0 : if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2382 0 : *flags |= AMD_CG_SUPPORT_SDMA_LS;
2383 0 : }
2384 :
2385 : const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2386 : .name = "sdma_v4_0",
2387 : .early_init = sdma_v4_0_early_init,
2388 : .late_init = sdma_v4_0_late_init,
2389 : .sw_init = sdma_v4_0_sw_init,
2390 : .sw_fini = sdma_v4_0_sw_fini,
2391 : .hw_init = sdma_v4_0_hw_init,
2392 : .hw_fini = sdma_v4_0_hw_fini,
2393 : .suspend = sdma_v4_0_suspend,
2394 : .resume = sdma_v4_0_resume,
2395 : .is_idle = sdma_v4_0_is_idle,
2396 : .wait_for_idle = sdma_v4_0_wait_for_idle,
2397 : .soft_reset = sdma_v4_0_soft_reset,
2398 : .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2399 : .set_powergating_state = sdma_v4_0_set_powergating_state,
2400 : .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2401 : };
2402 :
2403 : static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2404 : .type = AMDGPU_RING_TYPE_SDMA,
2405 : .align_mask = 0xf,
2406 : .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2407 : .support_64bit_ptrs = true,
2408 : .secure_submission_supported = true,
2409 : .vmhub = AMDGPU_MMHUB_0,
2410 : .get_rptr = sdma_v4_0_ring_get_rptr,
2411 : .get_wptr = sdma_v4_0_ring_get_wptr,
2412 : .set_wptr = sdma_v4_0_ring_set_wptr,
2413 : .emit_frame_size =
2414 : 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2415 : 3 + /* hdp invalidate */
2416 : 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2417 : /* sdma_v4_0_ring_emit_vm_flush */
2418 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2419 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2420 : 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2421 : .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2422 : .emit_ib = sdma_v4_0_ring_emit_ib,
2423 : .emit_fence = sdma_v4_0_ring_emit_fence,
2424 : .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2425 : .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2426 : .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2427 : .test_ring = sdma_v4_0_ring_test_ring,
2428 : .test_ib = sdma_v4_0_ring_test_ib,
2429 : .insert_nop = sdma_v4_0_ring_insert_nop,
2430 : .pad_ib = sdma_v4_0_ring_pad_ib,
2431 : .emit_wreg = sdma_v4_0_ring_emit_wreg,
2432 : .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2433 : .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2434 : };
2435 :
2436 : /*
2437 : * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2438 : * So create a individual constant ring_funcs for those instances.
2439 : */
2440 : static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2441 : .type = AMDGPU_RING_TYPE_SDMA,
2442 : .align_mask = 0xf,
2443 : .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2444 : .support_64bit_ptrs = true,
2445 : .secure_submission_supported = true,
2446 : .vmhub = AMDGPU_MMHUB_1,
2447 : .get_rptr = sdma_v4_0_ring_get_rptr,
2448 : .get_wptr = sdma_v4_0_ring_get_wptr,
2449 : .set_wptr = sdma_v4_0_ring_set_wptr,
2450 : .emit_frame_size =
2451 : 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2452 : 3 + /* hdp invalidate */
2453 : 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2454 : /* sdma_v4_0_ring_emit_vm_flush */
2455 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2456 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2457 : 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2458 : .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2459 : .emit_ib = sdma_v4_0_ring_emit_ib,
2460 : .emit_fence = sdma_v4_0_ring_emit_fence,
2461 : .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2462 : .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2463 : .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2464 : .test_ring = sdma_v4_0_ring_test_ring,
2465 : .test_ib = sdma_v4_0_ring_test_ib,
2466 : .insert_nop = sdma_v4_0_ring_insert_nop,
2467 : .pad_ib = sdma_v4_0_ring_pad_ib,
2468 : .emit_wreg = sdma_v4_0_ring_emit_wreg,
2469 : .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2470 : .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2471 : };
2472 :
2473 : static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2474 : .type = AMDGPU_RING_TYPE_SDMA,
2475 : .align_mask = 0xf,
2476 : .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2477 : .support_64bit_ptrs = true,
2478 : .secure_submission_supported = true,
2479 : .vmhub = AMDGPU_MMHUB_0,
2480 : .get_rptr = sdma_v4_0_ring_get_rptr,
2481 : .get_wptr = sdma_v4_0_page_ring_get_wptr,
2482 : .set_wptr = sdma_v4_0_page_ring_set_wptr,
2483 : .emit_frame_size =
2484 : 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2485 : 3 + /* hdp invalidate */
2486 : 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2487 : /* sdma_v4_0_ring_emit_vm_flush */
2488 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2489 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2490 : 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2491 : .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2492 : .emit_ib = sdma_v4_0_ring_emit_ib,
2493 : .emit_fence = sdma_v4_0_ring_emit_fence,
2494 : .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2495 : .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2496 : .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2497 : .test_ring = sdma_v4_0_ring_test_ring,
2498 : .test_ib = sdma_v4_0_ring_test_ib,
2499 : .insert_nop = sdma_v4_0_ring_insert_nop,
2500 : .pad_ib = sdma_v4_0_ring_pad_ib,
2501 : .emit_wreg = sdma_v4_0_ring_emit_wreg,
2502 : .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2503 : .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2504 : };
2505 :
2506 : static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2507 : .type = AMDGPU_RING_TYPE_SDMA,
2508 : .align_mask = 0xf,
2509 : .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2510 : .support_64bit_ptrs = true,
2511 : .secure_submission_supported = true,
2512 : .vmhub = AMDGPU_MMHUB_1,
2513 : .get_rptr = sdma_v4_0_ring_get_rptr,
2514 : .get_wptr = sdma_v4_0_page_ring_get_wptr,
2515 : .set_wptr = sdma_v4_0_page_ring_set_wptr,
2516 : .emit_frame_size =
2517 : 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2518 : 3 + /* hdp invalidate */
2519 : 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2520 : /* sdma_v4_0_ring_emit_vm_flush */
2521 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2522 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2523 : 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2524 : .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2525 : .emit_ib = sdma_v4_0_ring_emit_ib,
2526 : .emit_fence = sdma_v4_0_ring_emit_fence,
2527 : .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2528 : .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2529 : .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2530 : .test_ring = sdma_v4_0_ring_test_ring,
2531 : .test_ib = sdma_v4_0_ring_test_ib,
2532 : .insert_nop = sdma_v4_0_ring_insert_nop,
2533 : .pad_ib = sdma_v4_0_ring_pad_ib,
2534 : .emit_wreg = sdma_v4_0_ring_emit_wreg,
2535 : .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2536 : .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2537 : };
2538 :
2539 0 : static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2540 : {
2541 : int i;
2542 :
2543 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2544 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
2545 0 : adev->sdma.instance[i].ring.funcs =
2546 : &sdma_v4_0_ring_funcs_2nd_mmhub;
2547 : else
2548 0 : adev->sdma.instance[i].ring.funcs =
2549 : &sdma_v4_0_ring_funcs;
2550 0 : adev->sdma.instance[i].ring.me = i;
2551 0 : if (adev->sdma.has_page_queue) {
2552 0 : if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
2553 0 : adev->sdma.instance[i].page.funcs =
2554 : &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2555 : else
2556 0 : adev->sdma.instance[i].page.funcs =
2557 : &sdma_v4_0_page_ring_funcs;
2558 0 : adev->sdma.instance[i].page.me = i;
2559 : }
2560 : }
2561 0 : }
2562 :
2563 : static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2564 : .set = sdma_v4_0_set_trap_irq_state,
2565 : .process = sdma_v4_0_process_trap_irq,
2566 : };
2567 :
2568 : static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2569 : .process = sdma_v4_0_process_illegal_inst_irq,
2570 : };
2571 :
2572 : static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2573 : .set = sdma_v4_0_set_ecc_irq_state,
2574 : .process = amdgpu_sdma_process_ecc_irq,
2575 : };
2576 :
2577 : static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2578 : .process = sdma_v4_0_process_vm_hole_irq,
2579 : };
2580 :
2581 : static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2582 : .process = sdma_v4_0_process_doorbell_invalid_irq,
2583 : };
2584 :
2585 : static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2586 : .process = sdma_v4_0_process_pool_timeout_irq,
2587 : };
2588 :
2589 : static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2590 : .process = sdma_v4_0_process_srbm_write_irq,
2591 : };
2592 :
2593 : static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2594 : {
2595 0 : adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2596 0 : adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2597 : /*For Arcturus and Aldebaran, add another 4 irq handler*/
2598 0 : switch (adev->sdma.num_instances) {
2599 : case 5:
2600 : case 8:
2601 0 : adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2602 0 : adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2603 0 : adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2604 0 : adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2605 : break;
2606 : default:
2607 : break;
2608 : }
2609 0 : adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2610 0 : adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2611 0 : adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2612 0 : adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2613 0 : adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2614 0 : adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2615 0 : adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2616 : }
2617 :
2618 : /**
2619 : * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2620 : *
2621 : * @ib: indirect buffer to copy to
2622 : * @src_offset: src GPU address
2623 : * @dst_offset: dst GPU address
2624 : * @byte_count: number of bytes to xfer
2625 : * @tmz: if a secure copy should be used
2626 : *
2627 : * Copy GPU buffers using the DMA engine (VEGA10/12).
2628 : * Used by the amdgpu ttm implementation to move pages if
2629 : * registered as the asic copy callback.
2630 : */
2631 0 : static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2632 : uint64_t src_offset,
2633 : uint64_t dst_offset,
2634 : uint32_t byte_count,
2635 : bool tmz)
2636 : {
2637 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2638 0 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2639 : SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2640 0 : ib->ptr[ib->length_dw++] = byte_count - 1;
2641 0 : ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2642 0 : ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2643 0 : ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2644 0 : ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2645 0 : ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2646 0 : }
2647 :
2648 : /**
2649 : * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2650 : *
2651 : * @ib: indirect buffer to copy to
2652 : * @src_data: value to write to buffer
2653 : * @dst_offset: dst GPU address
2654 : * @byte_count: number of bytes to xfer
2655 : *
2656 : * Fill GPU buffers using the DMA engine (VEGA10/12).
2657 : */
2658 0 : static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2659 : uint32_t src_data,
2660 : uint64_t dst_offset,
2661 : uint32_t byte_count)
2662 : {
2663 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2664 0 : ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2665 0 : ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2666 0 : ib->ptr[ib->length_dw++] = src_data;
2667 0 : ib->ptr[ib->length_dw++] = byte_count - 1;
2668 0 : }
2669 :
2670 : static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2671 : .copy_max_bytes = 0x400000,
2672 : .copy_num_dw = 7,
2673 : .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2674 :
2675 : .fill_max_bytes = 0x400000,
2676 : .fill_num_dw = 5,
2677 : .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2678 : };
2679 :
2680 : static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2681 : {
2682 0 : adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2683 0 : if (adev->sdma.has_page_queue)
2684 0 : adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2685 : else
2686 0 : adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2687 : }
2688 :
2689 : static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2690 : .copy_pte_num_dw = 7,
2691 : .copy_pte = sdma_v4_0_vm_copy_pte,
2692 :
2693 : .write_pte = sdma_v4_0_vm_write_pte,
2694 : .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2695 : };
2696 :
2697 : static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2698 : {
2699 : struct drm_gpu_scheduler *sched;
2700 : unsigned i;
2701 :
2702 0 : adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2703 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2704 0 : if (adev->sdma.has_page_queue)
2705 0 : sched = &adev->sdma.instance[i].page.sched;
2706 : else
2707 0 : sched = &adev->sdma.instance[i].ring.sched;
2708 0 : adev->vm_manager.vm_pte_scheds[i] = sched;
2709 : }
2710 0 : adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2711 : }
2712 :
2713 0 : static void sdma_v4_0_get_ras_error_count(uint32_t value,
2714 : uint32_t instance,
2715 : uint32_t *sec_count)
2716 : {
2717 : uint32_t i;
2718 : uint32_t sec_cnt;
2719 :
2720 : /* double bits error (multiple bits) error detection is not supported */
2721 0 : for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2722 : /* the SDMA_EDC_COUNTER register in each sdma instance
2723 : * shares the same sed shift_mask
2724 : * */
2725 0 : sec_cnt = (value &
2726 0 : sdma_v4_0_ras_fields[i].sec_count_mask) >>
2727 0 : sdma_v4_0_ras_fields[i].sec_count_shift;
2728 0 : if (sec_cnt) {
2729 0 : DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2730 : sdma_v4_0_ras_fields[i].name,
2731 : instance, sec_cnt);
2732 0 : *sec_count += sec_cnt;
2733 : }
2734 : }
2735 0 : }
2736 :
2737 0 : static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev,
2738 : uint32_t instance, void *ras_error_status)
2739 : {
2740 0 : struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2741 0 : uint32_t sec_count = 0;
2742 0 : uint32_t reg_value = 0;
2743 :
2744 0 : reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2745 : /* double bit error is not supported */
2746 0 : if (reg_value)
2747 0 : sdma_v4_0_get_ras_error_count(reg_value,
2748 : instance, &sec_count);
2749 : /* err_data->ce_count should be initialized to 0
2750 : * before calling into this function */
2751 0 : err_data->ce_count += sec_count;
2752 : /* double bit error is not supported
2753 : * set ue count to 0 */
2754 0 : err_data->ue_count = 0;
2755 :
2756 0 : return 0;
2757 : };
2758 :
2759 0 : static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status)
2760 : {
2761 0 : int i = 0;
2762 :
2763 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
2764 0 : if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
2765 0 : dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
2766 0 : return;
2767 : }
2768 : }
2769 : }
2770 :
2771 0 : static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2772 : {
2773 : int i;
2774 :
2775 : /* read back edc counter registers to clear the counters */
2776 0 : if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2777 0 : for (i = 0; i < adev->sdma.num_instances; i++)
2778 0 : RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2779 : }
2780 0 : }
2781 :
2782 : const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = {
2783 : .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2784 : .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2785 : };
2786 :
2787 : static struct amdgpu_sdma_ras sdma_v4_0_ras = {
2788 : .ras_block = {
2789 : .hw_ops = &sdma_v4_0_ras_hw_ops,
2790 : .ras_cb = sdma_v4_0_process_ras_data_cb,
2791 : },
2792 : };
2793 :
2794 0 : static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2795 : {
2796 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
2797 : case IP_VERSION(4, 2, 0):
2798 : case IP_VERSION(4, 2, 2):
2799 0 : adev->sdma.ras = &sdma_v4_0_ras;
2800 0 : break;
2801 : case IP_VERSION(4, 4, 0):
2802 0 : adev->sdma.ras = &sdma_v4_4_ras;
2803 0 : break;
2804 : default:
2805 : break;
2806 : }
2807 :
2808 0 : if (adev->sdma.ras) {
2809 0 : amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block);
2810 :
2811 0 : strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma");
2812 0 : adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA;
2813 0 : adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
2814 0 : adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm;
2815 :
2816 : /* If don't define special ras_late_init function, use default ras_late_init */
2817 0 : if (!adev->sdma.ras->ras_block.ras_late_init)
2818 0 : adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init;
2819 :
2820 : /* If not defined special ras_cb function, use default ras_cb */
2821 0 : if (!adev->sdma.ras->ras_block.ras_cb)
2822 0 : adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb;
2823 : }
2824 0 : }
2825 :
2826 : const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2827 : .type = AMD_IP_BLOCK_TYPE_SDMA,
2828 : .major = 4,
2829 : .minor = 0,
2830 : .rev = 0,
2831 : .funcs = &sdma_v4_0_ip_funcs,
2832 : };
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