Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/delay.h>
25 : #include <linux/firmware.h>
26 : #include <linux/module.h>
27 : #include <linux/pci.h>
28 :
29 : #include "amdgpu.h"
30 : #include "amdgpu_ucode.h"
31 : #include "amdgpu_trace.h"
32 :
33 : #include "gc/gc_10_3_0_offset.h"
34 : #include "gc/gc_10_3_0_sh_mask.h"
35 : #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 : #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 : #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 : #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39 :
40 : #include "soc15_common.h"
41 : #include "soc15.h"
42 : #include "navi10_sdma_pkt_open.h"
43 : #include "nbio_v2_3.h"
44 : #include "sdma_common.h"
45 : #include "sdma_v5_2.h"
46 :
47 : MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 : MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 : MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 : MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51 :
52 : MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 : MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 : MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55 : MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56 :
57 : #define SDMA1_REG_OFFSET 0x600
58 : #define SDMA3_REG_OFFSET 0x400
59 : #define SDMA0_HYP_DEC_REG_START 0x5880
60 : #define SDMA0_HYP_DEC_REG_END 0x5893
61 : #define SDMA1_HYP_DEC_REG_OFFSET 0x20
62 :
63 : static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
64 : static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
65 : static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
66 : static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
67 :
68 : static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
69 : {
70 : u32 base;
71 :
72 : if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
73 : internal_offset <= SDMA0_HYP_DEC_REG_END) {
74 0 : base = adev->reg_offset[GC_HWIP][0][1];
75 0 : if (instance != 0)
76 0 : internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
77 : } else {
78 0 : if (instance < 2) {
79 0 : base = adev->reg_offset[GC_HWIP][0][0];
80 0 : if (instance == 1)
81 0 : internal_offset += SDMA1_REG_OFFSET;
82 : } else {
83 0 : base = adev->reg_offset[GC_HWIP][0][2];
84 0 : if (instance == 3)
85 0 : internal_offset += SDMA3_REG_OFFSET;
86 : }
87 : }
88 :
89 0 : return base + internal_offset;
90 : }
91 :
92 0 : static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
93 : {
94 0 : int err = 0;
95 : const struct sdma_firmware_header_v1_0 *hdr;
96 :
97 0 : err = amdgpu_ucode_validate(sdma_inst->fw);
98 0 : if (err)
99 : return err;
100 :
101 0 : hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
102 0 : sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
103 0 : sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
104 :
105 0 : if (sdma_inst->feature_version >= 20)
106 0 : sdma_inst->burst_nop = true;
107 :
108 : return 0;
109 : }
110 :
111 0 : static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
112 : {
113 0 : release_firmware(adev->sdma.instance[0].fw);
114 :
115 0 : memset((void *)adev->sdma.instance, 0,
116 : sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
117 0 : }
118 :
119 : /**
120 : * sdma_v5_2_init_microcode - load ucode images from disk
121 : *
122 : * @adev: amdgpu_device pointer
123 : *
124 : * Use the firmware interface to load the ucode images into
125 : * the driver (not loaded into hw).
126 : * Returns 0 on success, error on failure.
127 : */
128 :
129 : // emulation only, won't work on real chip
130 : // navi10 real chip need to use PSP to load firmware
131 0 : static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
132 : {
133 : const char *chip_name;
134 : char fw_name[40];
135 0 : int err = 0, i;
136 0 : struct amdgpu_firmware_info *info = NULL;
137 0 : const struct common_firmware_header *header = NULL;
138 :
139 0 : DRM_DEBUG("\n");
140 :
141 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
142 : case IP_VERSION(5, 2, 0):
143 : chip_name = "sienna_cichlid_sdma";
144 : break;
145 : case IP_VERSION(5, 2, 2):
146 0 : chip_name = "navy_flounder_sdma";
147 0 : break;
148 : case IP_VERSION(5, 2, 1):
149 0 : chip_name = "vangogh_sdma";
150 0 : break;
151 : case IP_VERSION(5, 2, 4):
152 0 : chip_name = "dimgrey_cavefish_sdma";
153 0 : break;
154 : case IP_VERSION(5, 2, 5):
155 0 : chip_name = "beige_goby_sdma";
156 0 : break;
157 : case IP_VERSION(5, 2, 3):
158 0 : chip_name = "yellow_carp_sdma";
159 0 : break;
160 : case IP_VERSION(5, 2, 6):
161 0 : chip_name = "sdma_5_2_6";
162 0 : break;
163 : case IP_VERSION(5, 2, 7):
164 0 : chip_name = "sdma_5_2_7";
165 0 : break;
166 : default:
167 0 : BUG();
168 : }
169 :
170 0 : snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
171 :
172 0 : err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
173 0 : if (err)
174 : goto out;
175 :
176 0 : err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
177 0 : if (err)
178 : goto out;
179 :
180 0 : for (i = 1; i < adev->sdma.num_instances; i++)
181 0 : memcpy((void *)&adev->sdma.instance[i],
182 : (void *)&adev->sdma.instance[0],
183 : sizeof(struct amdgpu_sdma_instance));
184 :
185 0 : if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
186 : return 0;
187 :
188 0 : DRM_DEBUG("psp_load == '%s'\n",
189 : adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
190 :
191 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
192 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
193 0 : info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
194 0 : info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
195 0 : info->fw = adev->sdma.instance[i].fw;
196 0 : header = (const struct common_firmware_header *)info->fw->data;
197 0 : adev->firmware.fw_size +=
198 0 : ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
199 : }
200 : }
201 :
202 : out:
203 0 : if (err) {
204 0 : DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
205 0 : sdma_v5_2_destroy_inst_ctx(adev);
206 : }
207 : return err;
208 : }
209 :
210 0 : static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
211 : {
212 : unsigned ret;
213 :
214 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
215 0 : amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
216 0 : amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
217 0 : amdgpu_ring_write(ring, 1);
218 0 : ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
219 0 : amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
220 :
221 0 : return ret;
222 : }
223 :
224 0 : static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
225 : unsigned offset)
226 : {
227 : unsigned cur;
228 :
229 0 : BUG_ON(offset > ring->buf_mask);
230 0 : BUG_ON(ring->ring[offset] != 0x55aa55aa);
231 :
232 0 : cur = (ring->wptr - 1) & ring->buf_mask;
233 0 : if (cur > offset)
234 0 : ring->ring[offset] = cur - offset;
235 : else
236 0 : ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
237 0 : }
238 :
239 : /**
240 : * sdma_v5_2_ring_get_rptr - get the current read pointer
241 : *
242 : * @ring: amdgpu ring pointer
243 : *
244 : * Get the current rptr from the hardware (NAVI10+).
245 : */
246 0 : static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
247 : {
248 : u64 *rptr;
249 :
250 : /* XXX check if swapping is necessary on BE */
251 0 : rptr = (u64 *)ring->rptr_cpu_addr;
252 :
253 0 : DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
254 0 : return ((*rptr) >> 2);
255 : }
256 :
257 : /**
258 : * sdma_v5_2_ring_get_wptr - get the current write pointer
259 : *
260 : * @ring: amdgpu ring pointer
261 : *
262 : * Get the current wptr from the hardware (NAVI10+).
263 : */
264 0 : static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
265 : {
266 0 : struct amdgpu_device *adev = ring->adev;
267 : u64 wptr;
268 :
269 0 : if (ring->use_doorbell) {
270 : /* XXX check if swapping is necessary on BE */
271 0 : wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
272 0 : DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
273 : } else {
274 0 : wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
275 0 : wptr = wptr << 32;
276 0 : wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
277 0 : DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
278 : }
279 :
280 0 : return wptr >> 2;
281 : }
282 :
283 : /**
284 : * sdma_v5_2_ring_set_wptr - commit the write pointer
285 : *
286 : * @ring: amdgpu ring pointer
287 : *
288 : * Write the wptr back to the hardware (NAVI10+).
289 : */
290 0 : static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
291 : {
292 0 : struct amdgpu_device *adev = ring->adev;
293 :
294 0 : DRM_DEBUG("Setting write pointer\n");
295 0 : if (ring->use_doorbell) {
296 0 : DRM_DEBUG("Using doorbell -- "
297 : "wptr_offs == 0x%08x "
298 : "lower_32_bits(ring->wptr << 2) == 0x%08x "
299 : "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
300 : ring->wptr_offs,
301 : lower_32_bits(ring->wptr << 2),
302 : upper_32_bits(ring->wptr << 2));
303 : /* XXX check if swapping is necessary on BE */
304 0 : atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
305 0 : ring->wptr << 2);
306 0 : DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
307 : ring->doorbell_index, ring->wptr << 2);
308 0 : WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
309 : } else {
310 0 : DRM_DEBUG("Not using doorbell -- "
311 : "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
312 : "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
313 : ring->me,
314 : lower_32_bits(ring->wptr << 2),
315 : ring->me,
316 : upper_32_bits(ring->wptr << 2));
317 0 : WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
318 : lower_32_bits(ring->wptr << 2));
319 0 : WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
320 : upper_32_bits(ring->wptr << 2));
321 : }
322 0 : }
323 :
324 0 : static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
325 : {
326 0 : struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
327 : int i;
328 :
329 0 : for (i = 0; i < count; i++)
330 0 : if (sdma && sdma->burst_nop && (i == 0))
331 0 : amdgpu_ring_write(ring, ring->funcs->nop |
332 0 : SDMA_PKT_NOP_HEADER_COUNT(count - 1));
333 : else
334 0 : amdgpu_ring_write(ring, ring->funcs->nop);
335 0 : }
336 :
337 : /**
338 : * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
339 : *
340 : * @ring: amdgpu ring pointer
341 : * @job: job to retrieve vmid from
342 : * @ib: IB object to schedule
343 : * @flags: unused
344 : *
345 : * Schedule an IB in the DMA ring.
346 : */
347 0 : static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
348 : struct amdgpu_job *job,
349 : struct amdgpu_ib *ib,
350 : uint32_t flags)
351 : {
352 0 : unsigned vmid = AMDGPU_JOB_GET_VMID(job);
353 0 : uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
354 :
355 : /* An IB packet must end on a 8 DW boundary--the next dword
356 : * must be on a 8-dword boundary. Our IB packet below is 6
357 : * dwords long, thus add x number of NOPs, such that, in
358 : * modular arithmetic,
359 : * wptr + 6 + x = 8k, k >= 0, which in C is,
360 : * (wptr + 6 + x) % 8 = 0.
361 : * The expression below, is a solution of x.
362 : */
363 0 : sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
364 :
365 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
366 0 : SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
367 : /* base must be 32 byte aligned */
368 0 : amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
369 0 : amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
370 0 : amdgpu_ring_write(ring, ib->length_dw);
371 0 : amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
372 0 : amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
373 0 : }
374 :
375 : /**
376 : * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
377 : *
378 : * @ring: amdgpu ring pointer
379 : *
380 : * flush the IB by graphics cache rinse.
381 : */
382 0 : static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
383 : {
384 0 : uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
385 : SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
386 : SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
387 : SDMA_GCR_GLI_INV(1);
388 :
389 : /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
390 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
391 0 : amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
392 0 : amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
393 : SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
394 0 : amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
395 : SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
396 0 : amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
397 : SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
398 0 : }
399 :
400 : /**
401 : * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
402 : *
403 : * @ring: amdgpu ring pointer
404 : *
405 : * Emit an hdp flush packet on the requested DMA ring.
406 : */
407 0 : static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
408 : {
409 0 : struct amdgpu_device *adev = ring->adev;
410 0 : u32 ref_and_mask = 0;
411 0 : const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
412 :
413 0 : ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
414 :
415 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
416 : SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
417 : SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
418 0 : amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
419 0 : amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
420 0 : amdgpu_ring_write(ring, ref_and_mask); /* reference */
421 0 : amdgpu_ring_write(ring, ref_and_mask); /* mask */
422 0 : amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
423 : SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
424 0 : }
425 :
426 : /**
427 : * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
428 : *
429 : * @ring: amdgpu ring pointer
430 : * @addr: address
431 : * @seq: sequence number
432 : * @flags: fence related flags
433 : *
434 : * Add a DMA fence packet to the ring to write
435 : * the fence seq number and DMA trap packet to generate
436 : * an interrupt if needed.
437 : */
438 0 : static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
439 : unsigned flags)
440 : {
441 0 : bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
442 : /* write the fence */
443 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
444 : SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
445 : /* zero in first two bits */
446 0 : BUG_ON(addr & 0x3);
447 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
448 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
449 0 : amdgpu_ring_write(ring, lower_32_bits(seq));
450 :
451 : /* optionally write high bits as well */
452 0 : if (write64bit) {
453 0 : addr += 4;
454 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
455 : SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
456 : /* zero in first two bits */
457 0 : BUG_ON(addr & 0x3);
458 0 : amdgpu_ring_write(ring, lower_32_bits(addr));
459 0 : amdgpu_ring_write(ring, upper_32_bits(addr));
460 0 : amdgpu_ring_write(ring, upper_32_bits(seq));
461 : }
462 :
463 0 : if ((flags & AMDGPU_FENCE_FLAG_INT)) {
464 0 : uint32_t ctx = ring->is_mes_queue ?
465 0 : (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
466 : /* generate an interrupt */
467 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
468 0 : amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
469 : }
470 0 : }
471 :
472 :
473 : /**
474 : * sdma_v5_2_gfx_stop - stop the gfx async dma engines
475 : *
476 : * @adev: amdgpu_device pointer
477 : *
478 : * Stop the gfx async dma ring buffers.
479 : */
480 0 : static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
481 : {
482 0 : struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
483 0 : struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
484 0 : struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
485 0 : struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
486 : u32 rb_cntl, ib_cntl;
487 : int i;
488 :
489 0 : if ((adev->mman.buffer_funcs_ring == sdma0) ||
490 0 : (adev->mman.buffer_funcs_ring == sdma1) ||
491 0 : (adev->mman.buffer_funcs_ring == sdma2) ||
492 : (adev->mman.buffer_funcs_ring == sdma3))
493 0 : amdgpu_ttm_set_buffer_funcs_status(adev, false);
494 :
495 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
496 0 : rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
497 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
498 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
499 0 : ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
500 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
501 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
502 : }
503 0 : }
504 :
505 : /**
506 : * sdma_v5_2_rlc_stop - stop the compute async dma engines
507 : *
508 : * @adev: amdgpu_device pointer
509 : *
510 : * Stop the compute async dma queues.
511 : */
512 : static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
513 : {
514 : /* XXX todo */
515 : }
516 :
517 : /**
518 : * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
519 : *
520 : * @adev: amdgpu_device pointer
521 : * @enable: enable/disable the DMA MEs context switch.
522 : *
523 : * Halt or unhalt the async dma engines context switch.
524 : */
525 0 : static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
526 : {
527 0 : u32 f32_cntl, phase_quantum = 0;
528 : int i;
529 :
530 0 : if (amdgpu_sdma_phase_quantum) {
531 : unsigned value = amdgpu_sdma_phase_quantum;
532 : unsigned unit = 0;
533 :
534 0 : while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
535 : SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
536 0 : value = (value + 1) >> 1;
537 0 : unit++;
538 : }
539 0 : if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
540 : SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
541 0 : value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
542 : SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
543 0 : unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
544 : SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
545 0 : WARN_ONCE(1,
546 : "clamping sdma_phase_quantum to %uK clock cycles\n",
547 : value << unit);
548 : }
549 0 : phase_quantum =
550 0 : value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
551 : unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
552 : }
553 :
554 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
555 0 : if (enable && amdgpu_sdma_phase_quantum) {
556 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
557 : phase_quantum);
558 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
559 : phase_quantum);
560 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
561 : phase_quantum);
562 : }
563 :
564 0 : if (!amdgpu_sriov_vf(adev)) {
565 0 : f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
566 0 : f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
567 : AUTO_CTXSW_ENABLE, enable ? 1 : 0);
568 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
569 : }
570 : }
571 :
572 0 : }
573 :
574 : /**
575 : * sdma_v5_2_enable - stop the async dma engines
576 : *
577 : * @adev: amdgpu_device pointer
578 : * @enable: enable/disable the DMA MEs.
579 : *
580 : * Halt or unhalt the async dma engines.
581 : */
582 0 : static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
583 : {
584 : u32 f32_cntl;
585 : int i;
586 :
587 0 : if (!enable) {
588 0 : sdma_v5_2_gfx_stop(adev);
589 0 : sdma_v5_2_rlc_stop(adev);
590 : }
591 :
592 0 : if (!amdgpu_sriov_vf(adev)) {
593 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
594 0 : f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
595 0 : f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
596 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
597 : }
598 : }
599 0 : }
600 :
601 : /**
602 : * sdma_v5_2_gfx_resume - setup and start the async dma engines
603 : *
604 : * @adev: amdgpu_device pointer
605 : *
606 : * Set up the gfx DMA ring buffers and enable them.
607 : * Returns 0 for success, error for failure.
608 : */
609 0 : static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
610 : {
611 : struct amdgpu_ring *ring;
612 : u32 rb_cntl, ib_cntl;
613 : u32 rb_bufsz;
614 : u32 doorbell;
615 : u32 doorbell_offset;
616 : u32 temp;
617 : u32 wptr_poll_cntl;
618 : u64 wptr_gpu_addr;
619 : int i, r;
620 :
621 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
622 0 : ring = &adev->sdma.instance[i].ring;
623 :
624 0 : if (!amdgpu_sriov_vf(adev))
625 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
626 :
627 : /* Set ring buffer size in dwords */
628 0 : rb_bufsz = order_base_2(ring->ring_size / 4);
629 0 : rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
630 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
631 : #ifdef __BIG_ENDIAN
632 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
633 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
634 : RPTR_WRITEBACK_SWAP_ENABLE, 1);
635 : #endif
636 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
637 :
638 : /* Initialize the ring buffer's read and write pointers */
639 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
640 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
641 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
642 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
643 :
644 : /* setup the wptr shadow polling */
645 0 : wptr_gpu_addr = ring->wptr_gpu_addr;
646 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
647 : lower_32_bits(wptr_gpu_addr));
648 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
649 : upper_32_bits(wptr_gpu_addr));
650 0 : wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
651 : mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
652 0 : wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
653 : SDMA0_GFX_RB_WPTR_POLL_CNTL,
654 : F32_POLL_ENABLE, 1);
655 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
656 : wptr_poll_cntl);
657 :
658 : /* set the wb address whether it's enabled or not */
659 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
660 : upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
661 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
662 : lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
663 :
664 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
665 :
666 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
667 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
668 :
669 0 : ring->wptr = 0;
670 :
671 : /* before programing wptr to a less value, need set minor_ptr_update first */
672 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
673 :
674 0 : if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
675 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
676 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
677 : }
678 :
679 0 : doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
680 0 : doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
681 :
682 0 : if (ring->use_doorbell) {
683 0 : doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
684 0 : doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
685 : OFFSET, ring->doorbell_index);
686 : } else {
687 0 : doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
688 : }
689 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
690 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
691 :
692 0 : adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
693 0 : ring->doorbell_index,
694 0 : adev->doorbell_index.sdma_doorbell_range);
695 :
696 0 : if (amdgpu_sriov_vf(adev))
697 0 : sdma_v5_2_ring_set_wptr(ring);
698 :
699 : /* set minor_ptr_update to 0 after wptr programed */
700 :
701 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
702 :
703 : /* SRIOV VF has no control of any of registers below */
704 0 : if (!amdgpu_sriov_vf(adev)) {
705 : /* set utc l1 enable flag always to 1 */
706 0 : temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
707 0 : temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
708 :
709 : /* enable MCBP */
710 0 : temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
711 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
712 :
713 : /* Set up RESP_MODE to non-copy addresses */
714 0 : temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
715 0 : temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
716 0 : temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
717 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
718 :
719 : /* program default cache read and write policy */
720 0 : temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
721 : /* clean read policy and write policy bits */
722 0 : temp &= 0xFF0FFF;
723 0 : temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
724 : (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
725 : SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
726 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
727 :
728 : /* unhalt engine */
729 0 : temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
730 0 : temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
731 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
732 : }
733 :
734 : /* enable DMA RB */
735 0 : rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
736 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
737 :
738 0 : ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
739 0 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
740 : #ifdef __BIG_ENDIAN
741 : ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
742 : #endif
743 : /* enable DMA IBs */
744 0 : WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
745 :
746 0 : ring->sched.ready = true;
747 :
748 0 : if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
749 0 : sdma_v5_2_ctx_switch_enable(adev, true);
750 0 : sdma_v5_2_enable(adev, true);
751 : }
752 :
753 0 : r = amdgpu_ring_test_ring(ring);
754 0 : if (r) {
755 0 : ring->sched.ready = false;
756 0 : return r;
757 : }
758 :
759 0 : if (adev->mman.buffer_funcs_ring == ring)
760 0 : amdgpu_ttm_set_buffer_funcs_status(adev, true);
761 : }
762 :
763 : return 0;
764 : }
765 :
766 : /**
767 : * sdma_v5_2_rlc_resume - setup and start the async dma engines
768 : *
769 : * @adev: amdgpu_device pointer
770 : *
771 : * Set up the compute DMA queues and enable them.
772 : * Returns 0 for success, error for failure.
773 : */
774 : static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
775 : {
776 : return 0;
777 : }
778 :
779 : /**
780 : * sdma_v5_2_load_microcode - load the sDMA ME ucode
781 : *
782 : * @adev: amdgpu_device pointer
783 : *
784 : * Loads the sDMA0/1/2/3 ucode.
785 : * Returns 0 for success, -EINVAL if the ucode is not available.
786 : */
787 0 : static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
788 : {
789 : const struct sdma_firmware_header_v1_0 *hdr;
790 : const __le32 *fw_data;
791 : u32 fw_size;
792 : int i, j;
793 :
794 : /* halt the MEs */
795 0 : sdma_v5_2_enable(adev, false);
796 :
797 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
798 0 : if (!adev->sdma.instance[i].fw)
799 : return -EINVAL;
800 :
801 0 : hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
802 0 : amdgpu_ucode_print_sdma_hdr(&hdr->header);
803 0 : fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
804 :
805 0 : fw_data = (const __le32 *)
806 0 : (adev->sdma.instance[i].fw->data +
807 0 : le32_to_cpu(hdr->header.ucode_array_offset_bytes));
808 :
809 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
810 :
811 0 : for (j = 0; j < fw_size; j++) {
812 0 : if (amdgpu_emu_mode == 1 && j % 500 == 0)
813 0 : msleep(1);
814 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
815 : }
816 :
817 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
818 : }
819 :
820 : return 0;
821 : }
822 :
823 0 : static int sdma_v5_2_soft_reset(void *handle)
824 : {
825 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
826 : u32 grbm_soft_reset;
827 : u32 tmp;
828 : int i;
829 :
830 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
831 0 : grbm_soft_reset = REG_SET_FIELD(0,
832 : GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
833 : 1);
834 0 : grbm_soft_reset <<= i;
835 :
836 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
837 0 : tmp |= grbm_soft_reset;
838 0 : DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
839 0 : WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
840 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
841 :
842 0 : udelay(50);
843 :
844 0 : tmp &= ~grbm_soft_reset;
845 0 : WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
846 0 : tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
847 :
848 0 : udelay(50);
849 : }
850 :
851 0 : return 0;
852 : }
853 :
854 : /**
855 : * sdma_v5_2_start - setup and start the async dma engines
856 : *
857 : * @adev: amdgpu_device pointer
858 : *
859 : * Set up the DMA engines and enable them.
860 : * Returns 0 for success, error for failure.
861 : */
862 0 : static int sdma_v5_2_start(struct amdgpu_device *adev)
863 : {
864 0 : int r = 0;
865 :
866 0 : if (amdgpu_sriov_vf(adev)) {
867 0 : sdma_v5_2_ctx_switch_enable(adev, false);
868 0 : sdma_v5_2_enable(adev, false);
869 :
870 : /* set RB registers */
871 0 : r = sdma_v5_2_gfx_resume(adev);
872 0 : return r;
873 : }
874 :
875 0 : if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
876 0 : r = sdma_v5_2_load_microcode(adev);
877 0 : if (r)
878 : return r;
879 :
880 : /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
881 0 : if (amdgpu_emu_mode == 1)
882 0 : msleep(1000);
883 : }
884 :
885 : /* TODO: check whether can submit a doorbell request to raise
886 : * a doorbell fence to exit gfxoff.
887 : */
888 0 : if (adev->in_s0ix)
889 0 : amdgpu_gfx_off_ctrl(adev, false);
890 :
891 0 : sdma_v5_2_soft_reset(adev);
892 : /* unhalt the MEs */
893 0 : sdma_v5_2_enable(adev, true);
894 : /* enable sdma ring preemption */
895 0 : sdma_v5_2_ctx_switch_enable(adev, true);
896 :
897 : /* start the gfx rings and rlc compute queues */
898 0 : r = sdma_v5_2_gfx_resume(adev);
899 0 : if (adev->in_s0ix)
900 0 : amdgpu_gfx_off_ctrl(adev, true);
901 0 : if (r)
902 : return r;
903 0 : r = sdma_v5_2_rlc_resume(adev);
904 :
905 0 : return r;
906 : }
907 :
908 0 : static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
909 : struct amdgpu_mqd_prop *prop)
910 : {
911 0 : struct v10_sdma_mqd *m = mqd;
912 : uint64_t wb_gpu_addr;
913 :
914 0 : m->sdmax_rlcx_rb_cntl =
915 0 : order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
916 : 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
917 0 : 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
918 : 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
919 :
920 0 : m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
921 0 : m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
922 :
923 0 : m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
924 : mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
925 :
926 0 : wb_gpu_addr = prop->wptr_gpu_addr;
927 0 : m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
928 0 : m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
929 :
930 0 : wb_gpu_addr = prop->rptr_gpu_addr;
931 0 : m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
932 0 : m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
933 :
934 0 : m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
935 : mmSDMA0_GFX_IB_CNTL));
936 :
937 0 : m->sdmax_rlcx_doorbell_offset =
938 0 : prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
939 :
940 0 : m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
941 :
942 0 : return 0;
943 : }
944 :
945 : static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
946 : {
947 0 : adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
948 0 : adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
949 : }
950 :
951 : /**
952 : * sdma_v5_2_ring_test_ring - simple async dma engine test
953 : *
954 : * @ring: amdgpu_ring structure holding ring information
955 : *
956 : * Test the DMA engine by writing using it to write an
957 : * value to memory.
958 : * Returns 0 for success, error for failure.
959 : */
960 0 : static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
961 : {
962 0 : struct amdgpu_device *adev = ring->adev;
963 : unsigned i;
964 : unsigned index;
965 : int r;
966 : u32 tmp;
967 : u64 gpu_addr;
968 0 : volatile uint32_t *cpu_ptr = NULL;
969 :
970 0 : tmp = 0xCAFEDEAD;
971 :
972 0 : if (ring->is_mes_queue) {
973 0 : uint32_t offset = 0;
974 0 : offset = amdgpu_mes_ctx_get_offs(ring,
975 : AMDGPU_MES_CTX_PADDING_OFFS);
976 0 : gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
977 0 : cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
978 0 : *cpu_ptr = tmp;
979 : } else {
980 0 : r = amdgpu_device_wb_get(adev, &index);
981 0 : if (r) {
982 0 : dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
983 0 : return r;
984 : }
985 :
986 0 : gpu_addr = adev->wb.gpu_addr + (index * 4);
987 0 : adev->wb.wb[index] = cpu_to_le32(tmp);
988 : }
989 :
990 0 : r = amdgpu_ring_alloc(ring, 20);
991 0 : if (r) {
992 0 : DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
993 0 : amdgpu_device_wb_free(adev, index);
994 0 : return r;
995 : }
996 :
997 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
998 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
999 0 : amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1000 0 : amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1001 0 : amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1002 0 : amdgpu_ring_write(ring, 0xDEADBEEF);
1003 0 : amdgpu_ring_commit(ring);
1004 :
1005 0 : for (i = 0; i < adev->usec_timeout; i++) {
1006 0 : if (ring->is_mes_queue)
1007 0 : tmp = le32_to_cpu(*cpu_ptr);
1008 : else
1009 0 : tmp = le32_to_cpu(adev->wb.wb[index]);
1010 0 : if (tmp == 0xDEADBEEF)
1011 : break;
1012 0 : if (amdgpu_emu_mode == 1)
1013 0 : msleep(1);
1014 : else
1015 : udelay(1);
1016 : }
1017 :
1018 0 : if (i >= adev->usec_timeout)
1019 0 : r = -ETIMEDOUT;
1020 :
1021 0 : if (!ring->is_mes_queue)
1022 0 : amdgpu_device_wb_free(adev, index);
1023 :
1024 : return r;
1025 : }
1026 :
1027 : /**
1028 : * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
1029 : *
1030 : * @ring: amdgpu_ring structure holding ring information
1031 : * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1032 : *
1033 : * Test a simple IB in the DMA ring.
1034 : * Returns 0 on success, error on failure.
1035 : */
1036 0 : static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1037 : {
1038 0 : struct amdgpu_device *adev = ring->adev;
1039 : struct amdgpu_ib ib;
1040 0 : struct dma_fence *f = NULL;
1041 : unsigned index;
1042 : long r;
1043 0 : u32 tmp = 0;
1044 : u64 gpu_addr;
1045 0 : volatile uint32_t *cpu_ptr = NULL;
1046 :
1047 0 : tmp = 0xCAFEDEAD;
1048 0 : memset(&ib, 0, sizeof(ib));
1049 :
1050 0 : if (ring->is_mes_queue) {
1051 0 : uint32_t offset = 0;
1052 0 : offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1053 0 : ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1054 0 : ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1055 :
1056 0 : offset = amdgpu_mes_ctx_get_offs(ring,
1057 : AMDGPU_MES_CTX_PADDING_OFFS);
1058 0 : gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1059 0 : cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1060 0 : *cpu_ptr = tmp;
1061 : } else {
1062 0 : r = amdgpu_device_wb_get(adev, &index);
1063 0 : if (r) {
1064 0 : dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1065 0 : return r;
1066 : }
1067 :
1068 0 : gpu_addr = adev->wb.gpu_addr + (index * 4);
1069 0 : adev->wb.wb[index] = cpu_to_le32(tmp);
1070 :
1071 0 : r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1072 0 : if (r) {
1073 0 : DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1074 0 : goto err0;
1075 : }
1076 : }
1077 :
1078 0 : ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1079 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1080 0 : ib.ptr[1] = lower_32_bits(gpu_addr);
1081 0 : ib.ptr[2] = upper_32_bits(gpu_addr);
1082 0 : ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1083 0 : ib.ptr[4] = 0xDEADBEEF;
1084 0 : ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1085 0 : ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1086 0 : ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1087 0 : ib.length_dw = 8;
1088 :
1089 0 : r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1090 0 : if (r)
1091 : goto err1;
1092 :
1093 0 : r = dma_fence_wait_timeout(f, false, timeout);
1094 0 : if (r == 0) {
1095 0 : DRM_ERROR("amdgpu: IB test timed out\n");
1096 0 : r = -ETIMEDOUT;
1097 0 : goto err1;
1098 0 : } else if (r < 0) {
1099 0 : DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1100 0 : goto err1;
1101 : }
1102 :
1103 0 : if (ring->is_mes_queue)
1104 0 : tmp = le32_to_cpu(*cpu_ptr);
1105 : else
1106 0 : tmp = le32_to_cpu(adev->wb.wb[index]);
1107 :
1108 0 : if (tmp == 0xDEADBEEF)
1109 : r = 0;
1110 : else
1111 0 : r = -EINVAL;
1112 :
1113 : err1:
1114 0 : amdgpu_ib_free(adev, &ib, NULL);
1115 0 : dma_fence_put(f);
1116 : err0:
1117 0 : if (!ring->is_mes_queue)
1118 0 : amdgpu_device_wb_free(adev, index);
1119 0 : return r;
1120 : }
1121 :
1122 :
1123 : /**
1124 : * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1125 : *
1126 : * @ib: indirect buffer to fill with commands
1127 : * @pe: addr of the page entry
1128 : * @src: src addr to copy from
1129 : * @count: number of page entries to update
1130 : *
1131 : * Update PTEs by copying them from the GART using sDMA.
1132 : */
1133 0 : static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1134 : uint64_t pe, uint64_t src,
1135 : unsigned count)
1136 : {
1137 0 : unsigned bytes = count * 8;
1138 :
1139 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1140 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1141 0 : ib->ptr[ib->length_dw++] = bytes - 1;
1142 0 : ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1143 0 : ib->ptr[ib->length_dw++] = lower_32_bits(src);
1144 0 : ib->ptr[ib->length_dw++] = upper_32_bits(src);
1145 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1146 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1147 :
1148 0 : }
1149 :
1150 : /**
1151 : * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1152 : *
1153 : * @ib: indirect buffer to fill with commands
1154 : * @pe: addr of the page entry
1155 : * @value: dst addr to write into pe
1156 : * @count: number of page entries to update
1157 : * @incr: increase next addr by incr bytes
1158 : *
1159 : * Update PTEs by writing them manually using sDMA.
1160 : */
1161 0 : static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1162 : uint64_t value, unsigned count,
1163 : uint32_t incr)
1164 : {
1165 0 : unsigned ndw = count * 2;
1166 :
1167 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1168 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1169 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1170 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1171 0 : ib->ptr[ib->length_dw++] = ndw - 1;
1172 0 : for (; ndw > 0; ndw -= 2) {
1173 0 : ib->ptr[ib->length_dw++] = lower_32_bits(value);
1174 0 : ib->ptr[ib->length_dw++] = upper_32_bits(value);
1175 0 : value += incr;
1176 : }
1177 0 : }
1178 :
1179 : /**
1180 : * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1181 : *
1182 : * @ib: indirect buffer to fill with commands
1183 : * @pe: addr of the page entry
1184 : * @addr: dst addr to write into pe
1185 : * @count: number of page entries to update
1186 : * @incr: increase next addr by incr bytes
1187 : * @flags: access flags
1188 : *
1189 : * Update the page tables using sDMA.
1190 : */
1191 0 : static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1192 : uint64_t pe,
1193 : uint64_t addr, unsigned count,
1194 : uint32_t incr, uint64_t flags)
1195 : {
1196 : /* for physically contiguous pages (vram) */
1197 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1198 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1199 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1200 0 : ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1201 0 : ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1202 0 : ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1203 0 : ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1204 0 : ib->ptr[ib->length_dw++] = incr; /* increment size */
1205 0 : ib->ptr[ib->length_dw++] = 0;
1206 0 : ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1207 0 : }
1208 :
1209 : /**
1210 : * sdma_v5_2_ring_pad_ib - pad the IB
1211 : *
1212 : * @ib: indirect buffer to fill with padding
1213 : * @ring: amdgpu_ring structure holding ring information
1214 : *
1215 : * Pad the IB with NOPs to a boundary multiple of 8.
1216 : */
1217 0 : static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1218 : {
1219 0 : struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1220 : u32 pad_count;
1221 : int i;
1222 :
1223 0 : pad_count = (-ib->length_dw) & 0x7;
1224 0 : for (i = 0; i < pad_count; i++)
1225 0 : if (sdma && sdma->burst_nop && (i == 0))
1226 0 : ib->ptr[ib->length_dw++] =
1227 0 : SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1228 0 : SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1229 : else
1230 0 : ib->ptr[ib->length_dw++] =
1231 : SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1232 0 : }
1233 :
1234 :
1235 : /**
1236 : * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1237 : *
1238 : * @ring: amdgpu_ring pointer
1239 : *
1240 : * Make sure all previous operations are completed (CIK).
1241 : */
1242 0 : static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1243 : {
1244 0 : uint32_t seq = ring->fence_drv.sync_seq;
1245 0 : uint64_t addr = ring->fence_drv.gpu_addr;
1246 :
1247 : /* wait for idle */
1248 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1249 : SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1250 : SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1251 : SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1252 0 : amdgpu_ring_write(ring, addr & 0xfffffffc);
1253 0 : amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1254 0 : amdgpu_ring_write(ring, seq); /* reference */
1255 0 : amdgpu_ring_write(ring, 0xffffffff); /* mask */
1256 0 : amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1257 : SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1258 0 : }
1259 :
1260 :
1261 : /**
1262 : * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1263 : *
1264 : * @ring: amdgpu_ring pointer
1265 : * @vmid: vmid number to use
1266 : * @pd_addr: address
1267 : *
1268 : * Update the page table base and flush the VM TLB
1269 : * using sDMA.
1270 : */
1271 0 : static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1272 : unsigned vmid, uint64_t pd_addr)
1273 : {
1274 0 : amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1275 0 : }
1276 :
1277 0 : static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1278 : uint32_t reg, uint32_t val)
1279 : {
1280 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1281 : SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1282 0 : amdgpu_ring_write(ring, reg);
1283 0 : amdgpu_ring_write(ring, val);
1284 0 : }
1285 :
1286 0 : static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1287 : uint32_t val, uint32_t mask)
1288 : {
1289 0 : amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1290 : SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1291 : SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1292 0 : amdgpu_ring_write(ring, reg << 2);
1293 0 : amdgpu_ring_write(ring, 0);
1294 0 : amdgpu_ring_write(ring, val); /* reference */
1295 0 : amdgpu_ring_write(ring, mask); /* mask */
1296 0 : amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1297 : SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1298 0 : }
1299 :
1300 0 : static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1301 : uint32_t reg0, uint32_t reg1,
1302 : uint32_t ref, uint32_t mask)
1303 : {
1304 0 : amdgpu_ring_emit_wreg(ring, reg0, ref);
1305 : /* wait for a cycle to reset vm_inv_eng*_ack */
1306 0 : amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1307 0 : amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1308 0 : }
1309 :
1310 0 : static int sdma_v5_2_early_init(void *handle)
1311 : {
1312 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313 :
1314 0 : sdma_v5_2_set_ring_funcs(adev);
1315 0 : sdma_v5_2_set_buffer_funcs(adev);
1316 0 : sdma_v5_2_set_vm_pte_funcs(adev);
1317 0 : sdma_v5_2_set_irq_funcs(adev);
1318 0 : sdma_v5_2_set_mqd_funcs(adev);
1319 :
1320 0 : return 0;
1321 : }
1322 :
1323 : static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1324 : {
1325 : switch (seq_num) {
1326 : case 0:
1327 : return SOC15_IH_CLIENTID_SDMA0;
1328 : case 1:
1329 : return SOC15_IH_CLIENTID_SDMA1;
1330 : case 2:
1331 : return SOC15_IH_CLIENTID_SDMA2;
1332 : case 3:
1333 : return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1334 : default:
1335 : break;
1336 : }
1337 : return -EINVAL;
1338 : }
1339 :
1340 : static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1341 : {
1342 0 : switch (seq_num) {
1343 : case 0:
1344 : return SDMA0_5_0__SRCID__SDMA_TRAP;
1345 : case 1:
1346 : return SDMA1_5_0__SRCID__SDMA_TRAP;
1347 : case 2:
1348 : return SDMA2_5_0__SRCID__SDMA_TRAP;
1349 : case 3:
1350 : return SDMA3_5_0__SRCID__SDMA_TRAP;
1351 : default:
1352 : break;
1353 : }
1354 : return -EINVAL;
1355 : }
1356 :
1357 0 : static int sdma_v5_2_sw_init(void *handle)
1358 : {
1359 : struct amdgpu_ring *ring;
1360 : int r, i;
1361 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 :
1363 : /* SDMA trap event */
1364 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1365 0 : r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1366 : sdma_v5_2_seq_to_trap_id(i),
1367 : &adev->sdma.trap_irq);
1368 0 : if (r)
1369 : return r;
1370 : }
1371 :
1372 0 : r = sdma_v5_2_init_microcode(adev);
1373 0 : if (r) {
1374 0 : DRM_ERROR("Failed to load sdma firmware!\n");
1375 0 : return r;
1376 : }
1377 :
1378 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1379 0 : ring = &adev->sdma.instance[i].ring;
1380 0 : ring->ring_obj = NULL;
1381 0 : ring->use_doorbell = true;
1382 0 : ring->me = i;
1383 :
1384 0 : DRM_INFO("use_doorbell being set to: [%s]\n",
1385 : ring->use_doorbell?"true":"false");
1386 :
1387 0 : ring->doorbell_index =
1388 0 : (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1389 :
1390 0 : sprintf(ring->name, "sdma%d", i);
1391 0 : r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1392 : AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1393 : AMDGPU_RING_PRIO_DEFAULT, NULL);
1394 0 : if (r)
1395 : return r;
1396 : }
1397 :
1398 : return r;
1399 : }
1400 :
1401 0 : static int sdma_v5_2_sw_fini(void *handle)
1402 : {
1403 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1404 : int i;
1405 :
1406 0 : for (i = 0; i < adev->sdma.num_instances; i++)
1407 0 : amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1408 :
1409 0 : sdma_v5_2_destroy_inst_ctx(adev);
1410 :
1411 0 : return 0;
1412 : }
1413 :
1414 0 : static int sdma_v5_2_hw_init(void *handle)
1415 : {
1416 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1417 :
1418 0 : return sdma_v5_2_start(adev);
1419 : }
1420 :
1421 0 : static int sdma_v5_2_hw_fini(void *handle)
1422 : {
1423 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1424 :
1425 0 : if (amdgpu_sriov_vf(adev))
1426 : return 0;
1427 :
1428 0 : sdma_v5_2_ctx_switch_enable(adev, false);
1429 0 : sdma_v5_2_enable(adev, false);
1430 :
1431 0 : return 0;
1432 : }
1433 :
1434 0 : static int sdma_v5_2_suspend(void *handle)
1435 : {
1436 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437 :
1438 0 : return sdma_v5_2_hw_fini(adev);
1439 : }
1440 :
1441 0 : static int sdma_v5_2_resume(void *handle)
1442 : {
1443 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444 :
1445 0 : return sdma_v5_2_hw_init(adev);
1446 : }
1447 :
1448 0 : static bool sdma_v5_2_is_idle(void *handle)
1449 : {
1450 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451 : u32 i;
1452 :
1453 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1454 0 : u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1455 :
1456 0 : if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1457 : return false;
1458 : }
1459 :
1460 : return true;
1461 : }
1462 :
1463 0 : static int sdma_v5_2_wait_for_idle(void *handle)
1464 : {
1465 : unsigned i;
1466 : u32 sdma0, sdma1, sdma2, sdma3;
1467 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468 :
1469 0 : for (i = 0; i < adev->usec_timeout; i++) {
1470 0 : sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1471 0 : sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1472 0 : sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1473 0 : sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1474 :
1475 0 : if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1476 : return 0;
1477 0 : udelay(1);
1478 : }
1479 : return -ETIMEDOUT;
1480 : }
1481 :
1482 0 : static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1483 : {
1484 0 : int i, r = 0;
1485 0 : struct amdgpu_device *adev = ring->adev;
1486 0 : u32 index = 0;
1487 : u64 sdma_gfx_preempt;
1488 :
1489 0 : amdgpu_sdma_get_index_from_ring(ring, &index);
1490 0 : sdma_gfx_preempt =
1491 0 : sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1492 :
1493 : /* assert preemption condition */
1494 0 : amdgpu_ring_set_preempt_cond_exec(ring, false);
1495 :
1496 : /* emit the trailing fence */
1497 0 : ring->trail_seq += 1;
1498 0 : amdgpu_ring_alloc(ring, 10);
1499 0 : sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1500 0 : ring->trail_seq, 0);
1501 0 : amdgpu_ring_commit(ring);
1502 :
1503 : /* assert IB preemption */
1504 0 : WREG32(sdma_gfx_preempt, 1);
1505 :
1506 : /* poll the trailing fence */
1507 0 : for (i = 0; i < adev->usec_timeout; i++) {
1508 0 : if (ring->trail_seq ==
1509 0 : le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1510 : break;
1511 0 : udelay(1);
1512 : }
1513 :
1514 0 : if (i >= adev->usec_timeout) {
1515 0 : r = -EINVAL;
1516 0 : DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1517 : }
1518 :
1519 : /* deassert IB preemption */
1520 0 : WREG32(sdma_gfx_preempt, 0);
1521 :
1522 : /* deassert the preemption condition */
1523 0 : amdgpu_ring_set_preempt_cond_exec(ring, true);
1524 0 : return r;
1525 : }
1526 :
1527 0 : static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1528 : struct amdgpu_irq_src *source,
1529 : unsigned type,
1530 : enum amdgpu_interrupt_state state)
1531 : {
1532 : u32 sdma_cntl;
1533 0 : u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1534 :
1535 0 : if (!amdgpu_sriov_vf(adev)) {
1536 0 : sdma_cntl = RREG32(reg_offset);
1537 0 : sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1538 : state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1539 0 : WREG32(reg_offset, sdma_cntl);
1540 : }
1541 :
1542 0 : return 0;
1543 : }
1544 :
1545 0 : static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1546 : struct amdgpu_irq_src *source,
1547 : struct amdgpu_iv_entry *entry)
1548 : {
1549 0 : uint32_t mes_queue_id = entry->src_data[0];
1550 :
1551 0 : DRM_DEBUG("IH: SDMA trap\n");
1552 :
1553 0 : if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1554 : struct amdgpu_mes_queue *queue;
1555 :
1556 0 : mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1557 :
1558 0 : spin_lock(&adev->mes.queue_id_lock);
1559 0 : queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1560 0 : if (queue) {
1561 0 : DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1562 0 : amdgpu_fence_process(queue->ring);
1563 : }
1564 0 : spin_unlock(&adev->mes.queue_id_lock);
1565 0 : return 0;
1566 : }
1567 :
1568 0 : switch (entry->client_id) {
1569 : case SOC15_IH_CLIENTID_SDMA0:
1570 0 : switch (entry->ring_id) {
1571 : case 0:
1572 0 : amdgpu_fence_process(&adev->sdma.instance[0].ring);
1573 0 : break;
1574 : case 1:
1575 : /* XXX compute */
1576 : break;
1577 : case 2:
1578 : /* XXX compute */
1579 : break;
1580 : case 3:
1581 : /* XXX page queue*/
1582 : break;
1583 : }
1584 : break;
1585 : case SOC15_IH_CLIENTID_SDMA1:
1586 0 : switch (entry->ring_id) {
1587 : case 0:
1588 0 : amdgpu_fence_process(&adev->sdma.instance[1].ring);
1589 0 : break;
1590 : case 1:
1591 : /* XXX compute */
1592 : break;
1593 : case 2:
1594 : /* XXX compute */
1595 : break;
1596 : case 3:
1597 : /* XXX page queue*/
1598 : break;
1599 : }
1600 : break;
1601 : case SOC15_IH_CLIENTID_SDMA2:
1602 0 : switch (entry->ring_id) {
1603 : case 0:
1604 0 : amdgpu_fence_process(&adev->sdma.instance[2].ring);
1605 0 : break;
1606 : case 1:
1607 : /* XXX compute */
1608 : break;
1609 : case 2:
1610 : /* XXX compute */
1611 : break;
1612 : case 3:
1613 : /* XXX page queue*/
1614 : break;
1615 : }
1616 : break;
1617 : case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1618 0 : switch (entry->ring_id) {
1619 : case 0:
1620 0 : amdgpu_fence_process(&adev->sdma.instance[3].ring);
1621 0 : break;
1622 : case 1:
1623 : /* XXX compute */
1624 : break;
1625 : case 2:
1626 : /* XXX compute */
1627 : break;
1628 : case 3:
1629 : /* XXX page queue*/
1630 : break;
1631 : }
1632 : break;
1633 : }
1634 : return 0;
1635 : }
1636 :
1637 0 : static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1638 : struct amdgpu_irq_src *source,
1639 : struct amdgpu_iv_entry *entry)
1640 : {
1641 0 : return 0;
1642 : }
1643 :
1644 0 : static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1645 : bool enable)
1646 : {
1647 : uint32_t data, def;
1648 : int i;
1649 :
1650 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1651 :
1652 0 : if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1653 0 : adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1654 :
1655 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1656 : /* Enable sdma clock gating */
1657 0 : def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1658 0 : data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1659 : SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1660 : SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1661 : SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1662 : SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1663 : SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1664 0 : if (def != data)
1665 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1666 : } else {
1667 : /* Disable sdma clock gating */
1668 0 : def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1669 0 : data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1670 : SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1671 : SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1672 : SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1673 : SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1674 : SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1675 0 : if (def != data)
1676 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1677 : }
1678 : }
1679 0 : }
1680 :
1681 0 : static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1682 : bool enable)
1683 : {
1684 : uint32_t data, def;
1685 : int i;
1686 :
1687 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1688 :
1689 0 : if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1690 0 : adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1691 :
1692 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1693 : /* Enable sdma mem light sleep */
1694 0 : def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1695 0 : data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1696 0 : if (def != data)
1697 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1698 :
1699 : } else {
1700 : /* Disable sdma mem light sleep */
1701 0 : def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1702 0 : data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1703 0 : if (def != data)
1704 0 : WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1705 :
1706 : }
1707 : }
1708 0 : }
1709 :
1710 0 : static int sdma_v5_2_set_clockgating_state(void *handle,
1711 : enum amd_clockgating_state state)
1712 : {
1713 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1714 :
1715 0 : if (amdgpu_sriov_vf(adev))
1716 : return 0;
1717 :
1718 0 : switch (adev->ip_versions[SDMA0_HWIP][0]) {
1719 : case IP_VERSION(5, 2, 0):
1720 : case IP_VERSION(5, 2, 2):
1721 : case IP_VERSION(5, 2, 1):
1722 : case IP_VERSION(5, 2, 4):
1723 : case IP_VERSION(5, 2, 5):
1724 : case IP_VERSION(5, 2, 6):
1725 : case IP_VERSION(5, 2, 3):
1726 0 : sdma_v5_2_update_medium_grain_clock_gating(adev,
1727 : state == AMD_CG_STATE_GATE);
1728 0 : sdma_v5_2_update_medium_grain_light_sleep(adev,
1729 : state == AMD_CG_STATE_GATE);
1730 0 : break;
1731 : default:
1732 : break;
1733 : }
1734 :
1735 : return 0;
1736 : }
1737 :
1738 0 : static int sdma_v5_2_set_powergating_state(void *handle,
1739 : enum amd_powergating_state state)
1740 : {
1741 0 : return 0;
1742 : }
1743 :
1744 0 : static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1745 : {
1746 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1747 : int data;
1748 :
1749 0 : if (amdgpu_sriov_vf(adev))
1750 0 : *flags = 0;
1751 :
1752 : /* AMD_CG_SUPPORT_SDMA_MGCG */
1753 0 : data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1754 0 : if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1755 0 : *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1756 :
1757 : /* AMD_CG_SUPPORT_SDMA_LS */
1758 0 : data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1759 0 : if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1760 0 : *flags |= AMD_CG_SUPPORT_SDMA_LS;
1761 0 : }
1762 :
1763 : const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1764 : .name = "sdma_v5_2",
1765 : .early_init = sdma_v5_2_early_init,
1766 : .late_init = NULL,
1767 : .sw_init = sdma_v5_2_sw_init,
1768 : .sw_fini = sdma_v5_2_sw_fini,
1769 : .hw_init = sdma_v5_2_hw_init,
1770 : .hw_fini = sdma_v5_2_hw_fini,
1771 : .suspend = sdma_v5_2_suspend,
1772 : .resume = sdma_v5_2_resume,
1773 : .is_idle = sdma_v5_2_is_idle,
1774 : .wait_for_idle = sdma_v5_2_wait_for_idle,
1775 : .soft_reset = sdma_v5_2_soft_reset,
1776 : .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1777 : .set_powergating_state = sdma_v5_2_set_powergating_state,
1778 : .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1779 : };
1780 :
1781 : static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1782 : .type = AMDGPU_RING_TYPE_SDMA,
1783 : .align_mask = 0xf,
1784 : .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1785 : .support_64bit_ptrs = true,
1786 : .secure_submission_supported = true,
1787 : .vmhub = AMDGPU_GFXHUB_0,
1788 : .get_rptr = sdma_v5_2_ring_get_rptr,
1789 : .get_wptr = sdma_v5_2_ring_get_wptr,
1790 : .set_wptr = sdma_v5_2_ring_set_wptr,
1791 : .emit_frame_size =
1792 : 5 + /* sdma_v5_2_ring_init_cond_exec */
1793 : 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1794 : 3 + /* hdp_invalidate */
1795 : 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1796 : /* sdma_v5_2_ring_emit_vm_flush */
1797 : SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1798 : SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1799 : 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1800 : .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1801 : .emit_ib = sdma_v5_2_ring_emit_ib,
1802 : .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1803 : .emit_fence = sdma_v5_2_ring_emit_fence,
1804 : .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1805 : .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1806 : .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1807 : .test_ring = sdma_v5_2_ring_test_ring,
1808 : .test_ib = sdma_v5_2_ring_test_ib,
1809 : .insert_nop = sdma_v5_2_ring_insert_nop,
1810 : .pad_ib = sdma_v5_2_ring_pad_ib,
1811 : .emit_wreg = sdma_v5_2_ring_emit_wreg,
1812 : .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1813 : .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1814 : .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1815 : .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1816 : .preempt_ib = sdma_v5_2_ring_preempt_ib,
1817 : };
1818 :
1819 : static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1820 : {
1821 : int i;
1822 :
1823 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1824 0 : adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1825 0 : adev->sdma.instance[i].ring.me = i;
1826 : }
1827 : }
1828 :
1829 : static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1830 : .set = sdma_v5_2_set_trap_irq_state,
1831 : .process = sdma_v5_2_process_trap_irq,
1832 : };
1833 :
1834 : static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1835 : .process = sdma_v5_2_process_illegal_inst_irq,
1836 : };
1837 :
1838 : static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1839 : {
1840 0 : adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1841 : adev->sdma.num_instances;
1842 0 : adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1843 0 : adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1844 : }
1845 :
1846 : /**
1847 : * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1848 : *
1849 : * @ib: indirect buffer to copy to
1850 : * @src_offset: src GPU address
1851 : * @dst_offset: dst GPU address
1852 : * @byte_count: number of bytes to xfer
1853 : * @tmz: if a secure copy should be used
1854 : *
1855 : * Copy GPU buffers using the DMA engine.
1856 : * Used by the amdgpu ttm implementation to move pages if
1857 : * registered as the asic copy callback.
1858 : */
1859 0 : static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1860 : uint64_t src_offset,
1861 : uint64_t dst_offset,
1862 : uint32_t byte_count,
1863 : bool tmz)
1864 : {
1865 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1866 0 : SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1867 : SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1868 0 : ib->ptr[ib->length_dw++] = byte_count - 1;
1869 0 : ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1870 0 : ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1871 0 : ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1872 0 : ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1873 0 : ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1874 0 : }
1875 :
1876 : /**
1877 : * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1878 : *
1879 : * @ib: indirect buffer to fill
1880 : * @src_data: value to write to buffer
1881 : * @dst_offset: dst GPU address
1882 : * @byte_count: number of bytes to xfer
1883 : *
1884 : * Fill GPU buffers using the DMA engine.
1885 : */
1886 0 : static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1887 : uint32_t src_data,
1888 : uint64_t dst_offset,
1889 : uint32_t byte_count)
1890 : {
1891 0 : ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1892 0 : ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1893 0 : ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1894 0 : ib->ptr[ib->length_dw++] = src_data;
1895 0 : ib->ptr[ib->length_dw++] = byte_count - 1;
1896 0 : }
1897 :
1898 : static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1899 : .copy_max_bytes = 0x400000,
1900 : .copy_num_dw = 7,
1901 : .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1902 :
1903 : .fill_max_bytes = 0x400000,
1904 : .fill_num_dw = 5,
1905 : .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1906 : };
1907 :
1908 : static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1909 : {
1910 0 : if (adev->mman.buffer_funcs == NULL) {
1911 0 : adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1912 0 : adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1913 : }
1914 : }
1915 :
1916 : static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1917 : .copy_pte_num_dw = 7,
1918 : .copy_pte = sdma_v5_2_vm_copy_pte,
1919 : .write_pte = sdma_v5_2_vm_write_pte,
1920 : .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1921 : };
1922 :
1923 : static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1924 : {
1925 : unsigned i;
1926 :
1927 0 : if (adev->vm_manager.vm_pte_funcs == NULL) {
1928 0 : adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1929 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1930 0 : adev->vm_manager.vm_pte_scheds[i] =
1931 0 : &adev->sdma.instance[i].ring.sched;
1932 : }
1933 0 : adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1934 : }
1935 : }
1936 :
1937 : const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1938 : .type = AMD_IP_BLOCK_TYPE_SDMA,
1939 : .major = 5,
1940 : .minor = 2,
1941 : .rev = 0,
1942 : .funcs = &sdma_v5_2_ip_funcs,
1943 : };
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