Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 : #include <linux/firmware.h>
24 : #include <linux/slab.h>
25 : #include <linux/module.h>
26 : #include <linux/pci.h>
27 :
28 : #include <drm/amdgpu_drm.h>
29 :
30 : #include "amdgpu.h"
31 : #include "amdgpu_atombios.h"
32 : #include "amdgpu_ih.h"
33 : #include "amdgpu_uvd.h"
34 : #include "amdgpu_vce.h"
35 : #include "amdgpu_ucode.h"
36 : #include "amdgpu_psp.h"
37 : #include "atom.h"
38 : #include "amd_pcie.h"
39 :
40 : #include "uvd/uvd_7_0_offset.h"
41 : #include "gc/gc_9_0_offset.h"
42 : #include "gc/gc_9_0_sh_mask.h"
43 : #include "sdma0/sdma0_4_0_offset.h"
44 : #include "sdma1/sdma1_4_0_offset.h"
45 : #include "nbio/nbio_7_0_default.h"
46 : #include "nbio/nbio_7_0_offset.h"
47 : #include "nbio/nbio_7_0_sh_mask.h"
48 : #include "nbio/nbio_7_0_smn.h"
49 : #include "mp/mp_9_0_offset.h"
50 :
51 : #include "soc15.h"
52 : #include "soc15_common.h"
53 : #include "gfx_v9_0.h"
54 : #include "gmc_v9_0.h"
55 : #include "gfxhub_v1_0.h"
56 : #include "mmhub_v1_0.h"
57 : #include "df_v1_7.h"
58 : #include "df_v3_6.h"
59 : #include "nbio_v6_1.h"
60 : #include "nbio_v7_0.h"
61 : #include "nbio_v7_4.h"
62 : #include "hdp_v4_0.h"
63 : #include "vega10_ih.h"
64 : #include "vega20_ih.h"
65 : #include "navi10_ih.h"
66 : #include "sdma_v4_0.h"
67 : #include "uvd_v7_0.h"
68 : #include "vce_v4_0.h"
69 : #include "vcn_v1_0.h"
70 : #include "vcn_v2_0.h"
71 : #include "jpeg_v2_0.h"
72 : #include "vcn_v2_5.h"
73 : #include "jpeg_v2_5.h"
74 : #include "smuio_v9_0.h"
75 : #include "smuio_v11_0.h"
76 : #include "smuio_v13_0.h"
77 : #include "amdgpu_vkms.h"
78 : #include "mxgpu_ai.h"
79 : #include "amdgpu_ras.h"
80 : #include "amdgpu_xgmi.h"
81 : #include <uapi/linux/kfd_ioctl.h>
82 :
83 : #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 : #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 : #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 : #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87 :
88 : static const struct amd_ip_funcs soc15_common_ip_funcs;
89 :
90 : /* Vega, Raven, Arcturus */
91 : static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92 : {
93 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
95 : };
96 :
97 : static const struct amdgpu_video_codecs vega_video_codecs_encode =
98 : {
99 : .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 : .codec_array = vega_video_codecs_encode_array,
101 : };
102 :
103 : /* Vega */
104 : static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105 : {
106 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
107 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
108 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
109 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
110 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
112 : };
113 :
114 : static const struct amdgpu_video_codecs vega_video_codecs_decode =
115 : {
116 : .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
117 : .codec_array = vega_video_codecs_decode_array,
118 : };
119 :
120 : /* Raven */
121 : static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
122 : {
123 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
124 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
125 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
126 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
127 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
128 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
129 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
130 : };
131 :
132 : static const struct amdgpu_video_codecs rv_video_codecs_decode =
133 : {
134 : .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
135 : .codec_array = rv_video_codecs_decode_array,
136 : };
137 :
138 : /* Renoir, Arcturus */
139 : static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
140 : {
141 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
142 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
143 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
144 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
145 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
146 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
147 : {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
148 : };
149 :
150 : static const struct amdgpu_video_codecs rn_video_codecs_decode =
151 : {
152 : .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 : .codec_array = rn_video_codecs_decode_array,
154 : };
155 :
156 0 : static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
157 : const struct amdgpu_video_codecs **codecs)
158 : {
159 0 : if (adev->ip_versions[VCE_HWIP][0]) {
160 0 : switch (adev->ip_versions[VCE_HWIP][0]) {
161 : case IP_VERSION(4, 0, 0):
162 : case IP_VERSION(4, 1, 0):
163 0 : if (encode)
164 0 : *codecs = &vega_video_codecs_encode;
165 : else
166 0 : *codecs = &vega_video_codecs_decode;
167 : return 0;
168 : default:
169 : return -EINVAL;
170 : }
171 : } else {
172 0 : switch (adev->ip_versions[UVD_HWIP][0]) {
173 : case IP_VERSION(1, 0, 0):
174 : case IP_VERSION(1, 0, 1):
175 0 : if (encode)
176 0 : *codecs = &vega_video_codecs_encode;
177 : else
178 0 : *codecs = &rv_video_codecs_decode;
179 : return 0;
180 : case IP_VERSION(2, 5, 0):
181 : case IP_VERSION(2, 6, 0):
182 : case IP_VERSION(2, 2, 0):
183 0 : if (encode)
184 0 : *codecs = &vega_video_codecs_encode;
185 : else
186 0 : *codecs = &rn_video_codecs_decode;
187 : return 0;
188 : default:
189 : return -EINVAL;
190 : }
191 : }
192 : }
193 :
194 : /*
195 : * Indirect registers accessor
196 : */
197 0 : static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
198 : {
199 : unsigned long address, data;
200 0 : address = adev->nbio.funcs->get_pcie_index_offset(adev);
201 0 : data = adev->nbio.funcs->get_pcie_data_offset(adev);
202 :
203 0 : return amdgpu_device_indirect_rreg(adev, address, data, reg);
204 : }
205 :
206 0 : static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
207 : {
208 : unsigned long address, data;
209 :
210 0 : address = adev->nbio.funcs->get_pcie_index_offset(adev);
211 0 : data = adev->nbio.funcs->get_pcie_data_offset(adev);
212 :
213 0 : amdgpu_device_indirect_wreg(adev, address, data, reg, v);
214 0 : }
215 :
216 0 : static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
217 : {
218 : unsigned long address, data;
219 0 : address = adev->nbio.funcs->get_pcie_index_offset(adev);
220 0 : data = adev->nbio.funcs->get_pcie_data_offset(adev);
221 :
222 0 : return amdgpu_device_indirect_rreg64(adev, address, data, reg);
223 : }
224 :
225 0 : static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
226 : {
227 : unsigned long address, data;
228 :
229 0 : address = adev->nbio.funcs->get_pcie_index_offset(adev);
230 0 : data = adev->nbio.funcs->get_pcie_data_offset(adev);
231 :
232 0 : amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
233 0 : }
234 :
235 0 : static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
236 : {
237 : unsigned long flags, address, data;
238 : u32 r;
239 :
240 0 : address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
241 0 : data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
242 :
243 0 : spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
244 0 : WREG32(address, ((reg) & 0x1ff));
245 0 : r = RREG32(data);
246 0 : spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
247 0 : return r;
248 : }
249 :
250 0 : static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
251 : {
252 : unsigned long flags, address, data;
253 :
254 0 : address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
255 0 : data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
256 :
257 0 : spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
258 0 : WREG32(address, ((reg) & 0x1ff));
259 0 : WREG32(data, (v));
260 0 : spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
261 0 : }
262 :
263 0 : static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
264 : {
265 : unsigned long flags, address, data;
266 : u32 r;
267 :
268 0 : address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
269 0 : data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
270 :
271 0 : spin_lock_irqsave(&adev->didt_idx_lock, flags);
272 0 : WREG32(address, (reg));
273 0 : r = RREG32(data);
274 0 : spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
275 0 : return r;
276 : }
277 :
278 0 : static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
279 : {
280 : unsigned long flags, address, data;
281 :
282 0 : address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
283 0 : data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
284 :
285 0 : spin_lock_irqsave(&adev->didt_idx_lock, flags);
286 0 : WREG32(address, (reg));
287 0 : WREG32(data, (v));
288 0 : spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
289 0 : }
290 :
291 0 : static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
292 : {
293 : unsigned long flags;
294 : u32 r;
295 :
296 0 : spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
297 0 : WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
298 0 : r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
299 0 : spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
300 0 : return r;
301 : }
302 :
303 0 : static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
304 : {
305 : unsigned long flags;
306 :
307 0 : spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
308 0 : WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
309 0 : WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
310 0 : spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
311 0 : }
312 :
313 0 : static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
314 : {
315 : unsigned long flags;
316 : u32 r;
317 :
318 0 : spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
319 0 : WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
320 0 : r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
321 0 : spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
322 0 : return r;
323 : }
324 :
325 0 : static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
326 : {
327 : unsigned long flags;
328 :
329 0 : spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
330 0 : WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
331 0 : WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
332 0 : spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
333 0 : }
334 :
335 0 : static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
336 : {
337 0 : return adev->nbio.funcs->get_memsize(adev);
338 : }
339 :
340 0 : static u32 soc15_get_xclk(struct amdgpu_device *adev)
341 : {
342 0 : u32 reference_clock = adev->clock.spll.reference_freq;
343 :
344 0 : if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
345 : adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
346 : return 10000;
347 0 : if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
348 : adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
349 0 : return reference_clock / 4;
350 :
351 : return reference_clock;
352 : }
353 :
354 :
355 0 : void soc15_grbm_select(struct amdgpu_device *adev,
356 : u32 me, u32 pipe, u32 queue, u32 vmid)
357 : {
358 0 : u32 grbm_gfx_cntl = 0;
359 0 : grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
360 0 : grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
361 0 : grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
362 0 : grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
363 :
364 0 : WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
365 0 : }
366 :
367 0 : static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
368 : {
369 : /* todo */
370 0 : }
371 :
372 0 : static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
373 : {
374 : /* todo */
375 0 : return false;
376 : }
377 :
378 : static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
379 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
380 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
381 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
382 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
383 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
384 : { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
385 : { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
386 : { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
387 : { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
388 : { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
389 : { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
390 : { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
391 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
392 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
393 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
394 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
395 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
396 : { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
397 : { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
398 : { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
399 : };
400 :
401 0 : static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
402 : u32 sh_num, u32 reg_offset)
403 : {
404 : uint32_t val;
405 :
406 0 : mutex_lock(&adev->grbm_idx_mutex);
407 0 : if (se_num != 0xffffffff || sh_num != 0xffffffff)
408 0 : amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
409 :
410 0 : val = RREG32(reg_offset);
411 :
412 0 : if (se_num != 0xffffffff || sh_num != 0xffffffff)
413 0 : amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
414 0 : mutex_unlock(&adev->grbm_idx_mutex);
415 0 : return val;
416 : }
417 :
418 0 : static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
419 : bool indexed, u32 se_num,
420 : u32 sh_num, u32 reg_offset)
421 : {
422 0 : if (indexed) {
423 0 : return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
424 : } else {
425 0 : if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
426 0 : return adev->gfx.config.gb_addr_config;
427 0 : else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
428 0 : return adev->gfx.config.db_debug2;
429 0 : return RREG32(reg_offset);
430 : }
431 : }
432 :
433 0 : static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
434 : u32 sh_num, u32 reg_offset, u32 *value)
435 : {
436 : uint32_t i;
437 : struct soc15_allowed_register_entry *en;
438 :
439 0 : *value = 0;
440 0 : for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
441 0 : en = &soc15_allowed_read_registers[i];
442 0 : if (adev->reg_offset[en->hwip][en->inst] &&
443 0 : reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
444 0 : + en->reg_offset))
445 0 : continue;
446 :
447 0 : *value = soc15_get_register_value(adev,
448 0 : soc15_allowed_read_registers[i].grbm_indexed,
449 : se_num, sh_num, reg_offset);
450 0 : return 0;
451 : }
452 : return -EINVAL;
453 : }
454 :
455 :
456 : /**
457 : * soc15_program_register_sequence - program an array of registers.
458 : *
459 : * @adev: amdgpu_device pointer
460 : * @regs: pointer to the register array
461 : * @array_size: size of the register array
462 : *
463 : * Programs an array or registers with and and or masks.
464 : * This is a helper for setting golden registers.
465 : */
466 :
467 0 : void soc15_program_register_sequence(struct amdgpu_device *adev,
468 : const struct soc15_reg_golden *regs,
469 : const u32 array_size)
470 : {
471 : const struct soc15_reg_golden *entry;
472 : u32 tmp, reg;
473 : int i;
474 :
475 0 : for (i = 0; i < array_size; ++i) {
476 0 : entry = ®s[i];
477 0 : reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
478 :
479 0 : if (entry->and_mask == 0xffffffff) {
480 0 : tmp = entry->or_mask;
481 : } else {
482 0 : tmp = (entry->hwip == GC_HWIP) ?
483 0 : RREG32_SOC15_IP(GC, reg) : RREG32(reg);
484 :
485 0 : tmp &= ~(entry->and_mask);
486 0 : tmp |= (entry->or_mask & entry->and_mask);
487 : }
488 :
489 0 : if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
490 0 : reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
491 0 : reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
492 0 : reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
493 0 : WREG32_RLC(reg, tmp);
494 : else
495 0 : (entry->hwip == GC_HWIP) ?
496 0 : WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
497 :
498 : }
499 :
500 0 : }
501 :
502 0 : static int soc15_asic_baco_reset(struct amdgpu_device *adev)
503 : {
504 0 : struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
505 0 : int ret = 0;
506 :
507 : /* avoid NBIF got stuck when do RAS recovery in BACO reset */
508 0 : if (ras && adev->ras_enabled)
509 0 : adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
510 :
511 0 : ret = amdgpu_dpm_baco_reset(adev);
512 0 : if (ret)
513 : return ret;
514 :
515 : /* re-enable doorbell interrupt after BACO exit */
516 0 : if (ras && adev->ras_enabled)
517 0 : adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
518 :
519 : return 0;
520 : }
521 :
522 : static enum amd_reset_method
523 0 : soc15_asic_reset_method(struct amdgpu_device *adev)
524 : {
525 0 : bool baco_reset = false;
526 0 : bool connected_to_cpu = false;
527 0 : struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
528 :
529 0 : if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
530 0 : connected_to_cpu = true;
531 :
532 0 : if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
533 : amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
534 0 : amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
535 : amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
536 : /* If connected to cpu, driver only support mode2 */
537 0 : if (connected_to_cpu)
538 : return AMD_RESET_METHOD_MODE2;
539 0 : return amdgpu_reset_method;
540 : }
541 :
542 0 : if (amdgpu_reset_method != -1)
543 0 : dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
544 : amdgpu_reset_method);
545 :
546 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
547 : case IP_VERSION(10, 0, 0):
548 : case IP_VERSION(10, 0, 1):
549 : case IP_VERSION(12, 0, 0):
550 : case IP_VERSION(12, 0, 1):
551 : return AMD_RESET_METHOD_MODE2;
552 : case IP_VERSION(9, 0, 0):
553 : case IP_VERSION(11, 0, 2):
554 0 : if (adev->asic_type == CHIP_VEGA20) {
555 0 : if (adev->psp.sos.fw_version >= 0x80067)
556 0 : baco_reset = amdgpu_dpm_is_baco_supported(adev);
557 : /*
558 : * 1. PMFW version > 0x284300: all cases use baco
559 : * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
560 : */
561 0 : if (ras && adev->ras_enabled &&
562 0 : adev->pm.fw_version <= 0x283400)
563 0 : baco_reset = false;
564 : } else {
565 0 : baco_reset = amdgpu_dpm_is_baco_supported(adev);
566 : }
567 : break;
568 : case IP_VERSION(13, 0, 2):
569 : /*
570 : * 1.connected to cpu: driver issue mode2 reset
571 : * 2.discret gpu: driver issue mode1 reset
572 : */
573 0 : if (connected_to_cpu)
574 : return AMD_RESET_METHOD_MODE2;
575 : break;
576 : default:
577 : break;
578 : }
579 :
580 0 : if (baco_reset)
581 : return AMD_RESET_METHOD_BACO;
582 : else
583 0 : return AMD_RESET_METHOD_MODE1;
584 : }
585 :
586 0 : static int soc15_asic_reset(struct amdgpu_device *adev)
587 : {
588 : /* original raven doesn't have full asic reset */
589 0 : if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
590 : (adev->apu_flags & AMD_APU_IS_RAVEN2))
591 : return 0;
592 :
593 0 : switch (soc15_asic_reset_method(adev)) {
594 : case AMD_RESET_METHOD_PCI:
595 0 : dev_info(adev->dev, "PCI reset\n");
596 0 : return amdgpu_device_pci_reset(adev);
597 : case AMD_RESET_METHOD_BACO:
598 0 : dev_info(adev->dev, "BACO reset\n");
599 0 : return soc15_asic_baco_reset(adev);
600 : case AMD_RESET_METHOD_MODE2:
601 0 : dev_info(adev->dev, "MODE2 reset\n");
602 0 : return amdgpu_dpm_mode2_reset(adev);
603 : default:
604 0 : dev_info(adev->dev, "MODE1 reset\n");
605 0 : return amdgpu_device_mode1_reset(adev);
606 : }
607 : }
608 :
609 0 : static bool soc15_supports_baco(struct amdgpu_device *adev)
610 : {
611 0 : switch (adev->ip_versions[MP1_HWIP][0]) {
612 : case IP_VERSION(9, 0, 0):
613 : case IP_VERSION(11, 0, 2):
614 0 : if (adev->asic_type == CHIP_VEGA20) {
615 0 : if (adev->psp.sos.fw_version >= 0x80067)
616 0 : return amdgpu_dpm_is_baco_supported(adev);
617 : return false;
618 : } else {
619 0 : return amdgpu_dpm_is_baco_supported(adev);
620 : }
621 : break;
622 : default:
623 : return false;
624 : }
625 : }
626 :
627 : /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
628 : u32 cntl_reg, u32 status_reg)
629 : {
630 : return 0;
631 : }*/
632 :
633 0 : static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
634 : {
635 : /*int r;
636 :
637 : r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
638 : if (r)
639 : return r;
640 :
641 : r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
642 : */
643 0 : return 0;
644 : }
645 :
646 0 : static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
647 : {
648 : /* todo */
649 :
650 0 : return 0;
651 : }
652 :
653 : static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
654 : {
655 0 : if (pci_is_root_bus(adev->pdev->bus))
656 : return;
657 :
658 : if (amdgpu_pcie_gen2 == 0)
659 : return;
660 :
661 : if (adev->flags & AMD_IS_APU)
662 : return;
663 :
664 : if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
665 : CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
666 : return;
667 :
668 : /* todo */
669 : }
670 :
671 0 : static void soc15_program_aspm(struct amdgpu_device *adev)
672 : {
673 0 : if (!amdgpu_device_should_use_aspm(adev))
674 : return;
675 :
676 0 : if (!(adev->flags & AMD_IS_APU) &&
677 0 : (adev->nbio.funcs->program_aspm))
678 0 : adev->nbio.funcs->program_aspm(adev);
679 : }
680 :
681 : static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
682 : bool enable)
683 : {
684 0 : adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
685 0 : adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
686 : }
687 :
688 : const struct amdgpu_ip_block_version vega10_common_ip_block =
689 : {
690 : .type = AMD_IP_BLOCK_TYPE_COMMON,
691 : .major = 2,
692 : .minor = 0,
693 : .rev = 0,
694 : .funcs = &soc15_common_ip_funcs,
695 : };
696 :
697 : static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
698 : {
699 0 : return adev->nbio.funcs->get_rev_id(adev);
700 : }
701 :
702 0 : static void soc15_reg_base_init(struct amdgpu_device *adev)
703 : {
704 : /* Set IP register base before any HW register access */
705 0 : switch (adev->asic_type) {
706 : case CHIP_VEGA10:
707 : case CHIP_VEGA12:
708 : case CHIP_RAVEN:
709 : case CHIP_RENOIR:
710 0 : vega10_reg_base_init(adev);
711 0 : break;
712 : case CHIP_VEGA20:
713 0 : vega20_reg_base_init(adev);
714 0 : break;
715 : case CHIP_ARCTURUS:
716 0 : arct_reg_base_init(adev);
717 0 : break;
718 : case CHIP_ALDEBARAN:
719 0 : aldebaran_reg_base_init(adev);
720 0 : break;
721 : default:
722 0 : DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
723 0 : break;
724 : }
725 0 : }
726 :
727 0 : void soc15_set_virt_ops(struct amdgpu_device *adev)
728 : {
729 0 : adev->virt.ops = &xgpu_ai_virt_ops;
730 :
731 : /* init soc15 reg base early enough so we can
732 : * request request full access for sriov before
733 : * set_ip_blocks. */
734 0 : soc15_reg_base_init(adev);
735 0 : }
736 :
737 0 : static bool soc15_need_full_reset(struct amdgpu_device *adev)
738 : {
739 : /* change this when we implement soft reset */
740 0 : return true;
741 : }
742 :
743 0 : static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
744 : uint64_t *count1)
745 : {
746 0 : uint32_t perfctr = 0;
747 : uint64_t cnt0_of, cnt1_of;
748 : int tmp;
749 :
750 : /* This reports 0 on APUs, so return to avoid writing/reading registers
751 : * that may or may not be different from their GPU counterparts
752 : */
753 0 : if (adev->flags & AMD_IS_APU)
754 : return;
755 :
756 : /* Set the 2 events that we wish to watch, defined above */
757 : /* Reg 40 is # received msgs */
758 : /* Reg 104 is # of posted requests sent */
759 0 : perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
760 0 : perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
761 :
762 : /* Write to enable desired perf counters */
763 0 : WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
764 : /* Zero out and enable the perf counters
765 : * Write 0x5:
766 : * Bit 0 = Start all counters(1)
767 : * Bit 2 = Global counter reset enable(1)
768 : */
769 0 : WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
770 :
771 0 : msleep(1000);
772 :
773 : /* Load the shadow and disable the perf counters
774 : * Write 0x2:
775 : * Bit 0 = Stop counters(0)
776 : * Bit 1 = Load the shadow counters(1)
777 : */
778 0 : WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
779 :
780 : /* Read register values to get any >32bit overflow */
781 0 : tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
782 0 : cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
783 0 : cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
784 :
785 : /* Get the values and add the overflow */
786 0 : *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
787 0 : *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
788 : }
789 :
790 0 : static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
791 : uint64_t *count1)
792 : {
793 0 : uint32_t perfctr = 0;
794 : uint64_t cnt0_of, cnt1_of;
795 : int tmp;
796 :
797 : /* This reports 0 on APUs, so return to avoid writing/reading registers
798 : * that may or may not be different from their GPU counterparts
799 : */
800 0 : if (adev->flags & AMD_IS_APU)
801 : return;
802 :
803 : /* Set the 2 events that we wish to watch, defined above */
804 : /* Reg 40 is # received msgs */
805 : /* Reg 108 is # of posted requests sent on VG20 */
806 0 : perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
807 : EVENT0_SEL, 40);
808 0 : perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
809 : EVENT1_SEL, 108);
810 :
811 : /* Write to enable desired perf counters */
812 0 : WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
813 : /* Zero out and enable the perf counters
814 : * Write 0x5:
815 : * Bit 0 = Start all counters(1)
816 : * Bit 2 = Global counter reset enable(1)
817 : */
818 0 : WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
819 :
820 0 : msleep(1000);
821 :
822 : /* Load the shadow and disable the perf counters
823 : * Write 0x2:
824 : * Bit 0 = Stop counters(0)
825 : * Bit 1 = Load the shadow counters(1)
826 : */
827 0 : WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
828 :
829 : /* Read register values to get any >32bit overflow */
830 0 : tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
831 0 : cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
832 0 : cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
833 :
834 : /* Get the values and add the overflow */
835 0 : *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
836 0 : *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
837 : }
838 :
839 0 : static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
840 : {
841 : u32 sol_reg;
842 :
843 : /* CP hangs in IGT reloading test on RN, reset to WA */
844 0 : if (adev->asic_type == CHIP_RENOIR)
845 : return true;
846 :
847 : /* Just return false for soc15 GPUs. Reset does not seem to
848 : * be necessary.
849 : */
850 0 : if (!amdgpu_passthrough(adev))
851 : return false;
852 :
853 0 : if (adev->flags & AMD_IS_APU)
854 : return false;
855 :
856 : /* Check sOS sign of life register to confirm sys driver and sOS
857 : * are already been loaded.
858 : */
859 0 : sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
860 0 : if (sol_reg)
861 : return true;
862 :
863 0 : return false;
864 : }
865 :
866 0 : static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
867 : {
868 : uint64_t nak_r, nak_g;
869 :
870 : /* Get the number of NAKs received and generated */
871 0 : nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
872 0 : nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
873 :
874 : /* Add the total number of NAKs, i.e the number of replays */
875 0 : return (nak_r + nak_g);
876 : }
877 :
878 0 : static void soc15_pre_asic_init(struct amdgpu_device *adev)
879 : {
880 0 : gmc_v9_0_restore_registers(adev);
881 0 : }
882 :
883 : static const struct amdgpu_asic_funcs soc15_asic_funcs =
884 : {
885 : .read_disabled_bios = &soc15_read_disabled_bios,
886 : .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
887 : .read_register = &soc15_read_register,
888 : .reset = &soc15_asic_reset,
889 : .reset_method = &soc15_asic_reset_method,
890 : .set_vga_state = &soc15_vga_set_state,
891 : .get_xclk = &soc15_get_xclk,
892 : .set_uvd_clocks = &soc15_set_uvd_clocks,
893 : .set_vce_clocks = &soc15_set_vce_clocks,
894 : .get_config_memsize = &soc15_get_config_memsize,
895 : .need_full_reset = &soc15_need_full_reset,
896 : .init_doorbell_index = &vega10_doorbell_index_init,
897 : .get_pcie_usage = &soc15_get_pcie_usage,
898 : .need_reset_on_init = &soc15_need_reset_on_init,
899 : .get_pcie_replay_count = &soc15_get_pcie_replay_count,
900 : .supports_baco = &soc15_supports_baco,
901 : .pre_asic_init = &soc15_pre_asic_init,
902 : .query_video_codecs = &soc15_query_video_codecs,
903 : };
904 :
905 : static const struct amdgpu_asic_funcs vega20_asic_funcs =
906 : {
907 : .read_disabled_bios = &soc15_read_disabled_bios,
908 : .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
909 : .read_register = &soc15_read_register,
910 : .reset = &soc15_asic_reset,
911 : .reset_method = &soc15_asic_reset_method,
912 : .set_vga_state = &soc15_vga_set_state,
913 : .get_xclk = &soc15_get_xclk,
914 : .set_uvd_clocks = &soc15_set_uvd_clocks,
915 : .set_vce_clocks = &soc15_set_vce_clocks,
916 : .get_config_memsize = &soc15_get_config_memsize,
917 : .need_full_reset = &soc15_need_full_reset,
918 : .init_doorbell_index = &vega20_doorbell_index_init,
919 : .get_pcie_usage = &vega20_get_pcie_usage,
920 : .need_reset_on_init = &soc15_need_reset_on_init,
921 : .get_pcie_replay_count = &soc15_get_pcie_replay_count,
922 : .supports_baco = &soc15_supports_baco,
923 : .pre_asic_init = &soc15_pre_asic_init,
924 : .query_video_codecs = &soc15_query_video_codecs,
925 : };
926 :
927 0 : static int soc15_common_early_init(void *handle)
928 : {
929 : #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
930 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
931 :
932 0 : if (!amdgpu_sriov_vf(adev)) {
933 0 : adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
934 0 : adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
935 : }
936 0 : adev->smc_rreg = NULL;
937 0 : adev->smc_wreg = NULL;
938 0 : adev->pcie_rreg = &soc15_pcie_rreg;
939 0 : adev->pcie_wreg = &soc15_pcie_wreg;
940 0 : adev->pcie_rreg64 = &soc15_pcie_rreg64;
941 0 : adev->pcie_wreg64 = &soc15_pcie_wreg64;
942 0 : adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
943 0 : adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
944 0 : adev->didt_rreg = &soc15_didt_rreg;
945 0 : adev->didt_wreg = &soc15_didt_wreg;
946 0 : adev->gc_cac_rreg = &soc15_gc_cac_rreg;
947 0 : adev->gc_cac_wreg = &soc15_gc_cac_wreg;
948 0 : adev->se_cac_rreg = &soc15_se_cac_rreg;
949 0 : adev->se_cac_wreg = &soc15_se_cac_wreg;
950 :
951 0 : adev->rev_id = soc15_get_rev_id(adev);
952 0 : adev->external_rev_id = 0xFF;
953 : /* TODO: split the GC and PG flags based on the relevant IP version for which
954 : * they are relevant.
955 : */
956 0 : switch (adev->ip_versions[GC_HWIP][0]) {
957 : case IP_VERSION(9, 0, 1):
958 0 : adev->asic_funcs = &soc15_asic_funcs;
959 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
960 : AMD_CG_SUPPORT_GFX_MGLS |
961 : AMD_CG_SUPPORT_GFX_RLC_LS |
962 : AMD_CG_SUPPORT_GFX_CP_LS |
963 : AMD_CG_SUPPORT_GFX_3D_CGCG |
964 : AMD_CG_SUPPORT_GFX_3D_CGLS |
965 : AMD_CG_SUPPORT_GFX_CGCG |
966 : AMD_CG_SUPPORT_GFX_CGLS |
967 : AMD_CG_SUPPORT_BIF_MGCG |
968 : AMD_CG_SUPPORT_BIF_LS |
969 : AMD_CG_SUPPORT_HDP_LS |
970 : AMD_CG_SUPPORT_DRM_MGCG |
971 : AMD_CG_SUPPORT_DRM_LS |
972 : AMD_CG_SUPPORT_ROM_MGCG |
973 : AMD_CG_SUPPORT_DF_MGCG |
974 : AMD_CG_SUPPORT_SDMA_MGCG |
975 : AMD_CG_SUPPORT_SDMA_LS |
976 : AMD_CG_SUPPORT_MC_MGCG |
977 : AMD_CG_SUPPORT_MC_LS;
978 0 : adev->pg_flags = 0;
979 0 : adev->external_rev_id = 0x1;
980 0 : break;
981 : case IP_VERSION(9, 2, 1):
982 0 : adev->asic_funcs = &soc15_asic_funcs;
983 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
984 : AMD_CG_SUPPORT_GFX_MGLS |
985 : AMD_CG_SUPPORT_GFX_CGCG |
986 : AMD_CG_SUPPORT_GFX_CGLS |
987 : AMD_CG_SUPPORT_GFX_3D_CGCG |
988 : AMD_CG_SUPPORT_GFX_3D_CGLS |
989 : AMD_CG_SUPPORT_GFX_CP_LS |
990 : AMD_CG_SUPPORT_MC_LS |
991 : AMD_CG_SUPPORT_MC_MGCG |
992 : AMD_CG_SUPPORT_SDMA_MGCG |
993 : AMD_CG_SUPPORT_SDMA_LS |
994 : AMD_CG_SUPPORT_BIF_MGCG |
995 : AMD_CG_SUPPORT_BIF_LS |
996 : AMD_CG_SUPPORT_HDP_MGCG |
997 : AMD_CG_SUPPORT_HDP_LS |
998 : AMD_CG_SUPPORT_ROM_MGCG |
999 : AMD_CG_SUPPORT_VCE_MGCG |
1000 : AMD_CG_SUPPORT_UVD_MGCG;
1001 0 : adev->pg_flags = 0;
1002 0 : adev->external_rev_id = adev->rev_id + 0x14;
1003 0 : break;
1004 : case IP_VERSION(9, 4, 0):
1005 0 : adev->asic_funcs = &vega20_asic_funcs;
1006 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1007 : AMD_CG_SUPPORT_GFX_MGLS |
1008 : AMD_CG_SUPPORT_GFX_CGCG |
1009 : AMD_CG_SUPPORT_GFX_CGLS |
1010 : AMD_CG_SUPPORT_GFX_3D_CGCG |
1011 : AMD_CG_SUPPORT_GFX_3D_CGLS |
1012 : AMD_CG_SUPPORT_GFX_CP_LS |
1013 : AMD_CG_SUPPORT_MC_LS |
1014 : AMD_CG_SUPPORT_MC_MGCG |
1015 : AMD_CG_SUPPORT_SDMA_MGCG |
1016 : AMD_CG_SUPPORT_SDMA_LS |
1017 : AMD_CG_SUPPORT_BIF_MGCG |
1018 : AMD_CG_SUPPORT_BIF_LS |
1019 : AMD_CG_SUPPORT_HDP_MGCG |
1020 : AMD_CG_SUPPORT_HDP_LS |
1021 : AMD_CG_SUPPORT_ROM_MGCG |
1022 : AMD_CG_SUPPORT_VCE_MGCG |
1023 : AMD_CG_SUPPORT_UVD_MGCG;
1024 0 : adev->pg_flags = 0;
1025 0 : adev->external_rev_id = adev->rev_id + 0x28;
1026 0 : break;
1027 : case IP_VERSION(9, 1, 0):
1028 : case IP_VERSION(9, 2, 2):
1029 0 : adev->asic_funcs = &soc15_asic_funcs;
1030 :
1031 0 : if (adev->rev_id >= 0x8)
1032 0 : adev->apu_flags |= AMD_APU_IS_RAVEN2;
1033 :
1034 0 : if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1035 0 : adev->external_rev_id = adev->rev_id + 0x79;
1036 0 : else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1037 0 : adev->external_rev_id = adev->rev_id + 0x41;
1038 0 : else if (adev->rev_id == 1)
1039 0 : adev->external_rev_id = adev->rev_id + 0x20;
1040 : else
1041 0 : adev->external_rev_id = adev->rev_id + 0x01;
1042 :
1043 0 : if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1044 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1045 : AMD_CG_SUPPORT_GFX_MGLS |
1046 : AMD_CG_SUPPORT_GFX_CP_LS |
1047 : AMD_CG_SUPPORT_GFX_3D_CGCG |
1048 : AMD_CG_SUPPORT_GFX_3D_CGLS |
1049 : AMD_CG_SUPPORT_GFX_CGCG |
1050 : AMD_CG_SUPPORT_GFX_CGLS |
1051 : AMD_CG_SUPPORT_BIF_LS |
1052 : AMD_CG_SUPPORT_HDP_LS |
1053 : AMD_CG_SUPPORT_MC_MGCG |
1054 : AMD_CG_SUPPORT_MC_LS |
1055 : AMD_CG_SUPPORT_SDMA_MGCG |
1056 : AMD_CG_SUPPORT_SDMA_LS |
1057 : AMD_CG_SUPPORT_VCN_MGCG;
1058 :
1059 0 : adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1060 0 : } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1061 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1062 : AMD_CG_SUPPORT_GFX_MGLS |
1063 : AMD_CG_SUPPORT_GFX_CP_LS |
1064 : AMD_CG_SUPPORT_GFX_3D_CGLS |
1065 : AMD_CG_SUPPORT_GFX_CGCG |
1066 : AMD_CG_SUPPORT_GFX_CGLS |
1067 : AMD_CG_SUPPORT_BIF_LS |
1068 : AMD_CG_SUPPORT_HDP_LS |
1069 : AMD_CG_SUPPORT_MC_MGCG |
1070 : AMD_CG_SUPPORT_MC_LS |
1071 : AMD_CG_SUPPORT_SDMA_MGCG |
1072 : AMD_CG_SUPPORT_SDMA_LS |
1073 : AMD_CG_SUPPORT_VCN_MGCG;
1074 :
1075 : /*
1076 : * MMHUB PG needs to be disabled for Picasso for
1077 : * stability reasons.
1078 : */
1079 0 : adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1080 : AMD_PG_SUPPORT_VCN;
1081 : } else {
1082 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1083 : AMD_CG_SUPPORT_GFX_MGLS |
1084 : AMD_CG_SUPPORT_GFX_RLC_LS |
1085 : AMD_CG_SUPPORT_GFX_CP_LS |
1086 : AMD_CG_SUPPORT_GFX_3D_CGLS |
1087 : AMD_CG_SUPPORT_GFX_CGCG |
1088 : AMD_CG_SUPPORT_GFX_CGLS |
1089 : AMD_CG_SUPPORT_BIF_MGCG |
1090 : AMD_CG_SUPPORT_BIF_LS |
1091 : AMD_CG_SUPPORT_HDP_MGCG |
1092 : AMD_CG_SUPPORT_HDP_LS |
1093 : AMD_CG_SUPPORT_DRM_MGCG |
1094 : AMD_CG_SUPPORT_DRM_LS |
1095 : AMD_CG_SUPPORT_MC_MGCG |
1096 : AMD_CG_SUPPORT_MC_LS |
1097 : AMD_CG_SUPPORT_SDMA_MGCG |
1098 : AMD_CG_SUPPORT_SDMA_LS |
1099 : AMD_CG_SUPPORT_VCN_MGCG;
1100 :
1101 0 : adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1102 : }
1103 : break;
1104 : case IP_VERSION(9, 4, 1):
1105 0 : adev->asic_funcs = &vega20_asic_funcs;
1106 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1107 : AMD_CG_SUPPORT_GFX_MGLS |
1108 : AMD_CG_SUPPORT_GFX_CGCG |
1109 : AMD_CG_SUPPORT_GFX_CGLS |
1110 : AMD_CG_SUPPORT_GFX_CP_LS |
1111 : AMD_CG_SUPPORT_HDP_MGCG |
1112 : AMD_CG_SUPPORT_HDP_LS |
1113 : AMD_CG_SUPPORT_SDMA_MGCG |
1114 : AMD_CG_SUPPORT_SDMA_LS |
1115 : AMD_CG_SUPPORT_MC_MGCG |
1116 : AMD_CG_SUPPORT_MC_LS |
1117 : AMD_CG_SUPPORT_IH_CG |
1118 : AMD_CG_SUPPORT_VCN_MGCG |
1119 : AMD_CG_SUPPORT_JPEG_MGCG;
1120 0 : adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1121 0 : adev->external_rev_id = adev->rev_id + 0x32;
1122 0 : break;
1123 : case IP_VERSION(9, 3, 0):
1124 0 : adev->asic_funcs = &soc15_asic_funcs;
1125 :
1126 0 : if (adev->apu_flags & AMD_APU_IS_RENOIR)
1127 0 : adev->external_rev_id = adev->rev_id + 0x91;
1128 : else
1129 0 : adev->external_rev_id = adev->rev_id + 0xa1;
1130 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1131 : AMD_CG_SUPPORT_GFX_MGLS |
1132 : AMD_CG_SUPPORT_GFX_3D_CGCG |
1133 : AMD_CG_SUPPORT_GFX_3D_CGLS |
1134 : AMD_CG_SUPPORT_GFX_CGCG |
1135 : AMD_CG_SUPPORT_GFX_CGLS |
1136 : AMD_CG_SUPPORT_GFX_CP_LS |
1137 : AMD_CG_SUPPORT_MC_MGCG |
1138 : AMD_CG_SUPPORT_MC_LS |
1139 : AMD_CG_SUPPORT_SDMA_MGCG |
1140 : AMD_CG_SUPPORT_SDMA_LS |
1141 : AMD_CG_SUPPORT_BIF_LS |
1142 : AMD_CG_SUPPORT_HDP_LS |
1143 : AMD_CG_SUPPORT_VCN_MGCG |
1144 : AMD_CG_SUPPORT_JPEG_MGCG |
1145 : AMD_CG_SUPPORT_IH_CG |
1146 : AMD_CG_SUPPORT_ATHUB_LS |
1147 : AMD_CG_SUPPORT_ATHUB_MGCG |
1148 : AMD_CG_SUPPORT_DF_MGCG;
1149 0 : adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1150 : AMD_PG_SUPPORT_VCN |
1151 : AMD_PG_SUPPORT_JPEG |
1152 : AMD_PG_SUPPORT_VCN_DPG;
1153 0 : break;
1154 : case IP_VERSION(9, 4, 2):
1155 0 : adev->asic_funcs = &vega20_asic_funcs;
1156 0 : adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1157 : AMD_CG_SUPPORT_GFX_MGLS |
1158 : AMD_CG_SUPPORT_GFX_CP_LS |
1159 : AMD_CG_SUPPORT_HDP_LS |
1160 : AMD_CG_SUPPORT_SDMA_MGCG |
1161 : AMD_CG_SUPPORT_SDMA_LS |
1162 : AMD_CG_SUPPORT_IH_CG |
1163 : AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1164 0 : adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1165 0 : adev->external_rev_id = adev->rev_id + 0x3c;
1166 0 : break;
1167 : default:
1168 : /* FIXME: not supported yet */
1169 : return -EINVAL;
1170 : }
1171 :
1172 0 : if (amdgpu_sriov_vf(adev)) {
1173 0 : amdgpu_virt_init_setting(adev);
1174 0 : xgpu_ai_mailbox_set_irq_funcs(adev);
1175 : }
1176 :
1177 : return 0;
1178 : }
1179 :
1180 0 : static int soc15_common_late_init(void *handle)
1181 : {
1182 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183 :
1184 0 : if (amdgpu_sriov_vf(adev))
1185 0 : xgpu_ai_mailbox_get_irq(adev);
1186 :
1187 0 : return 0;
1188 : }
1189 :
1190 0 : static int soc15_common_sw_init(void *handle)
1191 : {
1192 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193 :
1194 0 : if (amdgpu_sriov_vf(adev))
1195 0 : xgpu_ai_mailbox_add_irq_id(adev);
1196 :
1197 0 : if (adev->df.funcs &&
1198 0 : adev->df.funcs->sw_init)
1199 0 : adev->df.funcs->sw_init(adev);
1200 :
1201 0 : return 0;
1202 : }
1203 :
1204 0 : static int soc15_common_sw_fini(void *handle)
1205 : {
1206 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207 :
1208 0 : if (adev->df.funcs &&
1209 0 : adev->df.funcs->sw_fini)
1210 0 : adev->df.funcs->sw_fini(adev);
1211 0 : return 0;
1212 : }
1213 :
1214 0 : static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1215 : {
1216 : int i;
1217 : struct amdgpu_ring *ring;
1218 :
1219 : /* sdma/ih doorbell range are programed by hypervisor */
1220 0 : if (!amdgpu_sriov_vf(adev)) {
1221 0 : for (i = 0; i < adev->sdma.num_instances; i++) {
1222 0 : ring = &adev->sdma.instance[i].ring;
1223 0 : adev->nbio.funcs->sdma_doorbell_range(adev, i,
1224 0 : ring->use_doorbell, ring->doorbell_index,
1225 0 : adev->doorbell_index.sdma_doorbell_range);
1226 : }
1227 :
1228 0 : adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1229 0 : adev->irq.ih.doorbell_index);
1230 : }
1231 0 : }
1232 :
1233 0 : static int soc15_common_hw_init(void *handle)
1234 : {
1235 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1236 :
1237 : /* enable pcie gen2/3 link */
1238 0 : soc15_pcie_gen3_enable(adev);
1239 : /* enable aspm */
1240 0 : soc15_program_aspm(adev);
1241 : /* setup nbio registers */
1242 0 : adev->nbio.funcs->init_registers(adev);
1243 : /* remap HDP registers to a hole in mmio space,
1244 : * for the purpose of expose those registers
1245 : * to process space
1246 : */
1247 0 : if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1248 0 : adev->nbio.funcs->remap_hdp_registers(adev);
1249 :
1250 : /* enable the doorbell aperture */
1251 0 : soc15_enable_doorbell_aperture(adev, true);
1252 : /* HW doorbell routing policy: doorbell writing not
1253 : * in SDMA/IH/MM/ACV range will be routed to CP. So
1254 : * we need to init SDMA/IH/MM/ACV doorbell range prior
1255 : * to CP ip block init and ring test.
1256 : */
1257 0 : soc15_doorbell_range_init(adev);
1258 :
1259 0 : return 0;
1260 : }
1261 :
1262 0 : static int soc15_common_hw_fini(void *handle)
1263 : {
1264 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265 :
1266 : /* disable the doorbell aperture */
1267 0 : soc15_enable_doorbell_aperture(adev, false);
1268 0 : if (amdgpu_sriov_vf(adev))
1269 0 : xgpu_ai_mailbox_put_irq(adev);
1270 :
1271 0 : if (adev->nbio.ras_if &&
1272 0 : amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1273 0 : if (adev->nbio.ras &&
1274 0 : adev->nbio.ras->init_ras_controller_interrupt)
1275 0 : amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1276 0 : if (adev->nbio.ras &&
1277 0 : adev->nbio.ras->init_ras_err_event_athub_interrupt)
1278 0 : amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1279 : }
1280 :
1281 0 : return 0;
1282 : }
1283 :
1284 0 : static int soc15_common_suspend(void *handle)
1285 : {
1286 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 :
1288 0 : return soc15_common_hw_fini(adev);
1289 : }
1290 :
1291 0 : static int soc15_common_resume(void *handle)
1292 : {
1293 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294 :
1295 0 : return soc15_common_hw_init(adev);
1296 : }
1297 :
1298 0 : static bool soc15_common_is_idle(void *handle)
1299 : {
1300 0 : return true;
1301 : }
1302 :
1303 0 : static int soc15_common_wait_for_idle(void *handle)
1304 : {
1305 0 : return 0;
1306 : }
1307 :
1308 0 : static int soc15_common_soft_reset(void *handle)
1309 : {
1310 0 : return 0;
1311 : }
1312 :
1313 0 : static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1314 : {
1315 : uint32_t def, data;
1316 :
1317 0 : def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1318 :
1319 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1320 0 : data &= ~(0x01000000 |
1321 : 0x02000000 |
1322 : 0x04000000 |
1323 : 0x08000000 |
1324 : 0x10000000 |
1325 : 0x20000000 |
1326 : 0x40000000 |
1327 : 0x80000000);
1328 : else
1329 0 : data |= (0x01000000 |
1330 : 0x02000000 |
1331 : 0x04000000 |
1332 : 0x08000000 |
1333 : 0x10000000 |
1334 : 0x20000000 |
1335 : 0x40000000 |
1336 : 0x80000000);
1337 :
1338 0 : if (def != data)
1339 0 : WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1340 0 : }
1341 :
1342 0 : static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1343 : {
1344 : uint32_t def, data;
1345 :
1346 0 : def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1347 :
1348 0 : if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1349 0 : data |= 1;
1350 : else
1351 0 : data &= ~1;
1352 :
1353 0 : if (def != data)
1354 0 : WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1355 0 : }
1356 :
1357 0 : static int soc15_common_set_clockgating_state(void *handle,
1358 : enum amd_clockgating_state state)
1359 : {
1360 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1361 :
1362 0 : if (amdgpu_sriov_vf(adev))
1363 : return 0;
1364 :
1365 0 : switch (adev->ip_versions[NBIO_HWIP][0]) {
1366 : case IP_VERSION(6, 1, 0):
1367 : case IP_VERSION(6, 2, 0):
1368 : case IP_VERSION(7, 4, 0):
1369 0 : adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1370 : state == AMD_CG_STATE_GATE);
1371 0 : adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1372 : state == AMD_CG_STATE_GATE);
1373 0 : adev->hdp.funcs->update_clock_gating(adev,
1374 : state == AMD_CG_STATE_GATE);
1375 0 : soc15_update_drm_clock_gating(adev,
1376 : state == AMD_CG_STATE_GATE);
1377 0 : soc15_update_drm_light_sleep(adev,
1378 : state == AMD_CG_STATE_GATE);
1379 0 : adev->smuio.funcs->update_rom_clock_gating(adev,
1380 : state == AMD_CG_STATE_GATE);
1381 0 : adev->df.funcs->update_medium_grain_clock_gating(adev,
1382 : state == AMD_CG_STATE_GATE);
1383 0 : break;
1384 : case IP_VERSION(7, 0, 0):
1385 : case IP_VERSION(7, 0, 1):
1386 : case IP_VERSION(2, 5, 0):
1387 0 : adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1388 : state == AMD_CG_STATE_GATE);
1389 0 : adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1390 : state == AMD_CG_STATE_GATE);
1391 0 : adev->hdp.funcs->update_clock_gating(adev,
1392 : state == AMD_CG_STATE_GATE);
1393 0 : soc15_update_drm_clock_gating(adev,
1394 : state == AMD_CG_STATE_GATE);
1395 0 : soc15_update_drm_light_sleep(adev,
1396 : state == AMD_CG_STATE_GATE);
1397 0 : break;
1398 : case IP_VERSION(7, 4, 1):
1399 : case IP_VERSION(7, 4, 4):
1400 0 : adev->hdp.funcs->update_clock_gating(adev,
1401 : state == AMD_CG_STATE_GATE);
1402 0 : break;
1403 : default:
1404 : break;
1405 : }
1406 : return 0;
1407 : }
1408 :
1409 0 : static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1410 : {
1411 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412 : int data;
1413 :
1414 0 : if (amdgpu_sriov_vf(adev))
1415 0 : *flags = 0;
1416 :
1417 0 : adev->nbio.funcs->get_clockgating_state(adev, flags);
1418 :
1419 0 : adev->hdp.funcs->get_clock_gating_state(adev, flags);
1420 :
1421 0 : if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1422 :
1423 : /* AMD_CG_SUPPORT_DRM_MGCG */
1424 0 : data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1425 0 : if (!(data & 0x01000000))
1426 0 : *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1427 :
1428 : /* AMD_CG_SUPPORT_DRM_LS */
1429 0 : data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1430 0 : if (data & 0x1)
1431 0 : *flags |= AMD_CG_SUPPORT_DRM_LS;
1432 : }
1433 :
1434 : /* AMD_CG_SUPPORT_ROM_MGCG */
1435 0 : adev->smuio.funcs->get_clock_gating_state(adev, flags);
1436 :
1437 0 : adev->df.funcs->get_clockgating_state(adev, flags);
1438 0 : }
1439 :
1440 0 : static int soc15_common_set_powergating_state(void *handle,
1441 : enum amd_powergating_state state)
1442 : {
1443 : /* todo */
1444 0 : return 0;
1445 : }
1446 :
1447 : static const struct amd_ip_funcs soc15_common_ip_funcs = {
1448 : .name = "soc15_common",
1449 : .early_init = soc15_common_early_init,
1450 : .late_init = soc15_common_late_init,
1451 : .sw_init = soc15_common_sw_init,
1452 : .sw_fini = soc15_common_sw_fini,
1453 : .hw_init = soc15_common_hw_init,
1454 : .hw_fini = soc15_common_hw_fini,
1455 : .suspend = soc15_common_suspend,
1456 : .resume = soc15_common_resume,
1457 : .is_idle = soc15_common_is_idle,
1458 : .wait_for_idle = soc15_common_wait_for_idle,
1459 : .soft_reset = soc15_common_soft_reset,
1460 : .set_clockgating_state = soc15_common_set_clockgating_state,
1461 : .set_powergating_state = soc15_common_set_powergating_state,
1462 : .get_clockgating_state= soc15_common_get_clockgating_state,
1463 : };
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