Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <linux/pci.h>
25 :
26 : #include "amdgpu.h"
27 : #include "amdgpu_ih.h"
28 : #include "soc15.h"
29 :
30 : #include "oss/osssys_4_2_0_offset.h"
31 : #include "oss/osssys_4_2_0_sh_mask.h"
32 :
33 : #include "soc15_common.h"
34 : #include "vega20_ih.h"
35 :
36 : #define MAX_REARM_RETRY 10
37 :
38 : #define mmIH_CHICKEN_ALDEBARAN 0x18d
39 : #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40 :
41 : static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
42 :
43 : /**
44 : * vega20_ih_init_register_offset - Initialize register offset for ih rings
45 : *
46 : * @adev: amdgpu_device pointer
47 : *
48 : * Initialize register offset ih rings (VEGA20).
49 : */
50 0 : static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
51 : {
52 : struct amdgpu_ih_regs *ih_regs;
53 :
54 0 : if (adev->irq.ih.ring_size) {
55 0 : ih_regs = &adev->irq.ih.ih_regs;
56 0 : ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
57 0 : ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
58 0 : ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
59 0 : ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
60 0 : ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
61 0 : ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
62 0 : ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
63 0 : ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
64 0 : ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
65 : }
66 :
67 0 : if (adev->irq.ih1.ring_size) {
68 0 : ih_regs = &adev->irq.ih1.ih_regs;
69 0 : ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
70 0 : ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
71 0 : ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
72 0 : ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
73 0 : ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
74 0 : ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
75 0 : ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
76 : }
77 :
78 0 : if (adev->irq.ih2.ring_size) {
79 0 : ih_regs = &adev->irq.ih2.ih_regs;
80 0 : ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
81 0 : ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
82 0 : ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
83 0 : ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
84 0 : ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
85 0 : ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
86 0 : ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
87 : }
88 0 : }
89 :
90 : /**
91 : * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
92 : *
93 : * @adev: amdgpu_device pointer
94 : * @ih: amdgpu_ih_ring pointer
95 : * @enable: true - enable the interrupts, false - disable the interrupts
96 : *
97 : * Toggle the interrupt ring buffer (VEGA20)
98 : */
99 0 : static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
100 : struct amdgpu_ih_ring *ih,
101 : bool enable)
102 : {
103 : struct amdgpu_ih_regs *ih_regs;
104 : uint32_t tmp;
105 :
106 0 : ih_regs = &ih->ih_regs;
107 :
108 0 : tmp = RREG32(ih_regs->ih_rb_cntl);
109 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
110 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
111 :
112 : /* enable_intr field is only valid in ring0 */
113 0 : if (ih == &adev->irq.ih)
114 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
115 0 : if (amdgpu_sriov_vf(adev)) {
116 0 : if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
117 0 : dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
118 0 : return -ETIMEDOUT;
119 : }
120 : } else {
121 0 : WREG32(ih_regs->ih_rb_cntl, tmp);
122 : }
123 :
124 0 : if (enable) {
125 0 : ih->enabled = true;
126 : } else {
127 : /* set rptr, wptr to 0 */
128 0 : WREG32(ih_regs->ih_rb_rptr, 0);
129 0 : WREG32(ih_regs->ih_rb_wptr, 0);
130 0 : ih->enabled = false;
131 0 : ih->rptr = 0;
132 : }
133 :
134 : return 0;
135 : }
136 :
137 : /**
138 : * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
139 : *
140 : * @adev: amdgpu_device pointer
141 : * @enable: enable or disable interrupt ring buffers
142 : *
143 : * Toggle all the available interrupt ring buffers (VEGA20).
144 : */
145 0 : static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
146 : {
147 0 : struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
148 : int i;
149 : int r;
150 :
151 0 : for (i = 0; i < ARRAY_SIZE(ih); i++) {
152 0 : if (ih[i]->ring_size) {
153 0 : r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
154 0 : if (r)
155 : return r;
156 : }
157 : }
158 :
159 : return 0;
160 : }
161 :
162 0 : static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
163 : {
164 0 : int rb_bufsz = order_base_2(ih->ring_size / 4);
165 :
166 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
167 : MC_SPACE, ih->use_bus_addr ? 1 : 4);
168 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
169 : WPTR_OVERFLOW_CLEAR, 1);
170 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
171 : WPTR_OVERFLOW_ENABLE, 1);
172 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
173 : /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
174 : * value is written to memory
175 : */
176 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
177 : WPTR_WRITEBACK_ENABLE, 1);
178 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
179 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
180 0 : ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
181 :
182 0 : return ih_rb_cntl;
183 : }
184 :
185 : static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
186 : {
187 0 : u32 ih_doorbell_rtpr = 0;
188 :
189 0 : if (ih->use_doorbell) {
190 0 : ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
191 : IH_DOORBELL_RPTR, OFFSET,
192 : ih->doorbell_index);
193 0 : ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
194 : IH_DOORBELL_RPTR,
195 : ENABLE, 1);
196 : } else {
197 : ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
198 : IH_DOORBELL_RPTR,
199 : ENABLE, 0);
200 : }
201 : return ih_doorbell_rtpr;
202 : }
203 :
204 : /**
205 : * vega20_ih_enable_ring - enable an ih ring buffer
206 : *
207 : * @adev: amdgpu_device pointer
208 : * @ih: amdgpu_ih_ring pointer
209 : *
210 : * Enable an ih ring buffer (VEGA20)
211 : */
212 0 : static int vega20_ih_enable_ring(struct amdgpu_device *adev,
213 : struct amdgpu_ih_ring *ih)
214 : {
215 : struct amdgpu_ih_regs *ih_regs;
216 : uint32_t tmp;
217 :
218 0 : ih_regs = &ih->ih_regs;
219 :
220 : /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
221 0 : WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
222 0 : WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
223 :
224 0 : tmp = RREG32(ih_regs->ih_rb_cntl);
225 0 : tmp = vega20_ih_rb_cntl(ih, tmp);
226 0 : if (ih == &adev->irq.ih)
227 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
228 0 : if (ih == &adev->irq.ih1)
229 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
230 0 : if (amdgpu_sriov_vf(adev)) {
231 0 : if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
232 0 : dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
233 0 : return -ETIMEDOUT;
234 : }
235 : } else {
236 0 : WREG32(ih_regs->ih_rb_cntl, tmp);
237 : }
238 :
239 0 : if (ih == &adev->irq.ih) {
240 : /* set the ih ring 0 writeback address whether it's enabled or not */
241 0 : WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
242 0 : WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
243 : }
244 :
245 : /* set rptr, wptr to 0 */
246 0 : WREG32(ih_regs->ih_rb_wptr, 0);
247 0 : WREG32(ih_regs->ih_rb_rptr, 0);
248 :
249 0 : WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
250 :
251 0 : return 0;
252 : }
253 :
254 : /**
255 : * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
256 : *
257 : * @adev: amdgpu_device pointer
258 : *
259 : * Reroute VMC and UMC interrupts on primary ih ring to
260 : * ih ring 1 so they won't lose when bunches of page faults
261 : * interrupts overwhelms the interrupt handler(VEGA20)
262 : */
263 0 : static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
264 : {
265 : uint32_t tmp;
266 :
267 : /* vega20 ih reroute will go through psp this
268 : * function is used for newer asics starting arcturus
269 : */
270 0 : if (adev->asic_type >= CHIP_ARCTURUS) {
271 : /* Reroute to IH ring 1 for VMC */
272 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
273 0 : tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
274 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
275 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
276 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
277 :
278 : /* Reroute IH ring 1 for UTCL2 */
279 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
280 0 : tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
281 0 : tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
282 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
283 : }
284 0 : }
285 :
286 : /**
287 : * vega20_ih_irq_init - init and enable the interrupt ring
288 : *
289 : * @adev: amdgpu_device pointer
290 : *
291 : * Allocate a ring buffer for the interrupt controller,
292 : * enable the RLC, disable interrupts, enable the IH
293 : * ring buffer and enable it (VI).
294 : * Called at device load and reume.
295 : * Returns 0 for success, errors for failure.
296 : */
297 0 : static int vega20_ih_irq_init(struct amdgpu_device *adev)
298 : {
299 0 : struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
300 : u32 ih_chicken;
301 : int ret;
302 : int i;
303 :
304 : /* disable irqs */
305 0 : ret = vega20_ih_toggle_interrupts(adev, false);
306 0 : if (ret)
307 : return ret;
308 :
309 0 : adev->nbio.funcs->ih_control(adev);
310 :
311 0 : if (adev->asic_type == CHIP_ARCTURUS &&
312 0 : adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
313 0 : ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
314 0 : if (adev->irq.ih.use_bus_addr) {
315 0 : ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
316 : MC_SPACE_GPA_ENABLE, 1);
317 : }
318 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
319 : }
320 :
321 : /* psp firmware won't program IH_CHICKEN for aldebaran
322 : * driver needs to program it properly according to
323 : * MC_SPACE type in IH_RB_CNTL */
324 0 : if (adev->asic_type == CHIP_ALDEBARAN) {
325 0 : ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
326 0 : if (adev->irq.ih.use_bus_addr) {
327 0 : ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
328 : MC_SPACE_GPA_ENABLE, 1);
329 : }
330 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
331 : }
332 :
333 0 : for (i = 0; i < ARRAY_SIZE(ih); i++) {
334 0 : if (ih[i]->ring_size) {
335 0 : if (i == 1)
336 0 : vega20_ih_reroute_ih(adev);
337 0 : ret = vega20_ih_enable_ring(adev, ih[i]);
338 0 : if (ret)
339 : return ret;
340 : }
341 : }
342 :
343 0 : pci_set_master(adev->pdev);
344 :
345 : /* enable interrupts */
346 0 : ret = vega20_ih_toggle_interrupts(adev, true);
347 0 : if (ret)
348 : return ret;
349 :
350 0 : if (adev->irq.ih_soft.ring_size)
351 0 : adev->irq.ih_soft.enabled = true;
352 :
353 : return 0;
354 : }
355 :
356 : /**
357 : * vega20_ih_irq_disable - disable interrupts
358 : *
359 : * @adev: amdgpu_device pointer
360 : *
361 : * Disable interrupts on the hw (VEGA20).
362 : */
363 : static void vega20_ih_irq_disable(struct amdgpu_device *adev)
364 : {
365 0 : vega20_ih_toggle_interrupts(adev, false);
366 :
367 : /* Wait and acknowledge irq */
368 0 : mdelay(1);
369 : }
370 :
371 : /**
372 : * vega20_ih_get_wptr - get the IH ring buffer wptr
373 : *
374 : * @adev: amdgpu_device pointer
375 : * @ih: amdgpu_ih_ring pointer
376 : *
377 : * Get the IH ring buffer wptr from either the register
378 : * or the writeback memory buffer (VEGA20). Also check for
379 : * ring buffer overflow and deal with it.
380 : * Returns the value of the wptr.
381 : */
382 0 : static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
383 : struct amdgpu_ih_ring *ih)
384 : {
385 : u32 wptr, tmp;
386 : struct amdgpu_ih_regs *ih_regs;
387 :
388 0 : if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
389 : /* Only ring0 supports writeback. On other rings fall back
390 : * to register-based code with overflow checking below.
391 : * ih_soft ring doesn't have any backing hardware registers,
392 : * update wptr and return.
393 : */
394 0 : wptr = le32_to_cpu(*ih->wptr_cpu);
395 :
396 0 : if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
397 : goto out;
398 : }
399 :
400 0 : ih_regs = &ih->ih_regs;
401 :
402 : /* Double check that the overflow wasn't already cleared. */
403 0 : wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
404 0 : if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
405 : goto out;
406 :
407 0 : wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
408 :
409 : /* When a ring buffer overflow happen start parsing interrupt
410 : * from the last not overwritten vector (wptr + 32). Hopefully
411 : * this should allow us to catchup.
412 : */
413 0 : tmp = (wptr + 32) & ih->ptr_mask;
414 0 : dev_warn(adev->dev, "IH ring buffer overflow "
415 : "(0x%08X, 0x%08X, 0x%08X)\n",
416 : wptr, ih->rptr, tmp);
417 0 : ih->rptr = tmp;
418 :
419 0 : tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
420 0 : tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
421 0 : WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
422 :
423 : out:
424 0 : return (wptr & ih->ptr_mask);
425 : }
426 :
427 : /**
428 : * vega20_ih_irq_rearm - rearm IRQ if lost
429 : *
430 : * @adev: amdgpu_device pointer
431 : * @ih: amdgpu_ih_ring pointer
432 : *
433 : */
434 0 : static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
435 : struct amdgpu_ih_ring *ih)
436 : {
437 0 : uint32_t v = 0;
438 0 : uint32_t i = 0;
439 : struct amdgpu_ih_regs *ih_regs;
440 :
441 0 : ih_regs = &ih->ih_regs;
442 :
443 : /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
444 0 : for (i = 0; i < MAX_REARM_RETRY; i++) {
445 0 : v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
446 0 : if ((v < ih->ring_size) && (v != ih->rptr))
447 0 : WDOORBELL32(ih->doorbell_index, ih->rptr);
448 : else
449 : break;
450 : }
451 0 : }
452 :
453 : /**
454 : * vega20_ih_set_rptr - set the IH ring buffer rptr
455 : *
456 : * @adev: amdgpu_device pointer
457 : * @ih: amdgpu_ih_ring pointer
458 : *
459 : * Set the IH ring buffer rptr.
460 : */
461 0 : static void vega20_ih_set_rptr(struct amdgpu_device *adev,
462 : struct amdgpu_ih_ring *ih)
463 : {
464 : struct amdgpu_ih_regs *ih_regs;
465 :
466 0 : if (ih == &adev->irq.ih_soft)
467 : return;
468 :
469 0 : if (ih->use_doorbell) {
470 : /* XXX check if swapping is necessary on BE */
471 0 : *ih->rptr_cpu = ih->rptr;
472 0 : WDOORBELL32(ih->doorbell_index, ih->rptr);
473 :
474 0 : if (amdgpu_sriov_vf(adev))
475 0 : vega20_ih_irq_rearm(adev, ih);
476 : } else {
477 0 : ih_regs = &ih->ih_regs;
478 0 : WREG32(ih_regs->ih_rb_rptr, ih->rptr);
479 : }
480 : }
481 :
482 : /**
483 : * vega20_ih_self_irq - dispatch work for ring 1 and 2
484 : *
485 : * @adev: amdgpu_device pointer
486 : * @source: irq source
487 : * @entry: IV with WPTR update
488 : *
489 : * Update the WPTR from the IV and schedule work to handle the entries.
490 : */
491 0 : static int vega20_ih_self_irq(struct amdgpu_device *adev,
492 : struct amdgpu_irq_src *source,
493 : struct amdgpu_iv_entry *entry)
494 : {
495 0 : switch (entry->ring_id) {
496 : case 1:
497 0 : schedule_work(&adev->irq.ih1_work);
498 : break;
499 : case 2:
500 0 : schedule_work(&adev->irq.ih2_work);
501 : break;
502 : default: break;
503 : }
504 0 : return 0;
505 : }
506 :
507 : static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
508 : .process = vega20_ih_self_irq,
509 : };
510 :
511 : static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
512 : {
513 0 : adev->irq.self_irq.num_types = 0;
514 0 : adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
515 : }
516 :
517 0 : static int vega20_ih_early_init(void *handle)
518 : {
519 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
520 :
521 0 : vega20_ih_set_interrupt_funcs(adev);
522 0 : vega20_ih_set_self_irq_funcs(adev);
523 0 : return 0;
524 : }
525 :
526 0 : static int vega20_ih_sw_init(void *handle)
527 : {
528 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
529 : int r;
530 :
531 0 : r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
532 : &adev->irq.self_irq);
533 0 : if (r)
534 : return r;
535 :
536 0 : r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
537 0 : if (r)
538 : return r;
539 :
540 0 : adev->irq.ih.use_doorbell = true;
541 0 : adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
542 :
543 0 : r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
544 0 : if (r)
545 : return r;
546 :
547 0 : adev->irq.ih1.use_doorbell = true;
548 0 : adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
549 :
550 0 : r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
551 0 : if (r)
552 : return r;
553 :
554 0 : adev->irq.ih2.use_doorbell = true;
555 0 : adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
556 :
557 : /* initialize ih control registers offset */
558 0 : vega20_ih_init_register_offset(adev);
559 :
560 0 : r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
561 0 : if (r)
562 : return r;
563 :
564 0 : r = amdgpu_irq_init(adev);
565 :
566 0 : return r;
567 : }
568 :
569 0 : static int vega20_ih_sw_fini(void *handle)
570 : {
571 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572 :
573 0 : amdgpu_irq_fini_sw(adev);
574 :
575 0 : return 0;
576 : }
577 :
578 0 : static int vega20_ih_hw_init(void *handle)
579 : {
580 : int r;
581 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
582 :
583 0 : r = vega20_ih_irq_init(adev);
584 0 : if (r)
585 : return r;
586 :
587 0 : return 0;
588 : }
589 :
590 0 : static int vega20_ih_hw_fini(void *handle)
591 : {
592 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
593 :
594 0 : vega20_ih_irq_disable(adev);
595 :
596 0 : return 0;
597 : }
598 :
599 0 : static int vega20_ih_suspend(void *handle)
600 : {
601 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
602 :
603 0 : return vega20_ih_hw_fini(adev);
604 : }
605 :
606 0 : static int vega20_ih_resume(void *handle)
607 : {
608 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609 :
610 0 : return vega20_ih_hw_init(adev);
611 : }
612 :
613 0 : static bool vega20_ih_is_idle(void *handle)
614 : {
615 : /* todo */
616 0 : return true;
617 : }
618 :
619 0 : static int vega20_ih_wait_for_idle(void *handle)
620 : {
621 : /* todo */
622 0 : return -ETIMEDOUT;
623 : }
624 :
625 0 : static int vega20_ih_soft_reset(void *handle)
626 : {
627 : /* todo */
628 :
629 0 : return 0;
630 : }
631 :
632 0 : static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
633 : bool enable)
634 : {
635 : uint32_t data, def, field_val;
636 :
637 0 : if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
638 0 : def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
639 0 : field_val = enable ? 0 : 1;
640 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
641 : IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
642 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
643 : IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
644 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
645 : DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
646 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
647 : OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
648 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
649 : LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
650 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
651 : DYN_CLK_SOFT_OVERRIDE, field_val);
652 0 : data = REG_SET_FIELD(data, IH_CLK_CTRL,
653 : REG_CLK_SOFT_OVERRIDE, field_val);
654 0 : if (def != data)
655 0 : WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
656 : }
657 0 : }
658 :
659 0 : static int vega20_ih_set_clockgating_state(void *handle,
660 : enum amd_clockgating_state state)
661 : {
662 0 : struct amdgpu_device *adev = (struct amdgpu_device *)handle;
663 :
664 0 : vega20_ih_update_clockgating_state(adev,
665 : state == AMD_CG_STATE_GATE);
666 0 : return 0;
667 :
668 : }
669 :
670 0 : static int vega20_ih_set_powergating_state(void *handle,
671 : enum amd_powergating_state state)
672 : {
673 0 : return 0;
674 : }
675 :
676 : const struct amd_ip_funcs vega20_ih_ip_funcs = {
677 : .name = "vega20_ih",
678 : .early_init = vega20_ih_early_init,
679 : .late_init = NULL,
680 : .sw_init = vega20_ih_sw_init,
681 : .sw_fini = vega20_ih_sw_fini,
682 : .hw_init = vega20_ih_hw_init,
683 : .hw_fini = vega20_ih_hw_fini,
684 : .suspend = vega20_ih_suspend,
685 : .resume = vega20_ih_resume,
686 : .is_idle = vega20_ih_is_idle,
687 : .wait_for_idle = vega20_ih_wait_for_idle,
688 : .soft_reset = vega20_ih_soft_reset,
689 : .set_clockgating_state = vega20_ih_set_clockgating_state,
690 : .set_powergating_state = vega20_ih_set_powergating_state,
691 : };
692 :
693 : static const struct amdgpu_ih_funcs vega20_ih_funcs = {
694 : .get_wptr = vega20_ih_get_wptr,
695 : .decode_iv = amdgpu_ih_decode_iv_helper,
696 : .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
697 : .set_rptr = vega20_ih_set_rptr
698 : };
699 :
700 : static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
701 : {
702 0 : adev->irq.ih_funcs = &vega20_ih_funcs;
703 : }
704 :
705 : const struct amdgpu_ip_block_version vega20_ih_ip_block =
706 : {
707 : .type = AMD_IP_BLOCK_TYPE_IH,
708 : .major = 4,
709 : .minor = 2,
710 : .rev = 0,
711 : .funcs = &vega20_ih_ip_funcs,
712 : };
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