Line data Source code
1 : /*
2 : * Copyright 2012-16 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "core_types.h"
27 : #include "link_encoder.h"
28 : #include "dce_dmcu.h"
29 : #include "dm_services.h"
30 : #include "reg_helper.h"
31 : #include "fixed31_32.h"
32 : #include "dc.h"
33 :
34 : #define TO_DCE_DMCU(dmcu)\
35 : container_of(dmcu, struct dce_dmcu, base)
36 :
37 : #define REG(reg) \
38 : (dmcu_dce->regs->reg)
39 :
40 : #undef FN
41 : #define FN(reg_name, field_name) \
42 : dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
43 :
44 : #define CTX \
45 : dmcu_dce->base.ctx
46 :
47 : /* PSR related commands */
48 : #define PSR_ENABLE 0x20
49 : #define PSR_EXIT 0x21
50 : #define PSR_SET 0x23
51 : #define PSR_SET_WAITLOOP 0x31
52 : #define MCP_INIT_DMCU 0x88
53 : #define MCP_INIT_IRAM 0x89
54 : #define MCP_SYNC_PHY_LOCK 0x90
55 : #define MCP_SYNC_PHY_UNLOCK 0x91
56 : #define MCP_BL_SET_PWM_FRAC 0x6A /* Enable or disable Fractional PWM */
57 : #define CRC_WIN_NOTIFY 0x92
58 : #define CRC_STOP_UPDATE 0x93
59 : #define MCP_SEND_EDID_CEA 0xA0
60 : #define EDID_CEA_CMD_ACK 1
61 : #define EDID_CEA_CMD_NACK 2
62 : #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L
63 :
64 : // PSP FW version
65 : #define mmMP0_SMN_C2PMSG_58 0x1607A
66 :
67 : //Register access policy version
68 : #define mmMP0_SMN_C2PMSG_91 0x1609B
69 :
70 : static const uint32_t abm_gain_stepsize = 0x0060;
71 :
72 0 : static bool dce_dmcu_init(struct dmcu *dmcu)
73 : {
74 : // Do nothing
75 0 : return true;
76 : }
77 :
78 0 : static bool dce_dmcu_load_iram(struct dmcu *dmcu,
79 : unsigned int start_offset,
80 : const char *src,
81 : unsigned int bytes)
82 : {
83 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
84 0 : unsigned int count = 0;
85 :
86 : /* Enable write access to IRAM */
87 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
88 : IRAM_HOST_ACCESS_EN, 1,
89 : IRAM_WR_ADDR_AUTO_INC, 1);
90 :
91 0 : REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
92 :
93 0 : REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
94 :
95 0 : for (count = 0; count < bytes; count++)
96 0 : REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
97 :
98 : /* Disable write access to IRAM to allow dynamic sleep state */
99 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
100 : IRAM_HOST_ACCESS_EN, 0,
101 : IRAM_WR_ADDR_AUTO_INC, 0);
102 :
103 0 : return true;
104 : }
105 :
106 0 : static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)
107 : {
108 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
109 :
110 0 : uint32_t psr_state_offset = 0xf0;
111 :
112 : /* Enable write access to IRAM */
113 0 : REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
114 :
115 0 : REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
116 :
117 : /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
118 0 : REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
119 :
120 : /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
121 0 : *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
122 :
123 : /* Disable write access to IRAM after finished using IRAM
124 : * in order to allow dynamic sleep state
125 : */
126 0 : REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
127 0 : }
128 :
129 0 : static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
130 : {
131 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
132 0 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
133 0 : unsigned int dmcu_wait_reg_ready_interval = 100;
134 :
135 : unsigned int retryCount;
136 0 : enum dc_psr_state state = PSR_STATE0;
137 :
138 : /* waitDMCUReadyForCmd */
139 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
140 : dmcu_wait_reg_ready_interval,
141 : dmcu_max_retry_on_wait_reg_ready);
142 :
143 : /* setDMCUParam_Cmd */
144 0 : if (enable)
145 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
146 : PSR_ENABLE);
147 : else
148 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
149 : PSR_EXIT);
150 :
151 : /* notifyDMCUMsg */
152 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
153 0 : if (wait == true) {
154 0 : for (retryCount = 0; retryCount <= 100; retryCount++) {
155 0 : dce_get_dmcu_psr_state(dmcu, &state);
156 0 : if (enable) {
157 0 : if (state != PSR_STATE0)
158 : break;
159 : } else {
160 0 : if (state == PSR_STATE0)
161 : break;
162 : }
163 0 : udelay(10);
164 : }
165 : }
166 0 : }
167 :
168 0 : static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
169 : struct dc_link *link,
170 : struct psr_context *psr_context)
171 : {
172 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
173 :
174 0 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
175 0 : unsigned int dmcu_wait_reg_ready_interval = 100;
176 :
177 : union dce_dmcu_psr_config_data_reg1 masterCmdData1;
178 : union dce_dmcu_psr_config_data_reg2 masterCmdData2;
179 : union dce_dmcu_psr_config_data_reg3 masterCmdData3;
180 :
181 0 : link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
182 0 : psr_context->psrExitLinkTrainingRequired);
183 :
184 : /* Enable static screen interrupts for PSR supported display */
185 : /* Disable the interrupt coming from other displays. */
186 0 : REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
187 : STATIC_SCREEN1_INT_TO_UC_EN, 0,
188 : STATIC_SCREEN2_INT_TO_UC_EN, 0,
189 : STATIC_SCREEN3_INT_TO_UC_EN, 0,
190 : STATIC_SCREEN4_INT_TO_UC_EN, 0);
191 :
192 0 : switch (psr_context->controllerId) {
193 : /* Driver uses case 1 for unconfigured */
194 : case 1:
195 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
196 : STATIC_SCREEN1_INT_TO_UC_EN, 1);
197 0 : break;
198 : case 2:
199 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
200 : STATIC_SCREEN2_INT_TO_UC_EN, 1);
201 0 : break;
202 : case 3:
203 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
204 : STATIC_SCREEN3_INT_TO_UC_EN, 1);
205 0 : break;
206 : case 4:
207 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
208 : STATIC_SCREEN4_INT_TO_UC_EN, 1);
209 0 : break;
210 : case 5:
211 : /* CZ/NL only has 4 CRTC!!
212 : * really valid.
213 : * There is no interrupt enable mask for these instances.
214 : */
215 : break;
216 : case 6:
217 : /* CZ/NL only has 4 CRTC!!
218 : * These are here because they are defined in HW regspec,
219 : * but not really valid. There is no interrupt enable mask
220 : * for these instances.
221 : */
222 : break;
223 : default:
224 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
225 : STATIC_SCREEN1_INT_TO_UC_EN, 1);
226 0 : break;
227 : }
228 :
229 0 : link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
230 : psr_context->sdpTransmitLineNumDeadline);
231 :
232 : /* waitDMCUReadyForCmd */
233 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
234 : dmcu_wait_reg_ready_interval,
235 : dmcu_max_retry_on_wait_reg_ready);
236 :
237 : /* setDMCUParam_PSRHostConfigData */
238 0 : masterCmdData1.u32All = 0;
239 0 : masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
240 0 : masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
241 0 : masterCmdData1.bits.rfb_update_auto_en =
242 0 : psr_context->rfb_update_auto_en;
243 0 : masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
244 0 : masterCmdData1.bits.dcp_sel = psr_context->controllerId;
245 0 : masterCmdData1.bits.phy_type = psr_context->phyType;
246 0 : masterCmdData1.bits.frame_cap_ind =
247 0 : psr_context->psrFrameCaptureIndicationReq;
248 0 : masterCmdData1.bits.aux_chan = psr_context->channel;
249 0 : masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
250 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
251 : masterCmdData1.u32All);
252 :
253 0 : masterCmdData2.u32All = 0;
254 0 : masterCmdData2.bits.dig_fe = psr_context->engineId;
255 0 : masterCmdData2.bits.dig_be = psr_context->transmitterId;
256 0 : masterCmdData2.bits.skip_wait_for_pll_lock =
257 0 : psr_context->skipPsrWaitForPllLock;
258 0 : masterCmdData2.bits.frame_delay = psr_context->frame_delay;
259 0 : masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
260 0 : masterCmdData2.bits.num_of_controllers =
261 0 : psr_context->numberOfControllers;
262 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
263 : masterCmdData2.u32All);
264 :
265 0 : masterCmdData3.u32All = 0;
266 0 : masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
267 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
268 : masterCmdData3.u32All);
269 :
270 : /* setDMCUParam_Cmd */
271 0 : REG_UPDATE(MASTER_COMM_CMD_REG,
272 : MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
273 :
274 : /* notifyDMCUMsg */
275 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
276 :
277 0 : return true;
278 : }
279 :
280 0 : static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
281 : {
282 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
283 : unsigned int dmcu_uc_reset;
284 :
285 : /* microcontroller is not running */
286 0 : REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
287 :
288 : /* DMCU is not running */
289 0 : if (dmcu_uc_reset)
290 : return false;
291 :
292 0 : return true;
293 : }
294 :
295 0 : static void dce_psr_wait_loop(
296 : struct dmcu *dmcu,
297 : unsigned int wait_loop_number)
298 : {
299 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
300 : union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
301 :
302 0 : if (dmcu->cached_wait_loop_number == wait_loop_number)
303 0 : return;
304 :
305 : /* DMCU is not running */
306 0 : if (!dce_is_dmcu_initialized(dmcu))
307 : return;
308 :
309 : /* waitDMCUReadyForCmd */
310 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
311 :
312 0 : masterCmdData1.u32 = 0;
313 0 : masterCmdData1.bits.wait_loop = wait_loop_number;
314 0 : dmcu->cached_wait_loop_number = wait_loop_number;
315 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
316 :
317 : /* setDMCUParam_Cmd */
318 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
319 :
320 : /* notifyDMCUMsg */
321 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
322 : }
323 :
324 0 : static void dce_get_psr_wait_loop(
325 : struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
326 : {
327 0 : *psr_wait_loop_number = dmcu->cached_wait_loop_number;
328 0 : return;
329 : }
330 :
331 0 : static void dcn10_get_dmcu_version(struct dmcu *dmcu)
332 : {
333 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
334 0 : uint32_t dmcu_version_offset = 0xf1;
335 :
336 : /* Enable write access to IRAM */
337 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
338 : IRAM_HOST_ACCESS_EN, 1,
339 : IRAM_RD_ADDR_AUTO_INC, 1);
340 :
341 0 : REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
342 :
343 : /* Write address to IRAM_RD_ADDR and read from DATA register */
344 0 : REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
345 0 : dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
346 0 : dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
347 0 : dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
348 0 : dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
349 0 : REG_READ(DMCU_IRAM_RD_DATA));
350 :
351 : /* Disable write access to IRAM to allow dynamic sleep state */
352 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
353 : IRAM_HOST_ACCESS_EN, 0,
354 : IRAM_RD_ADDR_AUTO_INC, 0);
355 0 : }
356 :
357 0 : static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,
358 : uint32_t fractional_pwm)
359 : {
360 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
361 :
362 : /* Wait until microcontroller is ready to process interrupt */
363 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
364 :
365 : /* Set PWM fractional enable/disable */
366 0 : REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
367 :
368 : /* Set command to enable or disable fractional PWM microcontroller */
369 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
370 : MCP_BL_SET_PWM_FRAC);
371 :
372 : /* Notify microcontroller of new command */
373 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
374 :
375 : /* Ensure command has been executed before continuing */
376 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
377 0 : }
378 :
379 0 : static bool dcn10_dmcu_init(struct dmcu *dmcu)
380 : {
381 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
382 0 : const struct dc_config *config = &dmcu->ctx->dc->config;
383 0 : bool status = false;
384 0 : struct dc_context *ctx = dmcu->ctx;
385 : unsigned int i;
386 : // 5 4 3 2 1 0
387 : // F E D C B A - bit 0 is A, bit 5 is F
388 0 : unsigned int tx_interrupt_mask = 0;
389 :
390 0 : PERF_TRACE();
391 : /* Definition of DC_DMCU_SCRATCH
392 : * 0 : firmare not loaded
393 : * 1 : PSP load DMCU FW but not initialized
394 : * 2 : Firmware already initialized
395 : */
396 0 : dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
397 :
398 0 : for (i = 0; i < ctx->dc->link_count; i++) {
399 0 : if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) {
400 0 : if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A &&
401 : ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) {
402 0 : tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter;
403 : }
404 : }
405 : }
406 :
407 0 : switch (dmcu->dmcu_state) {
408 : case DMCU_UNLOADED:
409 : status = false;
410 : break;
411 : case DMCU_LOADED_UNINITIALIZED:
412 : /* Wait until microcontroller is ready to process interrupt */
413 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
414 :
415 : /* Set initialized ramping boundary value */
416 0 : REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
417 :
418 : /* Set backlight ramping stepsize */
419 0 : REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
420 :
421 0 : REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask);
422 :
423 : /* Set command to initialize microcontroller */
424 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
425 : MCP_INIT_DMCU);
426 :
427 : /* Notify microcontroller of new command */
428 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
429 :
430 : /* Ensure command has been executed before continuing */
431 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
432 :
433 : // Check state is initialized
434 0 : dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
435 :
436 : // If microcontroller is not in running state, fail
437 0 : if (dmcu->dmcu_state == DMCU_RUNNING) {
438 : /* Retrieve and cache the DMCU firmware version. */
439 0 : dcn10_get_dmcu_version(dmcu);
440 :
441 : /* Initialize DMCU to use fractional PWM or not */
442 0 : dcn10_dmcu_enable_fractional_pwm(dmcu,
443 0 : (config->disable_fractional_pwm == false) ? 1 : 0);
444 0 : status = true;
445 : } else {
446 : status = false;
447 : }
448 :
449 : break;
450 : case DMCU_RUNNING:
451 0 : status = true;
452 0 : break;
453 : default:
454 : status = false;
455 : break;
456 : }
457 :
458 0 : PERF_TRACE();
459 0 : return status;
460 : }
461 :
462 0 : static bool dcn21_dmcu_init(struct dmcu *dmcu)
463 : {
464 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
465 0 : uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
466 :
467 0 : if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {
468 : return false;
469 : }
470 :
471 0 : return dcn10_dmcu_init(dmcu);
472 : }
473 :
474 0 : static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
475 : unsigned int start_offset,
476 : const char *src,
477 : unsigned int bytes)
478 : {
479 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
480 0 : unsigned int count = 0;
481 :
482 : /* If microcontroller is not running, do nothing */
483 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
484 : return false;
485 :
486 : /* Enable write access to IRAM */
487 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
488 : IRAM_HOST_ACCESS_EN, 1,
489 : IRAM_WR_ADDR_AUTO_INC, 1);
490 :
491 0 : REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
492 :
493 0 : REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
494 :
495 0 : for (count = 0; count < bytes; count++)
496 0 : REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
497 :
498 : /* Disable write access to IRAM to allow dynamic sleep state */
499 0 : REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
500 : IRAM_HOST_ACCESS_EN, 0,
501 : IRAM_WR_ADDR_AUTO_INC, 0);
502 :
503 : /* Wait until microcontroller is ready to process interrupt */
504 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
505 :
506 : /* Set command to signal IRAM is loaded and to initialize IRAM */
507 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
508 : MCP_INIT_IRAM);
509 :
510 : /* Notify microcontroller of new command */
511 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
512 :
513 : /* Ensure command has been executed before continuing */
514 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
515 :
516 0 : return true;
517 : }
518 :
519 0 : static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)
520 : {
521 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
522 :
523 0 : uint32_t psr_state_offset = 0xf0;
524 :
525 : /* If microcontroller is not running, do nothing */
526 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
527 : return;
528 :
529 : /* Enable write access to IRAM */
530 0 : REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
531 :
532 0 : REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
533 :
534 : /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
535 0 : REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
536 :
537 : /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
538 0 : *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
539 :
540 : /* Disable write access to IRAM after finished using IRAM
541 : * in order to allow dynamic sleep state
542 : */
543 0 : REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
544 : }
545 :
546 0 : static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
547 : {
548 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
549 0 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
550 0 : unsigned int dmcu_wait_reg_ready_interval = 100;
551 :
552 : unsigned int retryCount;
553 0 : enum dc_psr_state state = PSR_STATE0;
554 :
555 : /* If microcontroller is not running, do nothing */
556 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
557 0 : return;
558 :
559 : /* waitDMCUReadyForCmd */
560 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
561 : dmcu_wait_reg_ready_interval,
562 : dmcu_max_retry_on_wait_reg_ready);
563 :
564 : /* setDMCUParam_Cmd */
565 0 : if (enable)
566 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
567 : PSR_ENABLE);
568 : else
569 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
570 : PSR_EXIT);
571 :
572 : /* notifyDMCUMsg */
573 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
574 :
575 : /* Below loops 1000 x 500us = 500 ms.
576 : * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
577 : * least a few frames. Should never hit the max retry assert below.
578 : */
579 0 : if (wait == true) {
580 0 : for (retryCount = 0; retryCount <= 1000; retryCount++) {
581 0 : dcn10_get_dmcu_psr_state(dmcu, &state);
582 0 : if (enable) {
583 0 : if (state != PSR_STATE0)
584 : break;
585 : } else {
586 0 : if (state == PSR_STATE0)
587 : break;
588 : }
589 0 : udelay(500);
590 : }
591 :
592 : /* assert if max retry hit */
593 0 : if (retryCount >= 1000)
594 0 : ASSERT(0);
595 : }
596 : }
597 :
598 0 : static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
599 : struct dc_link *link,
600 : struct psr_context *psr_context)
601 : {
602 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
603 :
604 0 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
605 0 : unsigned int dmcu_wait_reg_ready_interval = 100;
606 :
607 : union dce_dmcu_psr_config_data_reg1 masterCmdData1;
608 : union dce_dmcu_psr_config_data_reg2 masterCmdData2;
609 : union dce_dmcu_psr_config_data_reg3 masterCmdData3;
610 :
611 : /* If microcontroller is not running, do nothing */
612 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
613 : return false;
614 :
615 0 : link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
616 0 : psr_context->psrExitLinkTrainingRequired);
617 :
618 : /* Enable static screen interrupts for PSR supported display */
619 : /* Disable the interrupt coming from other displays. */
620 0 : REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
621 : STATIC_SCREEN1_INT_TO_UC_EN, 0,
622 : STATIC_SCREEN2_INT_TO_UC_EN, 0,
623 : STATIC_SCREEN3_INT_TO_UC_EN, 0,
624 : STATIC_SCREEN4_INT_TO_UC_EN, 0);
625 :
626 0 : switch (psr_context->controllerId) {
627 : /* Driver uses case 1 for unconfigured */
628 : case 1:
629 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
630 : STATIC_SCREEN1_INT_TO_UC_EN, 1);
631 0 : break;
632 : case 2:
633 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
634 : STATIC_SCREEN2_INT_TO_UC_EN, 1);
635 0 : break;
636 : case 3:
637 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
638 : STATIC_SCREEN3_INT_TO_UC_EN, 1);
639 0 : break;
640 : case 4:
641 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
642 : STATIC_SCREEN4_INT_TO_UC_EN, 1);
643 0 : break;
644 : case 5:
645 : /* CZ/NL only has 4 CRTC!!
646 : * really valid.
647 : * There is no interrupt enable mask for these instances.
648 : */
649 : break;
650 : case 6:
651 : /* CZ/NL only has 4 CRTC!!
652 : * These are here because they are defined in HW regspec,
653 : * but not really valid. There is no interrupt enable mask
654 : * for these instances.
655 : */
656 : break;
657 : default:
658 0 : REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
659 : STATIC_SCREEN1_INT_TO_UC_EN, 1);
660 0 : break;
661 : }
662 :
663 0 : link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
664 : psr_context->sdpTransmitLineNumDeadline);
665 :
666 0 : if (psr_context->allow_smu_optimizations)
667 0 : REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
668 :
669 : /* waitDMCUReadyForCmd */
670 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
671 : dmcu_wait_reg_ready_interval,
672 : dmcu_max_retry_on_wait_reg_ready);
673 :
674 : /* setDMCUParam_PSRHostConfigData */
675 0 : masterCmdData1.u32All = 0;
676 0 : masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
677 0 : masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
678 0 : masterCmdData1.bits.rfb_update_auto_en =
679 0 : psr_context->rfb_update_auto_en;
680 0 : masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
681 0 : masterCmdData1.bits.dcp_sel = psr_context->controllerId;
682 0 : masterCmdData1.bits.phy_type = psr_context->phyType;
683 0 : masterCmdData1.bits.frame_cap_ind =
684 0 : psr_context->psrFrameCaptureIndicationReq;
685 0 : masterCmdData1.bits.aux_chan = psr_context->channel;
686 0 : masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
687 0 : masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
688 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
689 : masterCmdData1.u32All);
690 :
691 0 : masterCmdData2.u32All = 0;
692 0 : masterCmdData2.bits.dig_fe = psr_context->engineId;
693 0 : masterCmdData2.bits.dig_be = psr_context->transmitterId;
694 0 : masterCmdData2.bits.skip_wait_for_pll_lock =
695 0 : psr_context->skipPsrWaitForPllLock;
696 0 : masterCmdData2.bits.frame_delay = psr_context->frame_delay;
697 0 : masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
698 0 : masterCmdData2.bits.num_of_controllers =
699 0 : psr_context->numberOfControllers;
700 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
701 : masterCmdData2.u32All);
702 :
703 0 : masterCmdData3.u32All = 0;
704 0 : masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
705 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
706 : masterCmdData3.u32All);
707 :
708 :
709 : /* setDMCUParam_Cmd */
710 0 : REG_UPDATE(MASTER_COMM_CMD_REG,
711 : MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
712 :
713 : /* notifyDMCUMsg */
714 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
715 :
716 : /* waitDMCUReadyForCmd */
717 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
718 :
719 0 : return true;
720 : }
721 :
722 0 : static void dcn10_psr_wait_loop(
723 : struct dmcu *dmcu,
724 : unsigned int wait_loop_number)
725 : {
726 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
727 : union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
728 :
729 : /* If microcontroller is not running, do nothing */
730 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
731 0 : return;
732 :
733 0 : if (wait_loop_number != 0) {
734 : /* waitDMCUReadyForCmd */
735 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
736 :
737 0 : masterCmdData1.u32 = 0;
738 0 : masterCmdData1.bits.wait_loop = wait_loop_number;
739 0 : dmcu->cached_wait_loop_number = wait_loop_number;
740 0 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
741 :
742 : /* setDMCUParam_Cmd */
743 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
744 :
745 : /* notifyDMCUMsg */
746 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
747 : }
748 : }
749 :
750 0 : static void dcn10_get_psr_wait_loop(
751 : struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
752 : {
753 0 : *psr_wait_loop_number = dmcu->cached_wait_loop_number;
754 0 : return;
755 : }
756 :
757 0 : static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
758 : {
759 : /* microcontroller is not running */
760 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
761 : return false;
762 0 : return true;
763 : }
764 :
765 :
766 :
767 0 : static bool dcn20_lock_phy(struct dmcu *dmcu)
768 : {
769 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
770 :
771 : /* If microcontroller is not running, do nothing */
772 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
773 : return false;
774 :
775 : /* waitDMCUReadyForCmd */
776 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
777 :
778 : /* setDMCUParam_Cmd */
779 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
780 :
781 : /* notifyDMCUMsg */
782 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
783 :
784 : /* waitDMCUReadyForCmd */
785 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
786 :
787 0 : return true;
788 : }
789 :
790 0 : static bool dcn20_unlock_phy(struct dmcu *dmcu)
791 : {
792 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
793 :
794 : /* If microcontroller is not running, do nothing */
795 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
796 : return false;
797 :
798 : /* waitDMCUReadyForCmd */
799 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
800 :
801 : /* setDMCUParam_Cmd */
802 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
803 :
804 : /* notifyDMCUMsg */
805 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
806 :
807 : /* waitDMCUReadyForCmd */
808 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
809 :
810 0 : return true;
811 : }
812 :
813 0 : static bool dcn10_send_edid_cea(struct dmcu *dmcu,
814 : int offset,
815 : int total_length,
816 : uint8_t *data,
817 : int length)
818 : {
819 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
820 : uint32_t header, data1, data2;
821 :
822 : /* If microcontroller is not running, do nothing */
823 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
824 : return false;
825 :
826 0 : if (length > 8 || length <= 0)
827 : return false;
828 :
829 0 : header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF);
830 0 : data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) |
831 0 : (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]);
832 0 : data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) |
833 0 : (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]);
834 :
835 : /* waitDMCUReadyForCmd */
836 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
837 :
838 : /* setDMCUParam_Cmd */
839 0 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA);
840 :
841 0 : REG_WRITE(MASTER_COMM_DATA_REG1, header);
842 0 : REG_WRITE(MASTER_COMM_DATA_REG2, data1);
843 0 : REG_WRITE(MASTER_COMM_DATA_REG3, data2);
844 :
845 : /* notifyDMCUMsg */
846 0 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
847 :
848 : /* waitDMCUReadyForCmd */
849 0 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
850 :
851 0 : return true;
852 : }
853 :
854 0 : static bool dcn10_get_scp_results(struct dmcu *dmcu,
855 : uint32_t *cmd,
856 : uint32_t *data1,
857 : uint32_t *data2,
858 : uint32_t *data3)
859 : {
860 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
861 :
862 : /* If microcontroller is not running, do nothing */
863 0 : if (dmcu->dmcu_state != DMCU_RUNNING)
864 : return false;
865 :
866 0 : *cmd = REG_READ(SLAVE_COMM_CMD_REG);
867 0 : *data1 = REG_READ(SLAVE_COMM_DATA_REG1);
868 0 : *data2 = REG_READ(SLAVE_COMM_DATA_REG2);
869 0 : *data3 = REG_READ(SLAVE_COMM_DATA_REG3);
870 :
871 : /* clear SCP interrupt */
872 0 : REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0);
873 :
874 0 : return true;
875 : }
876 :
877 0 : static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu,
878 : int *version,
879 : int *min_frame_rate,
880 : int *max_frame_rate)
881 : {
882 : uint32_t data[4];
883 : int cmd, ack, len;
884 :
885 0 : if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3]))
886 : return false;
887 :
888 0 : cmd = data[0] & 0x3FF;
889 0 : len = (data[0] >> 10) & 0x3F;
890 0 : ack = data[1];
891 :
892 0 : if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12)
893 : return false;
894 :
895 0 : if ((data[2] & 0xFF)) {
896 0 : *version = (data[2] >> 8) & 0xFF;
897 0 : *min_frame_rate = (data[3] >> 16) & 0xFFFF;
898 0 : *max_frame_rate = data[3] & 0xFFFF;
899 0 : return true;
900 : }
901 :
902 : return false;
903 : }
904 :
905 0 : static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)
906 : {
907 : uint32_t data[4];
908 : int cmd, ack;
909 :
910 0 : if (!dcn10_get_scp_results(dmcu,
911 : &data[0], &data[1], &data[2], &data[3]))
912 : return false;
913 :
914 0 : cmd = data[0] & 0x3FF;
915 0 : ack = data[1];
916 :
917 0 : if (cmd != MCP_SEND_EDID_CEA)
918 : return false;
919 :
920 0 : if (ack == EDID_CEA_CMD_ACK)
921 : return true;
922 :
923 0 : *offset = data[2]; /* nack */
924 0 : return false;
925 : }
926 :
927 :
928 : #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
929 : static void dcn10_forward_crc_window(struct dmcu *dmcu,
930 : struct crc_region *crc_win,
931 : struct otg_phy_mux *mux_mapping)
932 : {
933 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
934 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
935 : unsigned int dmcu_wait_reg_ready_interval = 100;
936 : unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0;
937 :
938 : /* If microcontroller is not running, do nothing */
939 : if (dmcu->dmcu_state != DMCU_RUNNING)
940 : return;
941 :
942 : if (!crc_win)
943 : return;
944 :
945 : /* waitDMCUReadyForCmd */
946 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
947 : dmcu_wait_reg_ready_interval,
948 : dmcu_max_retry_on_wait_reg_ready);
949 :
950 : /* build up nitification data */
951 : crc_start = (((unsigned int) crc_win->x_start) << 16) | crc_win->y_start;
952 : crc_end = (((unsigned int) crc_win->x_end) << 16) | crc_win->y_end;
953 : otg_phy_mux =
954 : (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num;
955 :
956 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
957 : crc_start);
958 :
959 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
960 : crc_end);
961 :
962 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
963 : otg_phy_mux);
964 :
965 : /* setDMCUParam_Cmd */
966 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
967 : CRC_WIN_NOTIFY);
968 :
969 : /* notifyDMCUMsg */
970 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
971 : }
972 :
973 : static void dcn10_stop_crc_win_update(struct dmcu *dmcu,
974 : struct otg_phy_mux *mux_mapping)
975 : {
976 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
977 : unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
978 : unsigned int dmcu_wait_reg_ready_interval = 100;
979 : unsigned int otg_phy_mux = 0;
980 :
981 : /* If microcontroller is not running, do nothing */
982 : if (dmcu->dmcu_state != DMCU_RUNNING)
983 : return;
984 :
985 : /* waitDMCUReadyForCmd */
986 : REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
987 : dmcu_wait_reg_ready_interval,
988 : dmcu_max_retry_on_wait_reg_ready);
989 :
990 : /* build up nitification data */
991 : otg_phy_mux =
992 : (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num;
993 :
994 : dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
995 : otg_phy_mux);
996 :
997 : /* setDMCUParam_Cmd */
998 : REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
999 : CRC_STOP_UPDATE);
1000 :
1001 : /* notifyDMCUMsg */
1002 : REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
1003 : }
1004 : #endif
1005 :
1006 : static const struct dmcu_funcs dce_funcs = {
1007 : .dmcu_init = dce_dmcu_init,
1008 : .load_iram = dce_dmcu_load_iram,
1009 : .set_psr_enable = dce_dmcu_set_psr_enable,
1010 : .setup_psr = dce_dmcu_setup_psr,
1011 : .get_psr_state = dce_get_dmcu_psr_state,
1012 : .set_psr_wait_loop = dce_psr_wait_loop,
1013 : .get_psr_wait_loop = dce_get_psr_wait_loop,
1014 : .is_dmcu_initialized = dce_is_dmcu_initialized
1015 : };
1016 :
1017 : static const struct dmcu_funcs dcn10_funcs = {
1018 : .dmcu_init = dcn10_dmcu_init,
1019 : .load_iram = dcn10_dmcu_load_iram,
1020 : .set_psr_enable = dcn10_dmcu_set_psr_enable,
1021 : .setup_psr = dcn10_dmcu_setup_psr,
1022 : .get_psr_state = dcn10_get_dmcu_psr_state,
1023 : .set_psr_wait_loop = dcn10_psr_wait_loop,
1024 : .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1025 : .send_edid_cea = dcn10_send_edid_cea,
1026 : .recv_amd_vsdb = dcn10_recv_amd_vsdb,
1027 : .recv_edid_cea_ack = dcn10_recv_edid_cea_ack,
1028 : #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1029 : .forward_crc_window = dcn10_forward_crc_window,
1030 : .stop_crc_win_update = dcn10_stop_crc_win_update,
1031 : #endif
1032 : .is_dmcu_initialized = dcn10_is_dmcu_initialized
1033 : };
1034 :
1035 : static const struct dmcu_funcs dcn20_funcs = {
1036 : .dmcu_init = dcn10_dmcu_init,
1037 : .load_iram = dcn10_dmcu_load_iram,
1038 : .set_psr_enable = dcn10_dmcu_set_psr_enable,
1039 : .setup_psr = dcn10_dmcu_setup_psr,
1040 : .get_psr_state = dcn10_get_dmcu_psr_state,
1041 : .set_psr_wait_loop = dcn10_psr_wait_loop,
1042 : .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1043 : .is_dmcu_initialized = dcn10_is_dmcu_initialized,
1044 : .lock_phy = dcn20_lock_phy,
1045 : .unlock_phy = dcn20_unlock_phy
1046 : };
1047 :
1048 : static const struct dmcu_funcs dcn21_funcs = {
1049 : .dmcu_init = dcn21_dmcu_init,
1050 : .load_iram = dcn10_dmcu_load_iram,
1051 : .set_psr_enable = dcn10_dmcu_set_psr_enable,
1052 : .setup_psr = dcn10_dmcu_setup_psr,
1053 : .get_psr_state = dcn10_get_dmcu_psr_state,
1054 : .set_psr_wait_loop = dcn10_psr_wait_loop,
1055 : .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1056 : .is_dmcu_initialized = dcn10_is_dmcu_initialized,
1057 : .lock_phy = dcn20_lock_phy,
1058 : .unlock_phy = dcn20_unlock_phy
1059 : };
1060 :
1061 : static void dce_dmcu_construct(
1062 : struct dce_dmcu *dmcu_dce,
1063 : struct dc_context *ctx,
1064 : const struct dce_dmcu_registers *regs,
1065 : const struct dce_dmcu_shift *dmcu_shift,
1066 : const struct dce_dmcu_mask *dmcu_mask)
1067 : {
1068 0 : struct dmcu *base = &dmcu_dce->base;
1069 :
1070 0 : base->ctx = ctx;
1071 0 : base->funcs = &dce_funcs;
1072 0 : base->cached_wait_loop_number = 0;
1073 :
1074 0 : dmcu_dce->regs = regs;
1075 0 : dmcu_dce->dmcu_shift = dmcu_shift;
1076 0 : dmcu_dce->dmcu_mask = dmcu_mask;
1077 : }
1078 :
1079 0 : static void dcn21_dmcu_construct(
1080 : struct dce_dmcu *dmcu_dce,
1081 : struct dc_context *ctx,
1082 : const struct dce_dmcu_registers *regs,
1083 : const struct dce_dmcu_shift *dmcu_shift,
1084 : const struct dce_dmcu_mask *dmcu_mask)
1085 : {
1086 0 : uint32_t psp_version = 0;
1087 :
1088 0 : dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1089 :
1090 0 : if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
1091 0 : psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
1092 0 : dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
1093 0 : dmcu_dce->base.psp_version = psp_version;
1094 : }
1095 0 : }
1096 :
1097 0 : struct dmcu *dce_dmcu_create(
1098 : struct dc_context *ctx,
1099 : const struct dce_dmcu_registers *regs,
1100 : const struct dce_dmcu_shift *dmcu_shift,
1101 : const struct dce_dmcu_mask *dmcu_mask)
1102 : {
1103 0 : struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
1104 :
1105 0 : if (dmcu_dce == NULL) {
1106 0 : BREAK_TO_DEBUGGER();
1107 0 : return NULL;
1108 : }
1109 :
1110 0 : dce_dmcu_construct(
1111 : dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1112 :
1113 : dmcu_dce->base.funcs = &dce_funcs;
1114 :
1115 0 : return &dmcu_dce->base;
1116 : }
1117 :
1118 0 : struct dmcu *dcn10_dmcu_create(
1119 : struct dc_context *ctx,
1120 : const struct dce_dmcu_registers *regs,
1121 : const struct dce_dmcu_shift *dmcu_shift,
1122 : const struct dce_dmcu_mask *dmcu_mask)
1123 : {
1124 0 : struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1125 :
1126 0 : if (dmcu_dce == NULL) {
1127 0 : BREAK_TO_DEBUGGER();
1128 0 : return NULL;
1129 : }
1130 :
1131 0 : dce_dmcu_construct(
1132 : dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1133 :
1134 0 : dmcu_dce->base.funcs = &dcn10_funcs;
1135 :
1136 0 : return &dmcu_dce->base;
1137 : }
1138 :
1139 0 : struct dmcu *dcn20_dmcu_create(
1140 : struct dc_context *ctx,
1141 : const struct dce_dmcu_registers *regs,
1142 : const struct dce_dmcu_shift *dmcu_shift,
1143 : const struct dce_dmcu_mask *dmcu_mask)
1144 : {
1145 0 : struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1146 :
1147 0 : if (dmcu_dce == NULL) {
1148 0 : BREAK_TO_DEBUGGER();
1149 0 : return NULL;
1150 : }
1151 :
1152 0 : dce_dmcu_construct(
1153 : dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1154 :
1155 0 : dmcu_dce->base.funcs = &dcn20_funcs;
1156 :
1157 0 : return &dmcu_dce->base;
1158 : }
1159 :
1160 0 : struct dmcu *dcn21_dmcu_create(
1161 : struct dc_context *ctx,
1162 : const struct dce_dmcu_registers *regs,
1163 : const struct dce_dmcu_shift *dmcu_shift,
1164 : const struct dce_dmcu_mask *dmcu_mask)
1165 : {
1166 0 : struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1167 :
1168 0 : if (dmcu_dce == NULL) {
1169 0 : BREAK_TO_DEBUGGER();
1170 0 : return NULL;
1171 : }
1172 :
1173 0 : dcn21_dmcu_construct(
1174 : dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1175 :
1176 0 : dmcu_dce->base.funcs = &dcn21_funcs;
1177 :
1178 0 : return &dmcu_dce->base;
1179 : }
1180 :
1181 0 : void dce_dmcu_destroy(struct dmcu **dmcu)
1182 : {
1183 0 : struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
1184 :
1185 0 : kfree(dmcu_dce);
1186 0 : *dmcu = NULL;
1187 0 : }
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