Line data Source code
1 : /*
2 : * Copyright 2019 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dmub_psr.h"
27 : #include "dc.h"
28 : #include "dc_dmub_srv.h"
29 : #include "dmub/dmub_srv.h"
30 : #include "core_types.h"
31 :
32 : #define DC_TRACE_LEVEL_MESSAGE(...) do {} while (0) /* do nothing */
33 :
34 : #define MAX_PIPES 6
35 :
36 : /*
37 : * Convert dmcub psr state to dmcu psr state.
38 : */
39 0 : static enum dc_psr_state convert_psr_state(uint32_t raw_state)
40 : {
41 0 : enum dc_psr_state state = PSR_STATE0;
42 :
43 0 : if (raw_state == 0)
44 : state = PSR_STATE0;
45 0 : else if (raw_state == 0x10)
46 : state = PSR_STATE1;
47 0 : else if (raw_state == 0x11)
48 : state = PSR_STATE1a;
49 0 : else if (raw_state == 0x20)
50 : state = PSR_STATE2;
51 0 : else if (raw_state == 0x21)
52 : state = PSR_STATE2a;
53 0 : else if (raw_state == 0x22)
54 : state = PSR_STATE2b;
55 0 : else if (raw_state == 0x30)
56 : state = PSR_STATE3;
57 0 : else if (raw_state == 0x31)
58 : state = PSR_STATE3Init;
59 0 : else if (raw_state == 0x40)
60 : state = PSR_STATE4;
61 0 : else if (raw_state == 0x41)
62 : state = PSR_STATE4a;
63 0 : else if (raw_state == 0x42)
64 : state = PSR_STATE4b;
65 0 : else if (raw_state == 0x43)
66 : state = PSR_STATE4c;
67 0 : else if (raw_state == 0x44)
68 : state = PSR_STATE4d;
69 0 : else if (raw_state == 0x50)
70 : state = PSR_STATE5;
71 0 : else if (raw_state == 0x51)
72 : state = PSR_STATE5a;
73 0 : else if (raw_state == 0x52)
74 : state = PSR_STATE5b;
75 0 : else if (raw_state == 0x53)
76 : state = PSR_STATE5c;
77 0 : else if (raw_state == 0x4A)
78 : state = PSR_STATE4_FULL_FRAME;
79 0 : else if (raw_state == 0x4B)
80 : state = PSR_STATE4a_FULL_FRAME;
81 0 : else if (raw_state == 0x4C)
82 : state = PSR_STATE4b_FULL_FRAME;
83 0 : else if (raw_state == 0x4D)
84 : state = PSR_STATE4c_FULL_FRAME;
85 0 : else if (raw_state == 0x4E)
86 : state = PSR_STATE4_FULL_FRAME_POWERUP;
87 0 : else if (raw_state == 0x60)
88 : state = PSR_STATE_HWLOCK_MGR;
89 0 : else if (raw_state == 0x61)
90 : state = PSR_STATE_POLLVUPDATE;
91 : else
92 0 : state = PSR_STATE_INVALID;
93 :
94 0 : return state;
95 : }
96 :
97 : /*
98 : * Get PSR state from firmware.
99 : */
100 0 : static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
101 : {
102 0 : struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
103 0 : uint32_t raw_state = 0;
104 0 : uint32_t retry_count = 0;
105 : enum dmub_status status;
106 :
107 : do {
108 : // Send gpint command and wait for ack
109 0 : status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
110 :
111 0 : if (status == DMUB_STATUS_OK) {
112 : // GPINT was executed, get response
113 0 : dmub_srv_get_gpint_response(srv, &raw_state);
114 0 : *state = convert_psr_state(raw_state);
115 : } else
116 : // Return invalid state when GPINT times out
117 0 : *state = PSR_STATE_INVALID;
118 :
119 0 : } while (++retry_count <= 1000 && *state == PSR_STATE_INVALID);
120 :
121 : // Assert if max retry hit
122 0 : if (retry_count >= 1000 && *state == PSR_STATE_INVALID) {
123 0 : ASSERT(0);
124 : DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
125 : WPP_BIT_FLAG_Firmware_PsrState,
126 : "Unable to get PSR state from FW.");
127 : } else
128 : DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
129 : WPP_BIT_FLAG_Firmware_PsrState,
130 : "Got PSR state from FW. PSR state: %d, Retry count: %d",
131 : *state, retry_count);
132 0 : }
133 :
134 : /*
135 : * Set PSR version.
136 : */
137 0 : static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
138 : {
139 : union dmub_rb_cmd cmd;
140 0 : struct dc_context *dc = dmub->ctx;
141 :
142 0 : if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED)
143 : return false;
144 :
145 0 : memset(&cmd, 0, sizeof(cmd));
146 0 : cmd.psr_set_version.header.type = DMUB_CMD__PSR;
147 0 : cmd.psr_set_version.header.sub_type = DMUB_CMD__PSR_SET_VERSION;
148 0 : switch (stream->link->psr_settings.psr_version) {
149 : case DC_PSR_VERSION_1:
150 0 : cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_1;
151 0 : break;
152 : case DC_PSR_VERSION_SU_1:
153 0 : cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_SU_1;
154 0 : break;
155 : case DC_PSR_VERSION_UNSUPPORTED:
156 : default:
157 0 : cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
158 0 : break;
159 : }
160 :
161 0 : if (cmd.psr_set_version.psr_set_version_data.version == PSR_VERSION_UNSUPPORTED)
162 : return false;
163 :
164 0 : cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
165 0 : cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
166 0 : cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
167 :
168 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
169 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
170 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
171 :
172 0 : return true;
173 : }
174 :
175 : /*
176 : * Enable/Disable PSR.
177 : */
178 0 : static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
179 : {
180 : union dmub_rb_cmd cmd;
181 0 : struct dc_context *dc = dmub->ctx;
182 : uint32_t retry_count;
183 0 : enum dc_psr_state state = PSR_STATE0;
184 :
185 0 : memset(&cmd, 0, sizeof(cmd));
186 0 : cmd.psr_enable.header.type = DMUB_CMD__PSR;
187 :
188 0 : cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
189 0 : cmd.psr_enable.data.panel_inst = panel_inst;
190 :
191 0 : if (enable)
192 0 : cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
193 : else
194 0 : cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE;
195 :
196 0 : cmd.psr_enable.header.payload_bytes = 0; // Send header only
197 :
198 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
199 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
200 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
201 :
202 : /* Below loops 1000 x 500us = 500 ms.
203 : * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
204 : * least a few frames. Should never hit the max retry assert below.
205 : */
206 0 : if (wait) {
207 0 : for (retry_count = 0; retry_count <= 1000; retry_count++) {
208 0 : dmub_psr_get_state(dmub, &state, panel_inst);
209 :
210 0 : if (enable) {
211 0 : if (state != PSR_STATE0)
212 : break;
213 : } else {
214 0 : if (state == PSR_STATE0)
215 : break;
216 : }
217 :
218 0 : udelay(500);
219 : }
220 :
221 : /* assert if max retry hit */
222 0 : if (retry_count >= 1000)
223 0 : ASSERT(0);
224 : }
225 0 : }
226 :
227 : /*
228 : * Set PSR level.
229 : */
230 0 : static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
231 : {
232 : union dmub_rb_cmd cmd;
233 0 : enum dc_psr_state state = PSR_STATE0;
234 0 : struct dc_context *dc = dmub->ctx;
235 :
236 0 : dmub_psr_get_state(dmub, &state, panel_inst);
237 :
238 0 : if (state == PSR_STATE0)
239 0 : return;
240 :
241 0 : memset(&cmd, 0, sizeof(cmd));
242 0 : cmd.psr_set_level.header.type = DMUB_CMD__PSR;
243 0 : cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
244 0 : cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
245 0 : cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
246 0 : cmd.psr_set_level.psr_set_level_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
247 0 : cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
248 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
249 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
250 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
251 : }
252 :
253 : /**
254 : * Set PSR vtotal requirement for FreeSync PSR.
255 : */
256 0 : static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
257 : uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
258 : {
259 : union dmub_rb_cmd cmd;
260 0 : struct dc_context *dc = dmub->ctx;
261 :
262 0 : memset(&cmd, 0, sizeof(cmd));
263 0 : cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
264 0 : cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
265 0 : cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
266 0 : cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
267 0 : cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
268 :
269 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
270 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
271 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
272 0 : }
273 :
274 : /*
275 : * Set PSR power optimization flags.
276 : */
277 0 : static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst)
278 : {
279 : union dmub_rb_cmd cmd;
280 0 : struct dc_context *dc = dmub->ctx;
281 :
282 0 : memset(&cmd, 0, sizeof(cmd));
283 0 : cmd.psr_set_power_opt.header.type = DMUB_CMD__PSR;
284 0 : cmd.psr_set_power_opt.header.sub_type = DMUB_CMD__SET_PSR_POWER_OPT;
285 0 : cmd.psr_set_power_opt.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_power_opt_data);
286 0 : cmd.psr_set_power_opt.psr_set_power_opt_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
287 0 : cmd.psr_set_power_opt.psr_set_power_opt_data.power_opt = power_opt;
288 0 : cmd.psr_set_power_opt.psr_set_power_opt_data.panel_inst = panel_inst;
289 :
290 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
291 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
292 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
293 0 : }
294 :
295 : /*
296 : * Setup PSR by programming phy registers and sending psr hw context values to firmware.
297 : */
298 0 : static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
299 : struct dc_link *link,
300 : struct psr_context *psr_context,
301 : uint8_t panel_inst)
302 : {
303 : union dmub_rb_cmd cmd;
304 0 : struct dc_context *dc = dmub->ctx;
305 0 : struct dmub_cmd_psr_copy_settings_data *copy_settings_data
306 : = &cmd.psr_copy_settings.psr_copy_settings_data;
307 0 : struct pipe_ctx *pipe_ctx = NULL;
308 0 : struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
309 0 : int i = 0;
310 :
311 0 : for (i = 0; i < MAX_PIPES; i++) {
312 0 : if (res_ctx->pipe_ctx[i].stream &&
313 0 : res_ctx->pipe_ctx[i].stream->link == link &&
314 0 : res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
315 0 : pipe_ctx = &res_ctx->pipe_ctx[i];
316 : //TODO: refactor for multi edp support
317 0 : break;
318 : }
319 : }
320 :
321 0 : if (!pipe_ctx)
322 : return false;
323 :
324 : // First, set the psr version
325 0 : if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
326 : return false;
327 :
328 : // Program DP DPHY fast training registers
329 0 : link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
330 0 : psr_context->psrExitLinkTrainingRequired);
331 :
332 : // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high
333 0 : link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
334 : psr_context->sdpTransmitLineNumDeadline);
335 :
336 0 : memset(&cmd, 0, sizeof(cmd));
337 0 : cmd.psr_copy_settings.header.type = DMUB_CMD__PSR;
338 0 : cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS;
339 0 : cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
340 :
341 : // Hw insts
342 0 : copy_settings_data->dpphy_inst = psr_context->transmitterId;
343 0 : copy_settings_data->aux_inst = psr_context->channel;
344 0 : copy_settings_data->digfe_inst = psr_context->engineId;
345 0 : copy_settings_data->digbe_inst = psr_context->transmitterId;
346 :
347 0 : copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
348 :
349 0 : if (pipe_ctx->plane_res.dpp)
350 0 : copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
351 : else
352 0 : copy_settings_data->dpp_inst = 0;
353 0 : if (pipe_ctx->stream_res.opp)
354 0 : copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst;
355 : else
356 0 : copy_settings_data->opp_inst = 0;
357 0 : if (pipe_ctx->stream_res.tg)
358 0 : copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst;
359 : else
360 0 : copy_settings_data->otg_inst = 0;
361 :
362 : // Misc
363 0 : copy_settings_data->use_phy_fsm = link->ctx->dc->debug.psr_power_use_phy_fsm;
364 0 : copy_settings_data->psr_level = psr_context->psr_level.u32all;
365 0 : copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
366 0 : copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;
367 0 : copy_settings_data->frame_delay = psr_context->frame_delay;
368 0 : copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
369 0 : copy_settings_data->init_sdp_deadline = psr_context->sdpTransmitLineNumDeadline;
370 0 : copy_settings_data->debug.u32All = 0;
371 0 : copy_settings_data->debug.bitfields.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
372 0 : copy_settings_data->debug.bitfields.use_hw_lock_mgr = 1;
373 0 : copy_settings_data->debug.bitfields.force_full_frame_update = 0;
374 :
375 0 : if (psr_context->su_granularity_required == 0)
376 0 : copy_settings_data->su_y_granularity = 0;
377 : else
378 0 : copy_settings_data->su_y_granularity = psr_context->su_y_granularity;
379 :
380 0 : copy_settings_data->line_capture_indication = 0;
381 0 : copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
382 0 : copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
383 0 : copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
384 0 : copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
385 0 : copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
386 0 : copy_settings_data->panel_inst = panel_inst;
387 0 : copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1);
388 :
389 : /**
390 : * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update)
391 : * Note that PSRSU+DSC is still under development.
392 : */
393 0 : if (copy_settings_data->dsc_enable_status &&
394 0 : link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
395 0 : !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
396 : sizeof(link->dpcd_caps.sink_dev_id_str)))
397 0 : link->psr_settings.force_ffu_mode = 1;
398 : else
399 0 : link->psr_settings.force_ffu_mode = 0;
400 0 : copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode;
401 :
402 0 : if (link->fec_state == dc_link_fec_enabled &&
403 0 : (!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
404 0 : sizeof(link->dpcd_caps.sink_dev_id_str)) ||
405 0 : !memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
406 : sizeof(link->dpcd_caps.sink_dev_id_str))))
407 0 : copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1;
408 : else
409 0 : copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0;
410 :
411 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
412 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
413 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
414 :
415 0 : return true;
416 : }
417 :
418 : /*
419 : * Send command to PSR to force static ENTER and ignore all state changes until exit
420 : */
421 0 : static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
422 : {
423 : union dmub_rb_cmd cmd;
424 0 : struct dc_context *dc = dmub->ctx;
425 :
426 0 : memset(&cmd, 0, sizeof(cmd));
427 :
428 0 : cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
429 0 : cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
430 0 : cmd.psr_force_static.header.type = DMUB_CMD__PSR;
431 0 : cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
432 0 : cmd.psr_enable.header.payload_bytes = 0;
433 :
434 0 : dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
435 0 : dc_dmub_srv_cmd_execute(dc->dmub_srv);
436 0 : dc_dmub_srv_wait_idle(dc->dmub_srv);
437 0 : }
438 :
439 : /*
440 : * Get PSR residency from firmware.
441 : */
442 0 : static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
443 : {
444 0 : struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
445 0 : uint16_t param = (uint16_t)(panel_inst << 8);
446 :
447 : /* Send gpint command and wait for ack */
448 0 : dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
449 :
450 0 : dmub_srv_get_gpint_response(srv, residency);
451 0 : }
452 :
453 : static const struct dmub_psr_funcs psr_funcs = {
454 : .psr_copy_settings = dmub_psr_copy_settings,
455 : .psr_enable = dmub_psr_enable,
456 : .psr_get_state = dmub_psr_get_state,
457 : .psr_set_level = dmub_psr_set_level,
458 : .psr_force_static = dmub_psr_force_static,
459 : .psr_get_residency = dmub_psr_get_residency,
460 : .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active,
461 : .psr_set_power_opt = dmub_psr_set_power_opt,
462 : };
463 :
464 : /*
465 : * Construct PSR object.
466 : */
467 : static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)
468 : {
469 0 : psr->ctx = ctx;
470 0 : psr->funcs = &psr_funcs;
471 : }
472 :
473 : /*
474 : * Allocate and initialize PSR object.
475 : */
476 0 : struct dmub_psr *dmub_psr_create(struct dc_context *ctx)
477 : {
478 0 : struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL);
479 :
480 0 : if (psr == NULL) {
481 0 : BREAK_TO_DEBUGGER();
482 0 : return NULL;
483 : }
484 :
485 0 : dmub_psr_construct(psr, ctx);
486 :
487 0 : return psr;
488 : }
489 :
490 : /*
491 : * Deallocate PSR object.
492 : */
493 0 : void dmub_psr_destroy(struct dmub_psr **dmub)
494 : {
495 0 : kfree(*dmub);
496 0 : *dmub = NULL;
497 0 : }
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