Line data Source code
1 : /*
2 : * Copyright 2012-16 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 : #include "dm_services.h"
26 :
27 : #include "dce/dce_11_0_d.h"
28 : #include "dce/dce_11_0_sh_mask.h"
29 : /* TODO: this needs to be looked at, used by Stella's workaround*/
30 : #include "gmc/gmc_8_2_d.h"
31 : #include "gmc/gmc_8_2_sh_mask.h"
32 :
33 : #include "include/logger_interface.h"
34 : #include "inc/dce_calcs.h"
35 :
36 : #include "dce/dce_mem_input.h"
37 : #include "dce110_mem_input_v.h"
38 :
39 0 : static void set_flip_control(
40 : struct dce_mem_input *mem_input110,
41 : bool immediate)
42 : {
43 0 : uint32_t value = 0;
44 :
45 0 : value = dm_read_reg(
46 : mem_input110->base.ctx,
47 : mmUNP_FLIP_CONTROL);
48 :
49 0 : set_reg_field_value(value, 1,
50 : UNP_FLIP_CONTROL,
51 : GRPH_SURFACE_UPDATE_PENDING_MODE);
52 :
53 0 : dm_write_reg(
54 : mem_input110->base.ctx,
55 : mmUNP_FLIP_CONTROL,
56 : value);
57 0 : }
58 :
59 : /* chroma part */
60 0 : static void program_pri_addr_c(
61 : struct dce_mem_input *mem_input110,
62 : PHYSICAL_ADDRESS_LOC address)
63 : {
64 0 : uint32_t value = 0;
65 0 : uint32_t temp = 0;
66 : /*high register MUST be programmed first*/
67 0 : temp = address.high_part &
68 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK;
69 :
70 0 : set_reg_field_value(value, temp,
71 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
72 : GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C);
73 :
74 0 : dm_write_reg(
75 : mem_input110->base.ctx,
76 : mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
77 : value);
78 :
79 0 : temp = 0;
80 0 : value = 0;
81 0 : temp = address.low_part >>
82 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;
83 :
84 0 : set_reg_field_value(value, temp,
85 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
86 : GRPH_PRIMARY_SURFACE_ADDRESS_C);
87 :
88 0 : dm_write_reg(
89 : mem_input110->base.ctx,
90 : mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
91 : value);
92 0 : }
93 :
94 : /* luma part */
95 0 : static void program_pri_addr_l(
96 : struct dce_mem_input *mem_input110,
97 : PHYSICAL_ADDRESS_LOC address)
98 : {
99 0 : uint32_t value = 0;
100 0 : uint32_t temp = 0;
101 :
102 : /*high register MUST be programmed first*/
103 0 : temp = address.high_part &
104 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK;
105 :
106 0 : set_reg_field_value(value, temp,
107 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
108 : GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L);
109 :
110 0 : dm_write_reg(
111 : mem_input110->base.ctx,
112 : mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
113 : value);
114 :
115 0 : temp = 0;
116 0 : value = 0;
117 0 : temp = address.low_part >>
118 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;
119 :
120 0 : set_reg_field_value(value, temp,
121 : UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
122 : GRPH_PRIMARY_SURFACE_ADDRESS_L);
123 :
124 0 : dm_write_reg(
125 : mem_input110->base.ctx,
126 : mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
127 : value);
128 0 : }
129 :
130 0 : static void program_addr(
131 : struct dce_mem_input *mem_input110,
132 : const struct dc_plane_address *addr)
133 : {
134 0 : switch (addr->type) {
135 : case PLN_ADDR_TYPE_GRAPHICS:
136 0 : program_pri_addr_l(
137 : mem_input110,
138 : addr->grph.addr);
139 0 : break;
140 : case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
141 0 : program_pri_addr_c(
142 : mem_input110,
143 : addr->video_progressive.chroma_addr);
144 0 : program_pri_addr_l(
145 : mem_input110,
146 : addr->video_progressive.luma_addr);
147 0 : break;
148 : default:
149 : /* not supported */
150 0 : BREAK_TO_DEBUGGER();
151 : }
152 0 : }
153 :
154 0 : static void enable(struct dce_mem_input *mem_input110)
155 : {
156 0 : uint32_t value = 0;
157 :
158 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
159 0 : set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
160 0 : dm_write_reg(mem_input110->base.ctx,
161 : mmUNP_GRPH_ENABLE,
162 : value);
163 0 : }
164 :
165 0 : static void program_tiling(
166 : struct dce_mem_input *mem_input110,
167 : const union dc_tiling_info *info,
168 : const enum surface_pixel_format pixel_format)
169 : {
170 0 : uint32_t value = 0;
171 :
172 0 : set_reg_field_value(value, info->gfx8.num_banks,
173 : UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
174 :
175 0 : set_reg_field_value(value, info->gfx8.bank_width,
176 : UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L);
177 :
178 0 : set_reg_field_value(value, info->gfx8.bank_height,
179 : UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L);
180 :
181 0 : set_reg_field_value(value, info->gfx8.tile_aspect,
182 : UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L);
183 :
184 0 : set_reg_field_value(value, info->gfx8.tile_split,
185 : UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L);
186 :
187 0 : set_reg_field_value(value, info->gfx8.tile_mode,
188 : UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L);
189 :
190 0 : set_reg_field_value(value, info->gfx8.pipe_config,
191 : UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG);
192 :
193 0 : set_reg_field_value(value, info->gfx8.array_mode,
194 : UNP_GRPH_CONTROL, GRPH_ARRAY_MODE);
195 :
196 0 : set_reg_field_value(value, 1,
197 : UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
198 :
199 0 : set_reg_field_value(value, 0,
200 : UNP_GRPH_CONTROL, GRPH_Z);
201 :
202 0 : dm_write_reg(
203 : mem_input110->base.ctx,
204 : mmUNP_GRPH_CONTROL,
205 : value);
206 :
207 0 : value = 0;
208 :
209 0 : set_reg_field_value(value, info->gfx8.bank_width_c,
210 : UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C);
211 :
212 0 : set_reg_field_value(value, info->gfx8.bank_height_c,
213 : UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C);
214 :
215 0 : set_reg_field_value(value, info->gfx8.tile_aspect_c,
216 : UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C);
217 :
218 0 : set_reg_field_value(value, info->gfx8.tile_split_c,
219 : UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C);
220 :
221 0 : set_reg_field_value(value, info->gfx8.tile_mode_c,
222 : UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C);
223 :
224 0 : dm_write_reg(
225 : mem_input110->base.ctx,
226 : mmUNP_GRPH_CONTROL_C,
227 : value);
228 0 : }
229 :
230 0 : static void program_size_and_rotation(
231 : struct dce_mem_input *mem_input110,
232 : enum dc_rotation_angle rotation,
233 : const struct plane_size *plane_size)
234 : {
235 0 : uint32_t value = 0;
236 0 : struct plane_size local_size = *plane_size;
237 :
238 0 : if (rotation == ROTATION_ANGLE_90 ||
239 0 : rotation == ROTATION_ANGLE_270) {
240 :
241 0 : swap(local_size.surface_size.x,
242 : local_size.surface_size.y);
243 0 : swap(local_size.surface_size.width,
244 : local_size.surface_size.height);
245 0 : swap(local_size.chroma_size.x,
246 : local_size.chroma_size.y);
247 0 : swap(local_size.chroma_size.width,
248 : local_size.chroma_size.height);
249 : }
250 :
251 0 : value = 0;
252 0 : set_reg_field_value(value, local_size.surface_pitch,
253 : UNP_GRPH_PITCH_L, GRPH_PITCH_L);
254 :
255 0 : dm_write_reg(
256 : mem_input110->base.ctx,
257 : mmUNP_GRPH_PITCH_L,
258 : value);
259 :
260 0 : value = 0;
261 0 : set_reg_field_value(value, local_size.chroma_pitch,
262 : UNP_GRPH_PITCH_C, GRPH_PITCH_C);
263 0 : dm_write_reg(
264 : mem_input110->base.ctx,
265 : mmUNP_GRPH_PITCH_C,
266 : value);
267 :
268 0 : value = 0;
269 0 : set_reg_field_value(value, 0,
270 : UNP_GRPH_X_START_L, GRPH_X_START_L);
271 0 : dm_write_reg(
272 : mem_input110->base.ctx,
273 : mmUNP_GRPH_X_START_L,
274 : value);
275 :
276 0 : value = 0;
277 0 : set_reg_field_value(value, 0,
278 : UNP_GRPH_X_START_C, GRPH_X_START_C);
279 0 : dm_write_reg(
280 : mem_input110->base.ctx,
281 : mmUNP_GRPH_X_START_C,
282 : value);
283 :
284 0 : value = 0;
285 0 : set_reg_field_value(value, 0,
286 : UNP_GRPH_Y_START_L, GRPH_Y_START_L);
287 0 : dm_write_reg(
288 : mem_input110->base.ctx,
289 : mmUNP_GRPH_Y_START_L,
290 : value);
291 :
292 0 : value = 0;
293 0 : set_reg_field_value(value, 0,
294 : UNP_GRPH_Y_START_C, GRPH_Y_START_C);
295 0 : dm_write_reg(
296 : mem_input110->base.ctx,
297 : mmUNP_GRPH_Y_START_C,
298 : value);
299 :
300 0 : value = 0;
301 0 : set_reg_field_value(value, local_size.surface_size.x +
302 : local_size.surface_size.width,
303 : UNP_GRPH_X_END_L, GRPH_X_END_L);
304 0 : dm_write_reg(
305 : mem_input110->base.ctx,
306 : mmUNP_GRPH_X_END_L,
307 : value);
308 :
309 0 : value = 0;
310 0 : set_reg_field_value(value, local_size.chroma_size.x +
311 : local_size.chroma_size.width,
312 : UNP_GRPH_X_END_C, GRPH_X_END_C);
313 0 : dm_write_reg(
314 : mem_input110->base.ctx,
315 : mmUNP_GRPH_X_END_C,
316 : value);
317 :
318 0 : value = 0;
319 0 : set_reg_field_value(value, local_size.surface_size.y +
320 : local_size.surface_size.height,
321 : UNP_GRPH_Y_END_L, GRPH_Y_END_L);
322 0 : dm_write_reg(
323 : mem_input110->base.ctx,
324 : mmUNP_GRPH_Y_END_L,
325 : value);
326 :
327 0 : value = 0;
328 0 : set_reg_field_value(value, local_size.chroma_size.y +
329 : local_size.chroma_size.height,
330 : UNP_GRPH_Y_END_C, GRPH_Y_END_C);
331 0 : dm_write_reg(
332 : mem_input110->base.ctx,
333 : mmUNP_GRPH_Y_END_C,
334 : value);
335 :
336 0 : value = 0;
337 : switch (rotation) {
338 : case ROTATION_ANGLE_90:
339 : set_reg_field_value(value, 3,
340 : UNP_HW_ROTATION, ROTATION_ANGLE);
341 : break;
342 : case ROTATION_ANGLE_180:
343 : set_reg_field_value(value, 2,
344 : UNP_HW_ROTATION, ROTATION_ANGLE);
345 : break;
346 : case ROTATION_ANGLE_270:
347 : set_reg_field_value(value, 1,
348 : UNP_HW_ROTATION, ROTATION_ANGLE);
349 : break;
350 : default:
351 : set_reg_field_value(value, 0,
352 : UNP_HW_ROTATION, ROTATION_ANGLE);
353 : break;
354 : }
355 :
356 0 : dm_write_reg(
357 : mem_input110->base.ctx,
358 : mmUNP_HW_ROTATION,
359 : value);
360 0 : }
361 :
362 0 : static void program_pixel_format(
363 : struct dce_mem_input *mem_input110,
364 : enum surface_pixel_format format)
365 : {
366 0 : if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
367 : uint32_t value;
368 : uint8_t grph_depth;
369 : uint8_t grph_format;
370 :
371 0 : value = dm_read_reg(
372 : mem_input110->base.ctx,
373 : mmUNP_GRPH_CONTROL);
374 :
375 : switch (format) {
376 : case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
377 : grph_depth = 0;
378 : grph_format = 0;
379 : break;
380 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
381 : grph_depth = 1;
382 : grph_format = 1;
383 : break;
384 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
385 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
386 : grph_depth = 2;
387 : grph_format = 0;
388 : break;
389 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
390 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
391 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
392 : grph_depth = 2;
393 : grph_format = 1;
394 : break;
395 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
396 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
397 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
398 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
399 : grph_depth = 3;
400 : grph_format = 0;
401 : break;
402 : default:
403 : grph_depth = 2;
404 : grph_format = 0;
405 : break;
406 : }
407 :
408 0 : set_reg_field_value(
409 : value,
410 : grph_depth,
411 : UNP_GRPH_CONTROL,
412 : GRPH_DEPTH);
413 0 : set_reg_field_value(
414 : value,
415 : grph_format,
416 : UNP_GRPH_CONTROL,
417 : GRPH_FORMAT);
418 :
419 0 : dm_write_reg(
420 : mem_input110->base.ctx,
421 : mmUNP_GRPH_CONTROL,
422 : value);
423 :
424 0 : value = dm_read_reg(
425 : mem_input110->base.ctx,
426 : mmUNP_GRPH_CONTROL_EXP);
427 :
428 : /* VIDEO FORMAT 0 */
429 0 : set_reg_field_value(
430 : value,
431 : 0,
432 : UNP_GRPH_CONTROL_EXP,
433 : VIDEO_FORMAT);
434 0 : dm_write_reg(
435 : mem_input110->base.ctx,
436 : mmUNP_GRPH_CONTROL_EXP,
437 : value);
438 :
439 : } else {
440 : /* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
441 : uint32_t value;
442 : uint8_t video_format;
443 :
444 0 : value = dm_read_reg(
445 : mem_input110->base.ctx,
446 : mmUNP_GRPH_CONTROL_EXP);
447 :
448 0 : switch (format) {
449 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
450 : video_format = 2;
451 : break;
452 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
453 0 : video_format = 3;
454 : break;
455 : default:
456 0 : video_format = 0;
457 : break;
458 : }
459 :
460 0 : set_reg_field_value(
461 : value,
462 : video_format,
463 : UNP_GRPH_CONTROL_EXP,
464 : VIDEO_FORMAT);
465 :
466 0 : dm_write_reg(
467 : mem_input110->base.ctx,
468 : mmUNP_GRPH_CONTROL_EXP,
469 : value);
470 : }
471 0 : }
472 :
473 0 : static bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
474 : {
475 0 : struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
476 : uint32_t value;
477 :
478 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
479 :
480 0 : if (get_reg_field_value(value, UNP_GRPH_UPDATE,
481 : GRPH_SURFACE_UPDATE_PENDING))
482 : return true;
483 :
484 0 : mem_input->current_address = mem_input->request_address;
485 0 : return false;
486 : }
487 :
488 0 : static bool dce_mem_input_v_program_surface_flip_and_addr(
489 : struct mem_input *mem_input,
490 : const struct dc_plane_address *address,
491 : bool flip_immediate)
492 : {
493 0 : struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
494 :
495 0 : set_flip_control(mem_input110, flip_immediate);
496 0 : program_addr(mem_input110,
497 : address);
498 :
499 0 : mem_input->request_address = *address;
500 :
501 0 : return true;
502 : }
503 :
504 : /* Scatter Gather param tables */
505 : static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
506 : { 8, 64, 64, 8, 8, 1, 4, 0, 0},
507 : { 16, 64, 32, 8, 16, 1, 8, 0, 0},
508 : { 32, 32, 32, 16, 16, 1, 8, 0, 0},
509 : { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
510 : };
511 :
512 : static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
513 : { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */
514 : { 16, 256, 8, 2, 0, 1, 0, 0, 0},
515 : { 32, 128, 8, 4, 0, 1, 0, 0, 0},
516 : { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
517 : };
518 :
519 : static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
520 : { 8, 4096, 1, 8, 0, 1, 0, 0, 0},
521 : { 16, 2048, 1, 8, 0, 1, 0, 0, 0},
522 : { 32, 1024, 1, 8, 0, 1, 0, 0, 0},
523 : { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
524 : };
525 :
526 : /* Helper to get table entry from surface info */
527 0 : static const unsigned int *get_dvmm_hw_setting(
528 : union dc_tiling_info *tiling_info,
529 : enum surface_pixel_format format,
530 : bool chroma)
531 : {
532 : enum bits_per_pixel {
533 : bpp_8 = 0,
534 : bpp_16,
535 : bpp_32,
536 : bpp_64
537 : } bpp;
538 :
539 0 : if (format >= SURFACE_PIXEL_FORMAT_INVALID)
540 : bpp = bpp_32;
541 0 : else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
542 0 : bpp = chroma ? bpp_16 : bpp_8;
543 : else
544 : bpp = bpp_8;
545 :
546 0 : switch (tiling_info->gfx8.array_mode) {
547 : case DC_ARRAY_1D_TILED_THIN1:
548 : case DC_ARRAY_1D_TILED_THICK:
549 : case DC_ARRAY_PRT_TILED_THIN1:
550 0 : return dvmm_Hw_Setting_1DTiling[bpp];
551 : case DC_ARRAY_2D_TILED_THIN1:
552 : case DC_ARRAY_2D_TILED_THICK:
553 : case DC_ARRAY_2D_TILED_X_THICK:
554 : case DC_ARRAY_PRT_2D_TILED_THIN1:
555 : case DC_ARRAY_PRT_2D_TILED_THICK:
556 0 : return dvmm_Hw_Setting_2DTiling[bpp];
557 : case DC_ARRAY_LINEAR_GENERAL:
558 : case DC_ARRAY_LINEAR_ALLIGNED:
559 0 : return dvmm_Hw_Setting_Linear[bpp];
560 : default:
561 0 : return dvmm_Hw_Setting_2DTiling[bpp];
562 : }
563 : }
564 :
565 0 : static void dce_mem_input_v_program_pte_vm(
566 : struct mem_input *mem_input,
567 : enum surface_pixel_format format,
568 : union dc_tiling_info *tiling_info,
569 : enum dc_rotation_angle rotation)
570 : {
571 0 : struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
572 0 : const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
573 0 : const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
574 :
575 0 : unsigned int page_width = 0;
576 0 : unsigned int page_height = 0;
577 0 : unsigned int page_width_chroma = 0;
578 0 : unsigned int page_height_chroma = 0;
579 0 : unsigned int temp_page_width = pte[1];
580 0 : unsigned int temp_page_height = pte[2];
581 0 : unsigned int min_pte_before_flip = 0;
582 0 : unsigned int min_pte_before_flip_chroma = 0;
583 0 : uint32_t value = 0;
584 :
585 0 : while ((temp_page_width >>= 1) != 0)
586 0 : page_width++;
587 0 : while ((temp_page_height >>= 1) != 0)
588 0 : page_height++;
589 :
590 0 : temp_page_width = pte_chroma[1];
591 0 : temp_page_height = pte_chroma[2];
592 0 : while ((temp_page_width >>= 1) != 0)
593 0 : page_width_chroma++;
594 0 : while ((temp_page_height >>= 1) != 0)
595 0 : page_height_chroma++;
596 :
597 0 : switch (rotation) {
598 : case ROTATION_ANGLE_90:
599 : case ROTATION_ANGLE_270:
600 0 : min_pte_before_flip = pte[4];
601 0 : min_pte_before_flip_chroma = pte_chroma[4];
602 0 : break;
603 : default:
604 0 : min_pte_before_flip = pte[3];
605 0 : min_pte_before_flip_chroma = pte_chroma[3];
606 0 : break;
607 : }
608 :
609 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
610 : /* TODO: un-hardcode requestlimit */
611 0 : set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L);
612 0 : set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C);
613 0 : dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value);
614 :
615 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
616 0 : set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
617 0 : set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
618 0 : set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
619 0 : dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value);
620 :
621 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
622 0 : set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
623 0 : set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
624 0 : dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value);
625 :
626 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C);
627 0 : set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C);
628 0 : set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C);
629 0 : set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C);
630 0 : dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value);
631 :
632 0 : value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C);
633 0 : set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
634 0 : set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
635 0 : dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
636 0 : }
637 :
638 0 : static void dce_mem_input_v_program_surface_config(
639 : struct mem_input *mem_input,
640 : enum surface_pixel_format format,
641 : union dc_tiling_info *tiling_info,
642 : struct plane_size *plane_size,
643 : enum dc_rotation_angle rotation,
644 : struct dc_plane_dcc_param *dcc,
645 : bool horizotal_mirror)
646 : {
647 0 : struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
648 :
649 0 : enable(mem_input110);
650 0 : program_tiling(mem_input110, tiling_info, format);
651 0 : program_size_and_rotation(mem_input110, rotation, plane_size);
652 0 : program_pixel_format(mem_input110, format);
653 0 : }
654 :
655 0 : static void program_urgency_watermark(
656 : const struct dc_context *ctx,
657 : const uint32_t urgency_addr,
658 : const uint32_t wm_addr,
659 : struct dce_watermarks marks_low,
660 : uint32_t total_dest_line_time_ns)
661 : {
662 : /* register value */
663 0 : uint32_t urgency_cntl = 0;
664 0 : uint32_t wm_mask_cntl = 0;
665 :
666 : /*Write mask to enable reading/writing of watermark set A*/
667 0 : wm_mask_cntl = dm_read_reg(ctx, wm_addr);
668 0 : set_reg_field_value(wm_mask_cntl,
669 : 1,
670 : DPGV0_WATERMARK_MASK_CONTROL,
671 : URGENCY_WATERMARK_MASK);
672 0 : dm_write_reg(ctx, wm_addr, wm_mask_cntl);
673 :
674 0 : urgency_cntl = dm_read_reg(ctx, urgency_addr);
675 :
676 0 : set_reg_field_value(
677 : urgency_cntl,
678 : marks_low.a_mark,
679 : DPGV0_PIPE_URGENCY_CONTROL,
680 : URGENCY_LOW_WATERMARK);
681 :
682 0 : set_reg_field_value(
683 : urgency_cntl,
684 : total_dest_line_time_ns,
685 : DPGV0_PIPE_URGENCY_CONTROL,
686 : URGENCY_HIGH_WATERMARK);
687 0 : dm_write_reg(ctx, urgency_addr, urgency_cntl);
688 :
689 : /*Write mask to enable reading/writing of watermark set B*/
690 0 : wm_mask_cntl = dm_read_reg(ctx, wm_addr);
691 0 : set_reg_field_value(wm_mask_cntl,
692 : 2,
693 : DPGV0_WATERMARK_MASK_CONTROL,
694 : URGENCY_WATERMARK_MASK);
695 0 : dm_write_reg(ctx, wm_addr, wm_mask_cntl);
696 :
697 0 : urgency_cntl = dm_read_reg(ctx, urgency_addr);
698 :
699 0 : set_reg_field_value(urgency_cntl,
700 : marks_low.b_mark,
701 : DPGV0_PIPE_URGENCY_CONTROL,
702 : URGENCY_LOW_WATERMARK);
703 :
704 0 : set_reg_field_value(urgency_cntl,
705 : total_dest_line_time_ns,
706 : DPGV0_PIPE_URGENCY_CONTROL,
707 : URGENCY_HIGH_WATERMARK);
708 :
709 0 : dm_write_reg(ctx, urgency_addr, urgency_cntl);
710 0 : }
711 :
712 : static void program_urgency_watermark_l(
713 : const struct dc_context *ctx,
714 : struct dce_watermarks marks_low,
715 : uint32_t total_dest_line_time_ns)
716 : {
717 0 : program_urgency_watermark(
718 : ctx,
719 : mmDPGV0_PIPE_URGENCY_CONTROL,
720 : mmDPGV0_WATERMARK_MASK_CONTROL,
721 : marks_low,
722 : total_dest_line_time_ns);
723 : }
724 :
725 : static void program_urgency_watermark_c(
726 : const struct dc_context *ctx,
727 : struct dce_watermarks marks_low,
728 : uint32_t total_dest_line_time_ns)
729 : {
730 0 : program_urgency_watermark(
731 : ctx,
732 : mmDPGV1_PIPE_URGENCY_CONTROL,
733 : mmDPGV1_WATERMARK_MASK_CONTROL,
734 : marks_low,
735 : total_dest_line_time_ns);
736 : }
737 :
738 0 : static void program_stutter_watermark(
739 : const struct dc_context *ctx,
740 : const uint32_t stutter_addr,
741 : const uint32_t wm_addr,
742 : struct dce_watermarks marks)
743 : {
744 : /* register value */
745 0 : uint32_t stutter_cntl = 0;
746 0 : uint32_t wm_mask_cntl = 0;
747 :
748 : /*Write mask to enable reading/writing of watermark set A*/
749 :
750 0 : wm_mask_cntl = dm_read_reg(ctx, wm_addr);
751 0 : set_reg_field_value(wm_mask_cntl,
752 : 1,
753 : DPGV0_WATERMARK_MASK_CONTROL,
754 : STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
755 0 : dm_write_reg(ctx, wm_addr, wm_mask_cntl);
756 :
757 0 : stutter_cntl = dm_read_reg(ctx, stutter_addr);
758 :
759 0 : if (ctx->dc->debug.disable_stutter) {
760 0 : set_reg_field_value(stutter_cntl,
761 : 0,
762 : DPGV0_PIPE_STUTTER_CONTROL,
763 : STUTTER_ENABLE);
764 : } else {
765 0 : set_reg_field_value(stutter_cntl,
766 : 1,
767 : DPGV0_PIPE_STUTTER_CONTROL,
768 : STUTTER_ENABLE);
769 : }
770 :
771 0 : set_reg_field_value(stutter_cntl,
772 : 1,
773 : DPGV0_PIPE_STUTTER_CONTROL,
774 : STUTTER_IGNORE_FBC);
775 :
776 : /*Write watermark set A*/
777 0 : set_reg_field_value(stutter_cntl,
778 : marks.a_mark,
779 : DPGV0_PIPE_STUTTER_CONTROL,
780 : STUTTER_EXIT_SELF_REFRESH_WATERMARK);
781 0 : dm_write_reg(ctx, stutter_addr, stutter_cntl);
782 :
783 : /*Write mask to enable reading/writing of watermark set B*/
784 0 : wm_mask_cntl = dm_read_reg(ctx, wm_addr);
785 0 : set_reg_field_value(wm_mask_cntl,
786 : 2,
787 : DPGV0_WATERMARK_MASK_CONTROL,
788 : STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
789 0 : dm_write_reg(ctx, wm_addr, wm_mask_cntl);
790 :
791 0 : stutter_cntl = dm_read_reg(ctx, stutter_addr);
792 : /*Write watermark set B*/
793 0 : set_reg_field_value(stutter_cntl,
794 : marks.b_mark,
795 : DPGV0_PIPE_STUTTER_CONTROL,
796 : STUTTER_EXIT_SELF_REFRESH_WATERMARK);
797 0 : dm_write_reg(ctx, stutter_addr, stutter_cntl);
798 0 : }
799 :
800 : static void program_stutter_watermark_l(
801 : const struct dc_context *ctx,
802 : struct dce_watermarks marks)
803 : {
804 0 : program_stutter_watermark(ctx,
805 : mmDPGV0_PIPE_STUTTER_CONTROL,
806 : mmDPGV0_WATERMARK_MASK_CONTROL,
807 : marks);
808 : }
809 :
810 : static void program_stutter_watermark_c(
811 : const struct dc_context *ctx,
812 : struct dce_watermarks marks)
813 : {
814 0 : program_stutter_watermark(ctx,
815 : mmDPGV1_PIPE_STUTTER_CONTROL,
816 : mmDPGV1_WATERMARK_MASK_CONTROL,
817 : marks);
818 : }
819 :
820 0 : static void program_nbp_watermark(
821 : const struct dc_context *ctx,
822 : const uint32_t wm_mask_ctrl_addr,
823 : const uint32_t nbp_pstate_ctrl_addr,
824 : struct dce_watermarks marks)
825 : {
826 : uint32_t value;
827 :
828 : /* Write mask to enable reading/writing of watermark set A */
829 :
830 0 : value = dm_read_reg(ctx, wm_mask_ctrl_addr);
831 :
832 0 : set_reg_field_value(
833 : value,
834 : 1,
835 : DPGV0_WATERMARK_MASK_CONTROL,
836 : NB_PSTATE_CHANGE_WATERMARK_MASK);
837 0 : dm_write_reg(ctx, wm_mask_ctrl_addr, value);
838 :
839 0 : value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
840 :
841 0 : set_reg_field_value(
842 : value,
843 : 1,
844 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
845 : NB_PSTATE_CHANGE_ENABLE);
846 0 : set_reg_field_value(
847 : value,
848 : 1,
849 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
850 : NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
851 0 : set_reg_field_value(
852 : value,
853 : 1,
854 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
855 : NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
856 0 : dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
857 :
858 : /* Write watermark set A */
859 0 : value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
860 0 : set_reg_field_value(
861 : value,
862 : marks.a_mark,
863 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
864 : NB_PSTATE_CHANGE_WATERMARK);
865 0 : dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
866 :
867 : /* Write mask to enable reading/writing of watermark set B */
868 0 : value = dm_read_reg(ctx, wm_mask_ctrl_addr);
869 0 : set_reg_field_value(
870 : value,
871 : 2,
872 : DPGV0_WATERMARK_MASK_CONTROL,
873 : NB_PSTATE_CHANGE_WATERMARK_MASK);
874 0 : dm_write_reg(ctx, wm_mask_ctrl_addr, value);
875 :
876 0 : value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
877 0 : set_reg_field_value(
878 : value,
879 : 1,
880 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
881 : NB_PSTATE_CHANGE_ENABLE);
882 0 : set_reg_field_value(
883 : value,
884 : 1,
885 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
886 : NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
887 0 : set_reg_field_value(
888 : value,
889 : 1,
890 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
891 : NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
892 0 : dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
893 :
894 : /* Write watermark set B */
895 0 : value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
896 0 : set_reg_field_value(
897 : value,
898 : marks.b_mark,
899 : DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
900 : NB_PSTATE_CHANGE_WATERMARK);
901 0 : dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
902 0 : }
903 :
904 : static void program_nbp_watermark_l(
905 : const struct dc_context *ctx,
906 : struct dce_watermarks marks)
907 : {
908 0 : program_nbp_watermark(ctx,
909 : mmDPGV0_WATERMARK_MASK_CONTROL,
910 : mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
911 : marks);
912 : }
913 :
914 : static void program_nbp_watermark_c(
915 : const struct dc_context *ctx,
916 : struct dce_watermarks marks)
917 : {
918 0 : program_nbp_watermark(ctx,
919 : mmDPGV1_WATERMARK_MASK_CONTROL,
920 : mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL,
921 : marks);
922 : }
923 :
924 0 : static void dce_mem_input_v_program_display_marks(
925 : struct mem_input *mem_input,
926 : struct dce_watermarks nbp,
927 : struct dce_watermarks stutter,
928 : struct dce_watermarks stutter_enter,
929 : struct dce_watermarks urgent,
930 : uint32_t total_dest_line_time_ns)
931 : {
932 0 : program_urgency_watermark_l(
933 0 : mem_input->ctx,
934 : urgent,
935 : total_dest_line_time_ns);
936 :
937 0 : program_nbp_watermark_l(
938 0 : mem_input->ctx,
939 : nbp);
940 :
941 0 : program_stutter_watermark_l(
942 0 : mem_input->ctx,
943 : stutter);
944 :
945 0 : }
946 :
947 0 : static void dce_mem_input_program_chroma_display_marks(
948 : struct mem_input *mem_input,
949 : struct dce_watermarks nbp,
950 : struct dce_watermarks stutter,
951 : struct dce_watermarks urgent,
952 : uint32_t total_dest_line_time_ns)
953 : {
954 0 : program_urgency_watermark_c(
955 0 : mem_input->ctx,
956 : urgent,
957 : total_dest_line_time_ns);
958 :
959 0 : program_nbp_watermark_c(
960 0 : mem_input->ctx,
961 : nbp);
962 :
963 0 : program_stutter_watermark_c(
964 0 : mem_input->ctx,
965 : stutter);
966 0 : }
967 :
968 0 : static void dce110_allocate_mem_input_v(
969 : struct mem_input *mi,
970 : uint32_t h_total,/* for current stream */
971 : uint32_t v_total,/* for current stream */
972 : uint32_t pix_clk_khz,/* for current stream */
973 : uint32_t total_stream_num)
974 : {
975 : uint32_t addr;
976 : uint32_t value;
977 : uint32_t pix_dur;
978 0 : if (pix_clk_khz != 0) {
979 0 : addr = mmDPGV0_PIPE_ARBITRATION_CONTROL1;
980 0 : value = dm_read_reg(mi->ctx, addr);
981 0 : pix_dur = 1000000000ULL / pix_clk_khz;
982 0 : set_reg_field_value(
983 : value,
984 : pix_dur,
985 : DPGV0_PIPE_ARBITRATION_CONTROL1,
986 : PIXEL_DURATION);
987 0 : dm_write_reg(mi->ctx, addr, value);
988 :
989 0 : addr = mmDPGV1_PIPE_ARBITRATION_CONTROL1;
990 0 : value = dm_read_reg(mi->ctx, addr);
991 0 : pix_dur = 1000000000ULL / pix_clk_khz;
992 0 : set_reg_field_value(
993 : value,
994 : pix_dur,
995 : DPGV1_PIPE_ARBITRATION_CONTROL1,
996 : PIXEL_DURATION);
997 0 : dm_write_reg(mi->ctx, addr, value);
998 :
999 0 : addr = mmDPGV0_PIPE_ARBITRATION_CONTROL2;
1000 0 : value = 0x4000800;
1001 0 : dm_write_reg(mi->ctx, addr, value);
1002 :
1003 0 : addr = mmDPGV1_PIPE_ARBITRATION_CONTROL2;
1004 0 : value = 0x4000800;
1005 0 : dm_write_reg(mi->ctx, addr, value);
1006 : }
1007 :
1008 0 : }
1009 :
1010 0 : static void dce110_free_mem_input_v(
1011 : struct mem_input *mi,
1012 : uint32_t total_stream_num)
1013 : {
1014 0 : }
1015 :
1016 : static const struct mem_input_funcs dce110_mem_input_v_funcs = {
1017 : .mem_input_program_display_marks =
1018 : dce_mem_input_v_program_display_marks,
1019 : .mem_input_program_chroma_display_marks =
1020 : dce_mem_input_program_chroma_display_marks,
1021 : .allocate_mem_input = dce110_allocate_mem_input_v,
1022 : .free_mem_input = dce110_free_mem_input_v,
1023 : .mem_input_program_surface_flip_and_addr =
1024 : dce_mem_input_v_program_surface_flip_and_addr,
1025 : .mem_input_program_pte_vm =
1026 : dce_mem_input_v_program_pte_vm,
1027 : .mem_input_program_surface_config =
1028 : dce_mem_input_v_program_surface_config,
1029 : .mem_input_is_flip_pending =
1030 : dce_mem_input_v_is_surface_pending
1031 : };
1032 : /*****************************************/
1033 : /* Constructor, Destructor */
1034 : /*****************************************/
1035 :
1036 0 : void dce110_mem_input_v_construct(
1037 : struct dce_mem_input *dce_mi,
1038 : struct dc_context *ctx)
1039 : {
1040 0 : dce_mi->base.funcs = &dce110_mem_input_v_funcs;
1041 0 : dce_mi->base.ctx = ctx;
1042 0 : }
1043 :
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