Line data Source code
1 : /*
2 : * Copyright 2012-15 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "link_encoder.h"
29 : #include "stream_encoder.h"
30 :
31 : #include "resource.h"
32 : #include "dce110/dce110_resource.h"
33 : #include "include/irq_service_interface.h"
34 : #include "dce/dce_audio.h"
35 : #include "dce110/dce110_timing_generator.h"
36 : #include "irq/dce110/irq_service_dce110.h"
37 : #include "dce110/dce110_timing_generator_v.h"
38 : #include "dce/dce_link_encoder.h"
39 : #include "dce/dce_stream_encoder.h"
40 : #include "dce/dce_mem_input.h"
41 : #include "dce110/dce110_mem_input_v.h"
42 : #include "dce/dce_ipp.h"
43 : #include "dce/dce_transform.h"
44 : #include "dce110/dce110_transform_v.h"
45 : #include "dce/dce_opp.h"
46 : #include "dce110/dce110_opp_v.h"
47 : #include "dce/dce_clock_source.h"
48 : #include "dce/dce_hwseq.h"
49 : #include "dce110/dce110_hw_sequencer.h"
50 : #include "dce/dce_aux.h"
51 : #include "dce/dce_abm.h"
52 : #include "dce/dce_dmcu.h"
53 : #include "dce/dce_i2c.h"
54 : #include "dce/dce_panel_cntl.h"
55 :
56 : #define DC_LOGGER \
57 : dc->ctx->logger
58 :
59 : #include "dce110/dce110_compressor.h"
60 :
61 : #include "reg_helper.h"
62 :
63 : #include "dce/dce_11_0_d.h"
64 : #include "dce/dce_11_0_sh_mask.h"
65 :
66 : #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
67 : #include "gmc/gmc_8_2_d.h"
68 : #include "gmc/gmc_8_2_sh_mask.h"
69 : #endif
70 :
71 : #ifndef mmDP_DPHY_INTERNAL_CTRL
72 : #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
73 : #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
74 : #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
75 : #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
76 : #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
77 : #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
78 : #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
79 : #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
80 : #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
81 : #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
82 : #endif
83 :
84 : #ifndef mmBIOS_SCRATCH_2
85 : #define mmBIOS_SCRATCH_2 0x05CB
86 : #define mmBIOS_SCRATCH_3 0x05CC
87 : #define mmBIOS_SCRATCH_6 0x05CF
88 : #endif
89 :
90 : #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
91 : #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
92 : #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
93 : #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
94 : #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
95 : #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
96 : #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
97 : #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
98 : #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
99 : #endif
100 :
101 : #ifndef mmDP_DPHY_FAST_TRAINING
102 : #define mmDP_DPHY_FAST_TRAINING 0x4ABC
103 : #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
104 : #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
105 : #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
106 : #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
107 : #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
108 : #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
109 : #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
110 : #endif
111 :
112 : #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
113 : #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
114 : #endif
115 :
116 : static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
117 : {
118 : .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 : .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
120 : },
121 : {
122 : .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 : .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 : },
125 : {
126 : .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 : .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 : },
129 : {
130 : .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 : .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
132 : },
133 : {
134 : .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
135 : .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
136 : },
137 : {
138 : .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
139 : .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
140 : }
141 : };
142 :
143 : /* set register offset */
144 : #define SR(reg_name)\
145 : .reg_name = mm ## reg_name
146 :
147 : /* set register offset with instance */
148 : #define SRI(reg_name, block, id)\
149 : .reg_name = mm ## block ## id ## _ ## reg_name
150 :
151 : static const struct dce_dmcu_registers dmcu_regs = {
152 : DMCU_DCE110_COMMON_REG_LIST()
153 : };
154 :
155 : static const struct dce_dmcu_shift dmcu_shift = {
156 : DMCU_MASK_SH_LIST_DCE110(__SHIFT)
157 : };
158 :
159 : static const struct dce_dmcu_mask dmcu_mask = {
160 : DMCU_MASK_SH_LIST_DCE110(_MASK)
161 : };
162 :
163 : static const struct dce_abm_registers abm_regs = {
164 : ABM_DCE110_COMMON_REG_LIST()
165 : };
166 :
167 : static const struct dce_abm_shift abm_shift = {
168 : ABM_MASK_SH_LIST_DCE110(__SHIFT)
169 : };
170 :
171 : static const struct dce_abm_mask abm_mask = {
172 : ABM_MASK_SH_LIST_DCE110(_MASK)
173 : };
174 :
175 : #define ipp_regs(id)\
176 : [id] = {\
177 : IPP_DCE110_REG_LIST_DCE_BASE(id)\
178 : }
179 :
180 : static const struct dce_ipp_registers ipp_regs[] = {
181 : ipp_regs(0),
182 : ipp_regs(1),
183 : ipp_regs(2)
184 : };
185 :
186 : static const struct dce_ipp_shift ipp_shift = {
187 : IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
188 : };
189 :
190 : static const struct dce_ipp_mask ipp_mask = {
191 : IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
192 : };
193 :
194 : #define transform_regs(id)\
195 : [id] = {\
196 : XFM_COMMON_REG_LIST_DCE110(id)\
197 : }
198 :
199 : static const struct dce_transform_registers xfm_regs[] = {
200 : transform_regs(0),
201 : transform_regs(1),
202 : transform_regs(2)
203 : };
204 :
205 : static const struct dce_transform_shift xfm_shift = {
206 : XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
207 : };
208 :
209 : static const struct dce_transform_mask xfm_mask = {
210 : XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
211 : };
212 :
213 : #define aux_regs(id)\
214 : [id] = {\
215 : AUX_REG_LIST(id)\
216 : }
217 :
218 : static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
219 : aux_regs(0),
220 : aux_regs(1),
221 : aux_regs(2),
222 : aux_regs(3),
223 : aux_regs(4),
224 : aux_regs(5)
225 : };
226 :
227 : #define hpd_regs(id)\
228 : [id] = {\
229 : HPD_REG_LIST(id)\
230 : }
231 :
232 : static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
233 : hpd_regs(0),
234 : hpd_regs(1),
235 : hpd_regs(2),
236 : hpd_regs(3),
237 : hpd_regs(4),
238 : hpd_regs(5)
239 : };
240 :
241 :
242 : #define link_regs(id)\
243 : [id] = {\
244 : LE_DCE110_REG_LIST(id)\
245 : }
246 :
247 : static const struct dce110_link_enc_registers link_enc_regs[] = {
248 : link_regs(0),
249 : link_regs(1),
250 : link_regs(2),
251 : link_regs(3),
252 : link_regs(4),
253 : link_regs(5),
254 : link_regs(6),
255 : };
256 :
257 : #define stream_enc_regs(id)\
258 : [id] = {\
259 : SE_COMMON_REG_LIST(id),\
260 : .TMDS_CNTL = 0,\
261 : }
262 :
263 : static const struct dce110_stream_enc_registers stream_enc_regs[] = {
264 : stream_enc_regs(0),
265 : stream_enc_regs(1),
266 : stream_enc_regs(2)
267 : };
268 :
269 : static const struct dce_stream_encoder_shift se_shift = {
270 : SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
271 : };
272 :
273 : static const struct dce_stream_encoder_mask se_mask = {
274 : SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
275 : };
276 :
277 : static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
278 : { DCE_PANEL_CNTL_REG_LIST() }
279 : };
280 :
281 : static const struct dce_panel_cntl_shift panel_cntl_shift = {
282 : DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
283 : };
284 :
285 : static const struct dce_panel_cntl_mask panel_cntl_mask = {
286 : DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
287 : };
288 :
289 : static const struct dce110_aux_registers_shift aux_shift = {
290 : DCE_AUX_MASK_SH_LIST(__SHIFT)
291 : };
292 :
293 : static const struct dce110_aux_registers_mask aux_mask = {
294 : DCE_AUX_MASK_SH_LIST(_MASK)
295 : };
296 :
297 : #define opp_regs(id)\
298 : [id] = {\
299 : OPP_DCE_110_REG_LIST(id),\
300 : }
301 :
302 : static const struct dce_opp_registers opp_regs[] = {
303 : opp_regs(0),
304 : opp_regs(1),
305 : opp_regs(2),
306 : opp_regs(3),
307 : opp_regs(4),
308 : opp_regs(5)
309 : };
310 :
311 : static const struct dce_opp_shift opp_shift = {
312 : OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
313 : };
314 :
315 : static const struct dce_opp_mask opp_mask = {
316 : OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
317 : };
318 :
319 : #define aux_engine_regs(id)\
320 : [id] = {\
321 : AUX_COMMON_REG_LIST(id), \
322 : .AUX_RESET_MASK = 0 \
323 : }
324 :
325 : static const struct dce110_aux_registers aux_engine_regs[] = {
326 : aux_engine_regs(0),
327 : aux_engine_regs(1),
328 : aux_engine_regs(2),
329 : aux_engine_regs(3),
330 : aux_engine_regs(4),
331 : aux_engine_regs(5)
332 : };
333 :
334 : #define audio_regs(id)\
335 : [id] = {\
336 : AUD_COMMON_REG_LIST(id)\
337 : }
338 :
339 : static const struct dce_audio_registers audio_regs[] = {
340 : audio_regs(0),
341 : audio_regs(1),
342 : audio_regs(2),
343 : audio_regs(3),
344 : audio_regs(4),
345 : audio_regs(5),
346 : audio_regs(6),
347 : };
348 :
349 : static const struct dce_audio_shift audio_shift = {
350 : AUD_COMMON_MASK_SH_LIST(__SHIFT)
351 : };
352 :
353 : static const struct dce_audio_mask audio_mask = {
354 : AUD_COMMON_MASK_SH_LIST(_MASK)
355 : };
356 :
357 : /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
358 :
359 :
360 : #define clk_src_regs(id)\
361 : [id] = {\
362 : CS_COMMON_REG_LIST_DCE_100_110(id),\
363 : }
364 :
365 : static const struct dce110_clk_src_regs clk_src_regs[] = {
366 : clk_src_regs(0),
367 : clk_src_regs(1),
368 : clk_src_regs(2)
369 : };
370 :
371 : static const struct dce110_clk_src_shift cs_shift = {
372 : CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
373 : };
374 :
375 : static const struct dce110_clk_src_mask cs_mask = {
376 : CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
377 : };
378 :
379 : static const struct bios_registers bios_regs = {
380 : .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
381 : .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
382 : };
383 :
384 : static const struct resource_caps carrizo_resource_cap = {
385 : .num_timing_generator = 3,
386 : .num_video_plane = 1,
387 : .num_audio = 3,
388 : .num_stream_encoder = 3,
389 : .num_pll = 2,
390 : .num_ddc = 3,
391 : };
392 :
393 : static const struct resource_caps stoney_resource_cap = {
394 : .num_timing_generator = 2,
395 : .num_video_plane = 1,
396 : .num_audio = 3,
397 : .num_stream_encoder = 3,
398 : .num_pll = 2,
399 : .num_ddc = 3,
400 : };
401 :
402 : static const struct dc_plane_cap plane_cap = {
403 : .type = DC_PLANE_TYPE_DCE_RGB,
404 : .blends_with_below = true,
405 : .blends_with_above = true,
406 : .per_pixel_alpha = 1,
407 :
408 : .pixel_format_support = {
409 : .argb8888 = true,
410 : .nv12 = false,
411 : .fp16 = true
412 : },
413 :
414 : .max_upscale_factor = {
415 : .argb8888 = 16000,
416 : .nv12 = 1,
417 : .fp16 = 1
418 : },
419 :
420 : .max_downscale_factor = {
421 : .argb8888 = 250,
422 : .nv12 = 1,
423 : .fp16 = 1
424 : },
425 : 64,
426 : 64
427 : };
428 :
429 : static const struct dc_plane_cap underlay_plane_cap = {
430 : .type = DC_PLANE_TYPE_DCE_UNDERLAY,
431 : .blends_with_above = true,
432 : .per_pixel_alpha = 1,
433 :
434 : .pixel_format_support = {
435 : .argb8888 = false,
436 : .nv12 = true,
437 : .fp16 = false
438 : },
439 :
440 : .max_upscale_factor = {
441 : .argb8888 = 1,
442 : .nv12 = 16000,
443 : .fp16 = 1
444 : },
445 :
446 : .max_downscale_factor = {
447 : .argb8888 = 1,
448 : .nv12 = 250,
449 : .fp16 = 1
450 : },
451 : 64,
452 : 64
453 : };
454 :
455 : #define CTX ctx
456 : #define REG(reg) mm ## reg
457 :
458 : #ifndef mmCC_DC_HDMI_STRAPS
459 : #define mmCC_DC_HDMI_STRAPS 0x4819
460 : #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
461 : #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
462 : #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
463 : #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
464 : #endif
465 :
466 0 : static int map_transmitter_id_to_phy_instance(
467 : enum transmitter transmitter)
468 : {
469 0 : switch (transmitter) {
470 : case TRANSMITTER_UNIPHY_A:
471 : return 0;
472 : case TRANSMITTER_UNIPHY_B:
473 0 : return 1;
474 : case TRANSMITTER_UNIPHY_C:
475 0 : return 2;
476 : case TRANSMITTER_UNIPHY_D:
477 0 : return 3;
478 : case TRANSMITTER_UNIPHY_E:
479 0 : return 4;
480 : case TRANSMITTER_UNIPHY_F:
481 0 : return 5;
482 : case TRANSMITTER_UNIPHY_G:
483 0 : return 6;
484 : default:
485 0 : ASSERT(0);
486 : return 0;
487 : }
488 : }
489 :
490 0 : static void read_dce_straps(
491 : struct dc_context *ctx,
492 : struct resource_straps *straps)
493 : {
494 0 : REG_GET_2(CC_DC_HDMI_STRAPS,
495 : HDMI_DISABLE, &straps->hdmi_disable,
496 : AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
497 :
498 0 : REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
499 0 : }
500 :
501 0 : static struct audio *create_audio(
502 : struct dc_context *ctx, unsigned int inst)
503 : {
504 0 : return dce_audio_create(ctx, inst,
505 : &audio_regs[inst], &audio_shift, &audio_mask);
506 : }
507 :
508 0 : static struct timing_generator *dce110_timing_generator_create(
509 : struct dc_context *ctx,
510 : uint32_t instance,
511 : const struct dce110_timing_generator_offsets *offsets)
512 : {
513 0 : struct dce110_timing_generator *tg110 =
514 : kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
515 :
516 0 : if (!tg110)
517 : return NULL;
518 :
519 0 : dce110_timing_generator_construct(tg110, ctx, instance, offsets);
520 0 : return &tg110->base;
521 : }
522 :
523 0 : static struct stream_encoder *dce110_stream_encoder_create(
524 : enum engine_id eng_id,
525 : struct dc_context *ctx)
526 : {
527 0 : struct dce110_stream_encoder *enc110 =
528 : kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
529 :
530 0 : if (!enc110)
531 : return NULL;
532 :
533 0 : dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
534 : &stream_enc_regs[eng_id],
535 : &se_shift, &se_mask);
536 0 : return &enc110->base;
537 : }
538 :
539 : #define SRII(reg_name, block, id)\
540 : .reg_name[id] = mm ## block ## id ## _ ## reg_name
541 :
542 : static const struct dce_hwseq_registers hwseq_stoney_reg = {
543 : HWSEQ_ST_REG_LIST()
544 : };
545 :
546 : static const struct dce_hwseq_registers hwseq_cz_reg = {
547 : HWSEQ_CZ_REG_LIST()
548 : };
549 :
550 : static const struct dce_hwseq_shift hwseq_shift = {
551 : HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
552 : };
553 :
554 : static const struct dce_hwseq_mask hwseq_mask = {
555 : HWSEQ_DCE11_MASK_SH_LIST(_MASK),
556 : };
557 :
558 0 : static struct dce_hwseq *dce110_hwseq_create(
559 : struct dc_context *ctx)
560 : {
561 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
562 :
563 0 : if (hws) {
564 0 : hws->ctx = ctx;
565 0 : hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
566 0 : &hwseq_stoney_reg : &hwseq_cz_reg;
567 0 : hws->shifts = &hwseq_shift;
568 0 : hws->masks = &hwseq_mask;
569 0 : hws->wa.blnd_crtc_trigger = true;
570 : }
571 0 : return hws;
572 : }
573 :
574 : static const struct resource_create_funcs res_create_funcs = {
575 : .read_dce_straps = read_dce_straps,
576 : .create_audio = create_audio,
577 : .create_stream_encoder = dce110_stream_encoder_create,
578 : .create_hwseq = dce110_hwseq_create,
579 : };
580 :
581 : #define mi_inst_regs(id) { \
582 : MI_DCE11_REG_LIST(id), \
583 : .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
584 : }
585 : static const struct dce_mem_input_registers mi_regs[] = {
586 : mi_inst_regs(0),
587 : mi_inst_regs(1),
588 : mi_inst_regs(2),
589 : };
590 :
591 : static const struct dce_mem_input_shift mi_shifts = {
592 : MI_DCE11_MASK_SH_LIST(__SHIFT),
593 : .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
594 : };
595 :
596 : static const struct dce_mem_input_mask mi_masks = {
597 : MI_DCE11_MASK_SH_LIST(_MASK),
598 : .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
599 : };
600 :
601 :
602 0 : static struct mem_input *dce110_mem_input_create(
603 : struct dc_context *ctx,
604 : uint32_t inst)
605 : {
606 0 : struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
607 : GFP_KERNEL);
608 :
609 0 : if (!dce_mi) {
610 0 : BREAK_TO_DEBUGGER();
611 0 : return NULL;
612 : }
613 :
614 0 : dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
615 0 : dce_mi->wa.single_head_rdreq_dmif_limit = 3;
616 0 : return &dce_mi->base;
617 : }
618 :
619 : static void dce110_transform_destroy(struct transform **xfm)
620 : {
621 0 : kfree(TO_DCE_TRANSFORM(*xfm));
622 0 : *xfm = NULL;
623 : }
624 :
625 0 : static struct transform *dce110_transform_create(
626 : struct dc_context *ctx,
627 : uint32_t inst)
628 : {
629 0 : struct dce_transform *transform =
630 : kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
631 :
632 0 : if (!transform)
633 : return NULL;
634 :
635 0 : dce_transform_construct(transform, ctx, inst,
636 : &xfm_regs[inst], &xfm_shift, &xfm_mask);
637 0 : return &transform->base;
638 : }
639 :
640 0 : static struct input_pixel_processor *dce110_ipp_create(
641 : struct dc_context *ctx, uint32_t inst)
642 : {
643 0 : struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
644 :
645 0 : if (!ipp) {
646 0 : BREAK_TO_DEBUGGER();
647 0 : return NULL;
648 : }
649 :
650 0 : dce_ipp_construct(ipp, ctx, inst,
651 : &ipp_regs[inst], &ipp_shift, &ipp_mask);
652 0 : return &ipp->base;
653 : }
654 :
655 : static const struct encoder_feature_support link_enc_feature = {
656 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
657 : .max_hdmi_pixel_clock = 300000,
658 : .flags.bits.IS_HBR2_CAPABLE = true,
659 : .flags.bits.IS_TPS3_CAPABLE = true
660 : };
661 :
662 0 : static struct link_encoder *dce110_link_encoder_create(
663 : struct dc_context *ctx,
664 : const struct encoder_init_data *enc_init_data)
665 : {
666 0 : struct dce110_link_encoder *enc110 =
667 : kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
668 : int link_regs_id;
669 :
670 0 : if (!enc110)
671 : return NULL;
672 :
673 0 : link_regs_id =
674 0 : map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
675 :
676 0 : dce110_link_encoder_construct(enc110,
677 : enc_init_data,
678 : &link_enc_feature,
679 : &link_enc_regs[link_regs_id],
680 0 : &link_enc_aux_regs[enc_init_data->channel - 1],
681 0 : &link_enc_hpd_regs[enc_init_data->hpd_source]);
682 0 : return &enc110->base;
683 : }
684 :
685 0 : static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data)
686 : {
687 0 : struct dce_panel_cntl *panel_cntl =
688 : kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
689 :
690 0 : if (!panel_cntl)
691 : return NULL;
692 :
693 0 : dce_panel_cntl_construct(panel_cntl,
694 : init_data,
695 0 : &panel_cntl_regs[init_data->inst],
696 : &panel_cntl_shift,
697 : &panel_cntl_mask);
698 :
699 0 : return &panel_cntl->base;
700 : }
701 :
702 0 : static struct output_pixel_processor *dce110_opp_create(
703 : struct dc_context *ctx,
704 : uint32_t inst)
705 : {
706 0 : struct dce110_opp *opp =
707 : kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
708 :
709 0 : if (!opp)
710 : return NULL;
711 :
712 0 : dce110_opp_construct(opp,
713 : ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
714 0 : return &opp->base;
715 : }
716 :
717 0 : static struct dce_aux *dce110_aux_engine_create(
718 : struct dc_context *ctx,
719 : uint32_t inst)
720 : {
721 0 : struct aux_engine_dce110 *aux_engine =
722 : kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
723 :
724 0 : if (!aux_engine)
725 : return NULL;
726 :
727 0 : dce110_aux_engine_construct(aux_engine, ctx, inst,
728 : SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
729 : &aux_engine_regs[inst],
730 : &aux_mask,
731 : &aux_shift,
732 0 : ctx->dc->caps.extended_aux_timeout_support);
733 :
734 0 : return &aux_engine->base;
735 : }
736 : #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
737 :
738 : static const struct dce_i2c_registers i2c_hw_regs[] = {
739 : i2c_inst_regs(1),
740 : i2c_inst_regs(2),
741 : i2c_inst_regs(3),
742 : i2c_inst_regs(4),
743 : i2c_inst_regs(5),
744 : i2c_inst_regs(6),
745 : };
746 :
747 : static const struct dce_i2c_shift i2c_shifts = {
748 : I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
749 : };
750 :
751 : static const struct dce_i2c_mask i2c_masks = {
752 : I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
753 : };
754 :
755 0 : static struct dce_i2c_hw *dce110_i2c_hw_create(
756 : struct dc_context *ctx,
757 : uint32_t inst)
758 : {
759 0 : struct dce_i2c_hw *dce_i2c_hw =
760 : kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
761 :
762 0 : if (!dce_i2c_hw)
763 : return NULL;
764 :
765 0 : dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
766 : &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
767 :
768 0 : return dce_i2c_hw;
769 : }
770 0 : static struct clock_source *dce110_clock_source_create(
771 : struct dc_context *ctx,
772 : struct dc_bios *bios,
773 : enum clock_source_id id,
774 : const struct dce110_clk_src_regs *regs,
775 : bool dp_clk_src)
776 : {
777 0 : struct dce110_clk_src *clk_src =
778 : kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
779 :
780 0 : if (!clk_src)
781 : return NULL;
782 :
783 0 : if (dce110_clk_src_construct(clk_src, ctx, bios, id,
784 : regs, &cs_shift, &cs_mask)) {
785 0 : clk_src->base.dp_clk_src = dp_clk_src;
786 0 : return &clk_src->base;
787 : }
788 :
789 0 : kfree(clk_src);
790 0 : BREAK_TO_DEBUGGER();
791 0 : return NULL;
792 : }
793 :
794 0 : static void dce110_clock_source_destroy(struct clock_source **clk_src)
795 : {
796 : struct dce110_clk_src *dce110_clk_src;
797 :
798 0 : if (!clk_src)
799 : return;
800 :
801 0 : dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
802 :
803 0 : kfree(dce110_clk_src->dp_ss_params);
804 0 : kfree(dce110_clk_src->hdmi_ss_params);
805 0 : kfree(dce110_clk_src->dvi_ss_params);
806 :
807 0 : kfree(dce110_clk_src);
808 0 : *clk_src = NULL;
809 : }
810 :
811 0 : static void dce110_resource_destruct(struct dce110_resource_pool *pool)
812 : {
813 : unsigned int i;
814 :
815 0 : for (i = 0; i < pool->base.pipe_count; i++) {
816 0 : if (pool->base.opps[i] != NULL)
817 0 : dce110_opp_destroy(&pool->base.opps[i]);
818 :
819 0 : if (pool->base.transforms[i] != NULL)
820 0 : dce110_transform_destroy(&pool->base.transforms[i]);
821 :
822 0 : if (pool->base.ipps[i] != NULL)
823 0 : dce_ipp_destroy(&pool->base.ipps[i]);
824 :
825 0 : if (pool->base.mis[i] != NULL) {
826 0 : kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
827 0 : pool->base.mis[i] = NULL;
828 : }
829 :
830 0 : if (pool->base.timing_generators[i] != NULL) {
831 0 : kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
832 0 : pool->base.timing_generators[i] = NULL;
833 : }
834 : }
835 :
836 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
837 0 : if (pool->base.engines[i] != NULL)
838 0 : dce110_engine_destroy(&pool->base.engines[i]);
839 0 : if (pool->base.hw_i2cs[i] != NULL) {
840 0 : kfree(pool->base.hw_i2cs[i]);
841 0 : pool->base.hw_i2cs[i] = NULL;
842 : }
843 0 : if (pool->base.sw_i2cs[i] != NULL) {
844 0 : kfree(pool->base.sw_i2cs[i]);
845 0 : pool->base.sw_i2cs[i] = NULL;
846 : }
847 : }
848 :
849 0 : for (i = 0; i < pool->base.stream_enc_count; i++) {
850 0 : if (pool->base.stream_enc[i] != NULL)
851 0 : kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
852 : }
853 :
854 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
855 0 : if (pool->base.clock_sources[i] != NULL) {
856 0 : dce110_clock_source_destroy(&pool->base.clock_sources[i]);
857 : }
858 : }
859 :
860 0 : if (pool->base.dp_clock_source != NULL)
861 0 : dce110_clock_source_destroy(&pool->base.dp_clock_source);
862 :
863 0 : for (i = 0; i < pool->base.audio_count; i++) {
864 0 : if (pool->base.audios[i] != NULL) {
865 0 : dce_aud_destroy(&pool->base.audios[i]);
866 : }
867 : }
868 :
869 0 : if (pool->base.abm != NULL)
870 0 : dce_abm_destroy(&pool->base.abm);
871 :
872 0 : if (pool->base.dmcu != NULL)
873 0 : dce_dmcu_destroy(&pool->base.dmcu);
874 :
875 0 : if (pool->base.irqs != NULL) {
876 0 : dal_irq_service_destroy(&pool->base.irqs);
877 : }
878 0 : }
879 :
880 :
881 0 : static void get_pixel_clock_parameters(
882 : const struct pipe_ctx *pipe_ctx,
883 : struct pixel_clk_params *pixel_clk_params)
884 : {
885 0 : const struct dc_stream_state *stream = pipe_ctx->stream;
886 :
887 : /*TODO: is this halved for YCbCr 420? in that case we might want to move
888 : * the pixel clock normalization for hdmi up to here instead of doing it
889 : * in pll_adjust_pix_clk
890 : */
891 0 : pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
892 0 : pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
893 0 : pixel_clk_params->signal_type = pipe_ctx->stream->signal;
894 0 : pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
895 : /* TODO: un-hardcode*/
896 0 : pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
897 : LINK_RATE_REF_FREQ_IN_KHZ;
898 0 : pixel_clk_params->flags.ENABLE_SS = 0;
899 0 : pixel_clk_params->color_depth =
900 0 : stream->timing.display_color_depth;
901 0 : pixel_clk_params->flags.DISPLAY_BLANKED = 1;
902 0 : pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
903 : PIXEL_ENCODING_YCBCR420);
904 0 : pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
905 0 : if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
906 0 : pixel_clk_params->color_depth = COLOR_DEPTH_888;
907 : }
908 0 : if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
909 0 : pixel_clk_params->requested_pix_clk_100hz = pixel_clk_params->requested_pix_clk_100hz / 2;
910 : }
911 0 : if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
912 0 : pixel_clk_params->requested_pix_clk_100hz *= 2;
913 :
914 0 : }
915 :
916 0 : void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
917 : {
918 0 : get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
919 0 : pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
920 : pipe_ctx->clock_source,
921 : &pipe_ctx->stream_res.pix_clk_params,
922 : &pipe_ctx->pll_settings);
923 0 : resource_build_bit_depth_reduction_params(pipe_ctx->stream,
924 0 : &pipe_ctx->stream->bit_depth_params);
925 0 : pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
926 0 : }
927 :
928 : static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
929 : {
930 0 : if (pipe_ctx->pipe_idx != underlay_idx)
931 : return true;
932 0 : if (!pipe_ctx->plane_state)
933 : return false;
934 0 : if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
935 : return false;
936 : return true;
937 : }
938 :
939 0 : static enum dc_status build_mapped_resource(
940 : const struct dc *dc,
941 : struct dc_state *context,
942 : struct dc_stream_state *stream)
943 : {
944 0 : struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
945 :
946 0 : if (!pipe_ctx)
947 : return DC_ERROR_UNEXPECTED;
948 :
949 0 : if (!is_surface_pixel_format_supported(pipe_ctx,
950 0 : dc->res_pool->underlay_pipe_index))
951 : return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
952 :
953 0 : dce110_resource_build_pipe_hw_param(pipe_ctx);
954 :
955 : /* TODO: validate audio ASIC caps, encoder */
956 :
957 0 : resource_build_info_frame(pipe_ctx);
958 :
959 : return DC_OK;
960 : }
961 :
962 0 : static bool dce110_validate_bandwidth(
963 : struct dc *dc,
964 : struct dc_state *context,
965 : bool fast_validate)
966 : {
967 0 : bool result = false;
968 :
969 : DC_LOG_BANDWIDTH_CALCS(
970 : "%s: start",
971 : __func__);
972 :
973 0 : if (bw_calcs(
974 : dc->ctx,
975 0 : dc->bw_dceip,
976 0 : dc->bw_vbios,
977 0 : context->res_ctx.pipe_ctx,
978 0 : dc->res_pool->pipe_count,
979 : &context->bw_ctx.bw.dce))
980 0 : result = true;
981 :
982 0 : if (!result)
983 0 : DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
984 : __func__,
985 : context->streams[0]->timing.h_addressable,
986 : context->streams[0]->timing.v_addressable,
987 : context->streams[0]->timing.pix_clk_100hz / 10);
988 :
989 0 : if (memcmp(&dc->current_state->bw_ctx.bw.dce,
990 : &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
991 :
992 : DC_LOG_BANDWIDTH_CALCS(
993 : "%s: finish,\n"
994 : "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
995 : "stutMark_b: %d stutMark_a: %d\n"
996 : "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
997 : "stutMark_b: %d stutMark_a: %d\n"
998 : "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
999 : "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
1000 : "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
1001 : "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
1002 : ,
1003 : __func__,
1004 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
1005 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
1006 : context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
1007 : context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
1008 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
1009 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
1010 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
1011 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
1012 : context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
1013 : context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
1014 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
1015 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
1016 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
1017 : context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
1018 : context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
1019 : context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
1020 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
1021 : context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
1022 : context->bw_ctx.bw.dce.stutter_mode_enable,
1023 : context->bw_ctx.bw.dce.cpuc_state_change_enable,
1024 : context->bw_ctx.bw.dce.cpup_state_change_enable,
1025 : context->bw_ctx.bw.dce.nbp_state_change_enable,
1026 : context->bw_ctx.bw.dce.all_displays_in_sync,
1027 : context->bw_ctx.bw.dce.dispclk_khz,
1028 : context->bw_ctx.bw.dce.sclk_khz,
1029 : context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1030 : context->bw_ctx.bw.dce.yclk_khz,
1031 : context->bw_ctx.bw.dce.blackout_recovery_time_us);
1032 : }
1033 0 : return result;
1034 : }
1035 :
1036 0 : static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
1037 : struct dc_caps *caps)
1038 : {
1039 0 : if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
1040 0 : ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
1041 : return DC_FAIL_SURFACE_VALIDATE;
1042 :
1043 0 : return DC_OK;
1044 : }
1045 :
1046 0 : static bool dce110_validate_surface_sets(
1047 : struct dc_state *context)
1048 : {
1049 : int i, j;
1050 :
1051 0 : for (i = 0; i < context->stream_count; i++) {
1052 0 : if (context->stream_status[i].plane_count == 0)
1053 0 : continue;
1054 :
1055 0 : if (context->stream_status[i].plane_count > 2)
1056 : return false;
1057 :
1058 0 : for (j = 0; j < context->stream_status[i].plane_count; j++) {
1059 0 : struct dc_plane_state *plane =
1060 : context->stream_status[i].plane_states[j];
1061 :
1062 : /* underlay validation */
1063 0 : if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1064 :
1065 0 : if ((plane->src_rect.width > 1920 ||
1066 0 : plane->src_rect.height > 1080))
1067 : return false;
1068 :
1069 : /* we don't have the logic to support underlay
1070 : * only yet so block the use case where we get
1071 : * NV12 plane as top layer
1072 : */
1073 0 : if (j == 0)
1074 : return false;
1075 :
1076 : /* irrespective of plane format,
1077 : * stream should be RGB encoded
1078 : */
1079 0 : if (context->streams[i]->timing.pixel_encoding
1080 : != PIXEL_ENCODING_RGB)
1081 : return false;
1082 :
1083 : }
1084 :
1085 : }
1086 : }
1087 :
1088 : return true;
1089 : }
1090 :
1091 0 : static enum dc_status dce110_validate_global(
1092 : struct dc *dc,
1093 : struct dc_state *context)
1094 : {
1095 0 : if (!dce110_validate_surface_sets(context))
1096 : return DC_FAIL_SURFACE_VALIDATE;
1097 :
1098 0 : return DC_OK;
1099 : }
1100 :
1101 0 : static enum dc_status dce110_add_stream_to_ctx(
1102 : struct dc *dc,
1103 : struct dc_state *new_ctx,
1104 : struct dc_stream_state *dc_stream)
1105 : {
1106 0 : enum dc_status result = DC_ERROR_UNEXPECTED;
1107 :
1108 0 : result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1109 :
1110 0 : if (result == DC_OK)
1111 0 : result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1112 :
1113 :
1114 0 : if (result == DC_OK)
1115 0 : result = build_mapped_resource(dc, new_ctx, dc_stream);
1116 :
1117 0 : return result;
1118 : }
1119 :
1120 0 : static struct pipe_ctx *dce110_acquire_underlay(
1121 : struct dc_state *context,
1122 : const struct resource_pool *pool,
1123 : struct dc_stream_state *stream)
1124 : {
1125 0 : struct dc *dc = stream->ctx->dc;
1126 0 : struct dce_hwseq *hws = dc->hwseq;
1127 0 : struct resource_context *res_ctx = &context->res_ctx;
1128 0 : unsigned int underlay_idx = pool->underlay_pipe_index;
1129 0 : struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1130 :
1131 0 : if (res_ctx->pipe_ctx[underlay_idx].stream)
1132 : return NULL;
1133 :
1134 0 : pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1135 0 : pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1136 : /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1137 0 : pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1138 0 : pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1139 0 : pipe_ctx->pipe_idx = underlay_idx;
1140 :
1141 0 : pipe_ctx->stream = stream;
1142 :
1143 0 : if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
1144 0 : struct tg_color black_color = {0};
1145 0 : struct dc_bios *dcb = dc->ctx->dc_bios;
1146 :
1147 0 : hws->funcs.enable_display_power_gating(
1148 : dc,
1149 0 : pipe_ctx->stream_res.tg->inst,
1150 : dcb, PIPE_GATING_CONTROL_DISABLE);
1151 :
1152 : /*
1153 : * This is for powering on underlay, so crtc does not
1154 : * need to be enabled
1155 : */
1156 :
1157 0 : pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1158 0 : &stream->timing,
1159 : 0,
1160 : 0,
1161 : 0,
1162 : 0,
1163 0 : pipe_ctx->stream->signal,
1164 : false);
1165 :
1166 0 : pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1167 : pipe_ctx->stream_res.tg,
1168 : true,
1169 : &stream->timing);
1170 :
1171 0 : pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1172 : stream->timing.h_total,
1173 : stream->timing.v_total,
1174 0 : stream->timing.pix_clk_100hz / 10,
1175 0 : context->stream_count);
1176 :
1177 0 : color_space_to_black_color(dc,
1178 : COLOR_SPACE_YCBCR601, &black_color);
1179 0 : pipe_ctx->stream_res.tg->funcs->set_blank_color(
1180 : pipe_ctx->stream_res.tg,
1181 : &black_color);
1182 : }
1183 :
1184 : return pipe_ctx;
1185 : }
1186 :
1187 0 : static void dce110_destroy_resource_pool(struct resource_pool **pool)
1188 : {
1189 0 : struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1190 :
1191 0 : dce110_resource_destruct(dce110_pool);
1192 0 : kfree(dce110_pool);
1193 0 : *pool = NULL;
1194 0 : }
1195 :
1196 0 : struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1197 : struct resource_context *res_ctx,
1198 : const struct resource_pool *pool,
1199 : struct dc_stream_state *stream)
1200 : {
1201 : int i;
1202 0 : int j = -1;
1203 0 : struct dc_link *link = stream->link;
1204 :
1205 0 : for (i = 0; i < pool->stream_enc_count; i++) {
1206 0 : if (!res_ctx->is_stream_enc_acquired[i] &&
1207 0 : pool->stream_enc[i]) {
1208 : /* Store first available for MST second display
1209 : * in daisy chain use case
1210 : */
1211 0 : j = i;
1212 0 : if (pool->stream_enc[i]->id ==
1213 0 : link->link_enc->preferred_engine)
1214 : return pool->stream_enc[i];
1215 : }
1216 : }
1217 :
1218 : /*
1219 : * For CZ and later, we can allow DIG FE and BE to differ for all display types
1220 : */
1221 :
1222 0 : if (j >= 0)
1223 0 : return pool->stream_enc[j];
1224 :
1225 : return NULL;
1226 : }
1227 :
1228 :
1229 : static const struct resource_funcs dce110_res_pool_funcs = {
1230 : .destroy = dce110_destroy_resource_pool,
1231 : .link_enc_create = dce110_link_encoder_create,
1232 : .panel_cntl_create = dce110_panel_cntl_create,
1233 : .validate_bandwidth = dce110_validate_bandwidth,
1234 : .validate_plane = dce110_validate_plane,
1235 : .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1236 : .add_stream_to_ctx = dce110_add_stream_to_ctx,
1237 : .validate_global = dce110_validate_global,
1238 : .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1239 : };
1240 :
1241 0 : static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1242 : {
1243 0 : struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1244 : GFP_KERNEL);
1245 0 : struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1246 : GFP_KERNEL);
1247 0 : struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1248 : GFP_KERNEL);
1249 0 : struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1250 : GFP_KERNEL);
1251 :
1252 0 : if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1253 0 : kfree(dce110_tgv);
1254 0 : kfree(dce110_xfmv);
1255 0 : kfree(dce110_miv);
1256 0 : kfree(dce110_oppv);
1257 0 : return false;
1258 : }
1259 :
1260 0 : dce110_opp_v_construct(dce110_oppv, ctx);
1261 :
1262 0 : dce110_timing_generator_v_construct(dce110_tgv, ctx);
1263 0 : dce110_mem_input_v_construct(dce110_miv, ctx);
1264 0 : dce110_transform_v_construct(dce110_xfmv, ctx);
1265 :
1266 0 : pool->opps[pool->pipe_count] = &dce110_oppv->base;
1267 0 : pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1268 0 : pool->mis[pool->pipe_count] = &dce110_miv->base;
1269 0 : pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1270 0 : pool->pipe_count++;
1271 :
1272 : /* update the public caps to indicate an underlay is available */
1273 0 : ctx->dc->caps.max_slave_planes = 1;
1274 0 : ctx->dc->caps.max_slave_yuv_planes = 1;
1275 0 : ctx->dc->caps.max_slave_rgb_planes = 0;
1276 :
1277 0 : return true;
1278 : }
1279 :
1280 0 : static void bw_calcs_data_update_from_pplib(struct dc *dc)
1281 : {
1282 0 : struct dm_pp_clock_levels clks = {0};
1283 :
1284 : /*do system clock*/
1285 0 : dm_pp_get_clock_levels_by_type(
1286 0 : dc->ctx,
1287 : DM_PP_CLOCK_TYPE_ENGINE_CLK,
1288 : &clks);
1289 : /* convert all the clock fro kHz to fix point mHz */
1290 0 : dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1291 0 : clks.clocks_in_khz[clks.num_levels-1], 1000);
1292 0 : dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
1293 0 : clks.clocks_in_khz[clks.num_levels/8], 1000);
1294 0 : dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
1295 0 : clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1296 0 : dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
1297 0 : clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1298 0 : dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
1299 0 : clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1300 0 : dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
1301 0 : clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1302 0 : dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
1303 0 : clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1304 0 : dc->bw_vbios->low_sclk = bw_frc_to_fixed(
1305 0 : clks.clocks_in_khz[0], 1000);
1306 0 : dc->sclk_lvls = clks;
1307 :
1308 : /*do display clock*/
1309 0 : dm_pp_get_clock_levels_by_type(
1310 0 : dc->ctx,
1311 : DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1312 : &clks);
1313 0 : dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1314 0 : clks.clocks_in_khz[clks.num_levels-1], 1000);
1315 0 : dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed(
1316 0 : clks.clocks_in_khz[clks.num_levels>>1], 1000);
1317 0 : dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed(
1318 0 : clks.clocks_in_khz[0], 1000);
1319 :
1320 : /*do memory clock*/
1321 0 : dm_pp_get_clock_levels_by_type(
1322 0 : dc->ctx,
1323 : DM_PP_CLOCK_TYPE_MEMORY_CLK,
1324 : &clks);
1325 :
1326 0 : dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1327 0 : clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1328 0 : dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1329 0 : clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1330 : 1000);
1331 0 : dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1332 0 : clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1333 : 1000);
1334 0 : }
1335 :
1336 : static const struct resource_caps *dce110_resource_cap(
1337 : struct hw_asic_id *asic_id)
1338 : {
1339 0 : if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1340 : return &stoney_resource_cap;
1341 : else
1342 : return &carrizo_resource_cap;
1343 : }
1344 :
1345 0 : static bool dce110_resource_construct(
1346 : uint8_t num_virtual_links,
1347 : struct dc *dc,
1348 : struct dce110_resource_pool *pool,
1349 : struct hw_asic_id asic_id)
1350 : {
1351 : unsigned int i;
1352 0 : struct dc_context *ctx = dc->ctx;
1353 : struct dc_bios *bp;
1354 :
1355 0 : ctx->dc_bios->regs = &bios_regs;
1356 :
1357 0 : pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1358 0 : pool->base.funcs = &dce110_res_pool_funcs;
1359 :
1360 : /*************************************************
1361 : * Resource + asic cap harcoding *
1362 : *************************************************/
1363 :
1364 0 : pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1365 0 : pool->base.underlay_pipe_index = pool->base.pipe_count;
1366 0 : pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1367 0 : dc->caps.max_downscale_ratio = 150;
1368 0 : dc->caps.i2c_speed_in_khz = 40;
1369 0 : dc->caps.i2c_speed_in_khz_hdcp = 40;
1370 0 : dc->caps.max_cursor_size = 128;
1371 0 : dc->caps.min_horizontal_blanking_period = 80;
1372 0 : dc->caps.is_apu = true;
1373 0 : dc->caps.extended_aux_timeout_support = false;
1374 :
1375 : /*************************************************
1376 : * Create resources *
1377 : *************************************************/
1378 :
1379 0 : bp = ctx->dc_bios;
1380 :
1381 0 : if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1382 0 : pool->base.dp_clock_source =
1383 0 : dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1384 :
1385 0 : pool->base.clock_sources[0] =
1386 0 : dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1387 : &clk_src_regs[0], false);
1388 0 : pool->base.clock_sources[1] =
1389 0 : dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1390 : &clk_src_regs[1], false);
1391 :
1392 0 : pool->base.clk_src_count = 2;
1393 :
1394 : /* TODO: find out if CZ support 3 PLLs */
1395 : }
1396 :
1397 0 : if (pool->base.dp_clock_source == NULL) {
1398 0 : dm_error("DC: failed to create dp clock source!\n");
1399 0 : BREAK_TO_DEBUGGER();
1400 0 : goto res_create_fail;
1401 : }
1402 :
1403 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1404 0 : if (pool->base.clock_sources[i] == NULL) {
1405 0 : dm_error("DC: failed to create clock sources!\n");
1406 0 : BREAK_TO_DEBUGGER();
1407 0 : goto res_create_fail;
1408 : }
1409 : }
1410 :
1411 0 : pool->base.dmcu = dce_dmcu_create(ctx,
1412 : &dmcu_regs,
1413 : &dmcu_shift,
1414 : &dmcu_mask);
1415 0 : if (pool->base.dmcu == NULL) {
1416 0 : dm_error("DC: failed to create dmcu!\n");
1417 0 : BREAK_TO_DEBUGGER();
1418 0 : goto res_create_fail;
1419 : }
1420 :
1421 0 : pool->base.abm = dce_abm_create(ctx,
1422 : &abm_regs,
1423 : &abm_shift,
1424 : &abm_mask);
1425 0 : if (pool->base.abm == NULL) {
1426 0 : dm_error("DC: failed to create abm!\n");
1427 0 : BREAK_TO_DEBUGGER();
1428 0 : goto res_create_fail;
1429 : }
1430 :
1431 : {
1432 : struct irq_service_init_data init_data;
1433 0 : init_data.ctx = dc->ctx;
1434 0 : pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1435 0 : if (!pool->base.irqs)
1436 : goto res_create_fail;
1437 : }
1438 :
1439 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1440 0 : pool->base.timing_generators[i] = dce110_timing_generator_create(
1441 : ctx, i, &dce110_tg_offsets[i]);
1442 0 : if (pool->base.timing_generators[i] == NULL) {
1443 0 : BREAK_TO_DEBUGGER();
1444 0 : dm_error("DC: failed to create tg!\n");
1445 0 : goto res_create_fail;
1446 : }
1447 :
1448 0 : pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1449 0 : if (pool->base.mis[i] == NULL) {
1450 0 : BREAK_TO_DEBUGGER();
1451 0 : dm_error(
1452 : "DC: failed to create memory input!\n");
1453 0 : goto res_create_fail;
1454 : }
1455 :
1456 0 : pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1457 0 : if (pool->base.ipps[i] == NULL) {
1458 0 : BREAK_TO_DEBUGGER();
1459 0 : dm_error(
1460 : "DC: failed to create input pixel processor!\n");
1461 0 : goto res_create_fail;
1462 : }
1463 :
1464 0 : pool->base.transforms[i] = dce110_transform_create(ctx, i);
1465 0 : if (pool->base.transforms[i] == NULL) {
1466 0 : BREAK_TO_DEBUGGER();
1467 0 : dm_error(
1468 : "DC: failed to create transform!\n");
1469 0 : goto res_create_fail;
1470 : }
1471 :
1472 0 : pool->base.opps[i] = dce110_opp_create(ctx, i);
1473 0 : if (pool->base.opps[i] == NULL) {
1474 0 : BREAK_TO_DEBUGGER();
1475 0 : dm_error(
1476 : "DC: failed to create output pixel processor!\n");
1477 0 : goto res_create_fail;
1478 : }
1479 : }
1480 :
1481 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1482 0 : pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1483 0 : if (pool->base.engines[i] == NULL) {
1484 0 : BREAK_TO_DEBUGGER();
1485 0 : dm_error(
1486 : "DC:failed to create aux engine!!\n");
1487 0 : goto res_create_fail;
1488 : }
1489 0 : pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1490 0 : if (pool->base.hw_i2cs[i] == NULL) {
1491 0 : BREAK_TO_DEBUGGER();
1492 0 : dm_error(
1493 : "DC:failed to create i2c engine!!\n");
1494 0 : goto res_create_fail;
1495 : }
1496 0 : pool->base.sw_i2cs[i] = NULL;
1497 : }
1498 :
1499 0 : if (dc->config.fbc_support)
1500 0 : dc->fbc_compressor = dce110_compressor_create(ctx);
1501 :
1502 0 : if (!underlay_create(ctx, &pool->base))
1503 : goto res_create_fail;
1504 :
1505 0 : if (!resource_construct(num_virtual_links, dc, &pool->base,
1506 : &res_create_funcs))
1507 : goto res_create_fail;
1508 :
1509 : /* Create hardware sequencer */
1510 0 : dce110_hw_sequencer_construct(dc);
1511 :
1512 0 : dc->caps.max_planes = pool->base.pipe_count;
1513 :
1514 0 : for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1515 0 : dc->caps.planes[i] = plane_cap;
1516 :
1517 0 : dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1518 :
1519 0 : bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1520 :
1521 0 : bw_calcs_data_update_from_pplib(dc);
1522 :
1523 0 : return true;
1524 :
1525 : res_create_fail:
1526 0 : dce110_resource_destruct(pool);
1527 0 : return false;
1528 : }
1529 :
1530 0 : struct resource_pool *dce110_create_resource_pool(
1531 : uint8_t num_virtual_links,
1532 : struct dc *dc,
1533 : struct hw_asic_id asic_id)
1534 : {
1535 0 : struct dce110_resource_pool *pool =
1536 : kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1537 :
1538 0 : if (!pool)
1539 : return NULL;
1540 :
1541 0 : if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
1542 0 : return &pool->base;
1543 :
1544 0 : kfree(pool);
1545 0 : BREAK_TO_DEBUGGER();
1546 0 : return NULL;
1547 : }
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