Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 :
28 : #include "core_types.h"
29 :
30 : #include "reg_helper.h"
31 : #include "dcn20_dpp.h"
32 : #include "basics/conversion.h"
33 :
34 : #define NUM_PHASES 64
35 : #define HORZ_MAX_TAPS 8
36 : #define VERT_MAX_TAPS 8
37 :
38 : #define BLACK_OFFSET_RGB_Y 0x0
39 : #define BLACK_OFFSET_CBCR 0x8000
40 :
41 : #define REG(reg)\
42 : dpp->tf_regs->reg
43 :
44 : #define CTX \
45 : dpp->base.ctx
46 :
47 : #undef FN
48 : #define FN(reg_name, field_name) \
49 : dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 :
51 0 : void dpp20_read_state(struct dpp *dpp_base,
52 : struct dcn_dpp_state *s)
53 : {
54 0 : struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
55 :
56 0 : REG_GET(DPP_CONTROL,
57 : DPP_CLOCK_ENABLE, &s->is_enabled);
58 0 : REG_GET(CM_DGAM_CONTROL,
59 : CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
60 : // BGAM has no ROM, and definition is different, can't reuse same dump
61 : //REG_GET(CM_BLNDGAM_CONTROL,
62 : // CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
63 0 : REG_GET(CM_GAMUT_REMAP_CONTROL,
64 : CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
65 0 : if (s->gamut_remap_mode) {
66 0 : s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
67 0 : s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
68 0 : s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
69 0 : s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
70 0 : s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
71 0 : s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
72 : }
73 0 : }
74 :
75 0 : void dpp2_power_on_obuf(
76 : struct dpp *dpp_base,
77 : bool power_on)
78 : {
79 0 : struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
80 :
81 0 : REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
82 :
83 0 : REG_UPDATE(OBUF_MEM_PWR_CTRL,
84 : OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
85 :
86 0 : REG_UPDATE(DSCL_MEM_PWR_CTRL,
87 : LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
88 0 : }
89 :
90 0 : void dpp2_dummy_program_input_lut(
91 : struct dpp *dpp_base,
92 : const struct dc_gamma *gamma)
93 0 : {}
94 :
95 0 : static void dpp2_cnv_setup (
96 : struct dpp *dpp_base,
97 : enum surface_pixel_format format,
98 : enum expansion_mode mode,
99 : struct dc_csc_transform input_csc_color_matrix,
100 : enum dc_color_space input_color_space,
101 : struct cnv_alpha_2bit_lut *alpha_2bit_lut)
102 : {
103 0 : struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
104 0 : uint32_t pixel_format = 0;
105 0 : uint32_t alpha_en = 1;
106 0 : enum dc_color_space color_space = COLOR_SPACE_SRGB;
107 0 : enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS;
108 0 : bool force_disable_cursor = false;
109 : struct out_csc_color_matrix tbl_entry;
110 0 : uint32_t is_2bit = 0;
111 0 : int i = 0;
112 :
113 0 : REG_SET_2(FORMAT_CONTROL, 0,
114 : CNVC_BYPASS, 0,
115 : FORMAT_EXPANSION_MODE, mode);
116 :
117 : //hardcode default
118 : //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14
119 : //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled
120 : //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled
121 : //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled
122 0 : REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
123 0 : REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
124 0 : REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
125 0 : REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
126 :
127 : switch (format) {
128 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
129 : pixel_format = 1;
130 : break;
131 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
132 : pixel_format = 3;
133 : alpha_en = 0;
134 : break;
135 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
136 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
137 : pixel_format = 8;
138 : break;
139 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
140 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
141 : pixel_format = 10;
142 : is_2bit = 1;
143 : break;
144 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
145 : force_disable_cursor = false;
146 : pixel_format = 65;
147 : color_space = COLOR_SPACE_YCBCR709;
148 : select = DCN2_ICSC_SELECT_ICSC_A;
149 : break;
150 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
151 : force_disable_cursor = true;
152 : pixel_format = 64;
153 : color_space = COLOR_SPACE_YCBCR709;
154 : select = DCN2_ICSC_SELECT_ICSC_A;
155 : break;
156 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
157 : force_disable_cursor = true;
158 : pixel_format = 67;
159 : color_space = COLOR_SPACE_YCBCR709;
160 : select = DCN2_ICSC_SELECT_ICSC_A;
161 : break;
162 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
163 : force_disable_cursor = true;
164 : pixel_format = 66;
165 : color_space = COLOR_SPACE_YCBCR709;
166 : select = DCN2_ICSC_SELECT_ICSC_A;
167 : break;
168 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
169 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
170 : pixel_format = 26; /* ARGB16161616_UNORM */
171 : break;
172 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
173 : pixel_format = 24;
174 : break;
175 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
176 : pixel_format = 25;
177 : break;
178 : case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
179 : pixel_format = 12;
180 : color_space = COLOR_SPACE_YCBCR709;
181 : select = DCN2_ICSC_SELECT_ICSC_A;
182 : break;
183 : case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
184 : pixel_format = 112;
185 : alpha_en = 0;
186 : break;
187 : case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
188 : pixel_format = 113;
189 : alpha_en = 0;
190 : break;
191 : case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
192 : pixel_format = 114;
193 : color_space = COLOR_SPACE_YCBCR709;
194 : select = DCN2_ICSC_SELECT_ICSC_A;
195 : is_2bit = 1;
196 : break;
197 : case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
198 : pixel_format = 115;
199 : color_space = COLOR_SPACE_YCBCR709;
200 : select = DCN2_ICSC_SELECT_ICSC_A;
201 : is_2bit = 1;
202 : break;
203 : case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
204 : pixel_format = 118;
205 : alpha_en = 0;
206 : break;
207 : case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
208 : pixel_format = 119;
209 : alpha_en = 0;
210 : break;
211 : default:
212 : break;
213 : }
214 :
215 : /* Set default color space based on format if none is given. */
216 0 : color_space = input_color_space ? input_color_space : color_space;
217 :
218 0 : if (is_2bit == 1 && alpha_2bit_lut != NULL) {
219 0 : REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
220 0 : REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
221 0 : REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
222 0 : REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
223 : }
224 :
225 0 : REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
226 : CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
227 0 : REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
228 :
229 : // if input adjustments exist, program icsc with those values
230 0 : if (input_csc_color_matrix.enable_adjustment
231 : == true) {
232 0 : for (i = 0; i < 12; i++)
233 0 : tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
234 :
235 0 : tbl_entry.color_space = input_color_space;
236 :
237 0 : if (color_space >= COLOR_SPACE_YCBCR601)
238 : select = DCN2_ICSC_SELECT_ICSC_A;
239 : else
240 0 : select = DCN2_ICSC_SELECT_BYPASS;
241 :
242 0 : dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry);
243 : } else
244 0 : dpp2_program_input_csc(dpp_base, color_space, select, NULL);
245 :
246 0 : if (force_disable_cursor) {
247 0 : REG_UPDATE(CURSOR_CONTROL,
248 : CURSOR_ENABLE, 0);
249 0 : REG_UPDATE(CURSOR0_CONTROL,
250 : CUR0_ENABLE, 0);
251 :
252 : }
253 0 : dpp2_power_on_obuf(dpp_base, true);
254 :
255 0 : }
256 :
257 : /*compute the maximum number of lines that we can fit in the line buffer*/
258 0 : void dscl2_calc_lb_num_partitions(
259 : const struct scaler_data *scl_data,
260 : enum lb_memory_config lb_config,
261 : int *num_part_y,
262 : int *num_part_c)
263 : {
264 : int memory_line_size_y, memory_line_size_c, memory_line_size_a,
265 : lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
266 :
267 0 : int line_size = scl_data->viewport.width < scl_data->recout.width ?
268 0 : scl_data->viewport.width : scl_data->recout.width;
269 0 : int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
270 0 : scl_data->viewport_c.width : scl_data->recout.width;
271 :
272 0 : if (line_size == 0)
273 0 : line_size = 1;
274 :
275 0 : if (line_size_c == 0)
276 0 : line_size_c = 1;
277 :
278 0 : memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
279 0 : memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
280 0 : memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
281 :
282 0 : if (lb_config == LB_MEMORY_CONFIG_1) {
283 : lb_memory_size = 970;
284 : lb_memory_size_c = 970;
285 : lb_memory_size_a = 970;
286 0 : } else if (lb_config == LB_MEMORY_CONFIG_2) {
287 : lb_memory_size = 1290;
288 : lb_memory_size_c = 1290;
289 : lb_memory_size_a = 1290;
290 0 : } else if (lb_config == LB_MEMORY_CONFIG_3) {
291 : /* 420 mode: using 3rd mem from Y, Cr and Cb */
292 : lb_memory_size = 970 + 1290 + 484 + 484 + 484;
293 : lb_memory_size_c = 970 + 1290;
294 : lb_memory_size_a = 970 + 1290 + 484;
295 : } else {
296 0 : lb_memory_size = 970 + 1290 + 484;
297 0 : lb_memory_size_c = 970 + 1290 + 484;
298 0 : lb_memory_size_a = 970 + 1290 + 484;
299 : }
300 0 : *num_part_y = lb_memory_size / memory_line_size_y;
301 0 : *num_part_c = lb_memory_size_c / memory_line_size_c;
302 0 : num_partitions_a = lb_memory_size_a / memory_line_size_a;
303 :
304 0 : if (scl_data->lb_params.alpha_en
305 0 : && (num_partitions_a < *num_part_y))
306 0 : *num_part_y = num_partitions_a;
307 :
308 0 : if (*num_part_y > 64)
309 0 : *num_part_y = 64;
310 0 : if (*num_part_c > 64)
311 0 : *num_part_c = 64;
312 0 : }
313 :
314 0 : void dpp2_cnv_set_alpha_keyer(
315 : struct dpp *dpp_base,
316 : struct cnv_color_keyer_params *color_keyer)
317 : {
318 0 : struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
319 :
320 0 : REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
321 :
322 0 : REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
323 :
324 0 : REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
325 0 : REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
326 :
327 0 : REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
328 0 : REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
329 :
330 0 : REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
331 0 : REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
332 :
333 0 : REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
334 0 : REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
335 0 : }
336 :
337 0 : void dpp2_set_cursor_attributes(
338 : struct dpp *dpp_base,
339 : struct dc_cursor_attributes *cursor_attributes)
340 : {
341 0 : enum dc_cursor_color_format color_format = cursor_attributes->color_format;
342 0 : struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
343 0 : int cur_rom_en = 0;
344 :
345 0 : if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
346 : color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
347 0 : if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
348 0 : cur_rom_en = 1;
349 : }
350 : }
351 :
352 0 : REG_UPDATE_3(CURSOR0_CONTROL,
353 : CUR0_MODE, color_format,
354 : CUR0_EXPANSION_MODE, 0,
355 : CUR0_ROM_EN, cur_rom_en);
356 :
357 0 : if (color_format == CURSOR_MODE_MONO) {
358 : /* todo: clarify what to program these to */
359 0 : REG_UPDATE(CURSOR0_COLOR0,
360 : CUR0_COLOR0, 0x00000000);
361 0 : REG_UPDATE(CURSOR0_COLOR1,
362 : CUR0_COLOR1, 0xFFFFFFFF);
363 : }
364 0 : }
365 :
366 0 : void oppn20_dummy_program_regamma_pwl(
367 : struct dpp *dpp,
368 : const struct pwl_params *params,
369 : enum opp_regamma mode)
370 0 : {}
371 :
372 : static struct dpp_funcs dcn20_dpp_funcs = {
373 : .dpp_read_state = dpp20_read_state,
374 : .dpp_reset = dpp_reset,
375 : .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
376 : .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
377 : .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap,
378 : .dpp_set_csc_adjustment = NULL,
379 : .dpp_set_csc_default = NULL,
380 : .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
381 : .dpp_set_degamma = dpp2_set_degamma,
382 : .dpp_program_input_lut = dpp2_dummy_program_input_lut,
383 : .dpp_full_bypass = dpp1_full_bypass,
384 : .dpp_setup = dpp2_cnv_setup,
385 : .dpp_program_degamma_pwl = dpp2_set_degamma_pwl,
386 : .dpp_program_blnd_lut = dpp20_program_blnd_lut,
387 : .dpp_program_shaper_lut = dpp20_program_shaper,
388 : .dpp_program_3dlut = dpp20_program_3dlut,
389 : .dpp_program_bias_and_scale = NULL,
390 : .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
391 : .set_cursor_attributes = dpp2_set_cursor_attributes,
392 : .set_cursor_position = dpp1_set_cursor_position,
393 : .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
394 : .dpp_dppclk_control = dpp1_dppclk_control,
395 : .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
396 : };
397 :
398 : static struct dpp_caps dcn20_dpp_cap = {
399 : .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
400 : .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
401 : };
402 :
403 0 : bool dpp2_construct(
404 : struct dcn20_dpp *dpp,
405 : struct dc_context *ctx,
406 : uint32_t inst,
407 : const struct dcn2_dpp_registers *tf_regs,
408 : const struct dcn2_dpp_shift *tf_shift,
409 : const struct dcn2_dpp_mask *tf_mask)
410 : {
411 0 : dpp->base.ctx = ctx;
412 :
413 0 : dpp->base.inst = inst;
414 0 : dpp->base.funcs = &dcn20_dpp_funcs;
415 0 : dpp->base.caps = &dcn20_dpp_cap;
416 :
417 0 : dpp->tf_regs = tf_regs;
418 0 : dpp->tf_shift = tf_shift;
419 0 : dpp->tf_mask = tf_mask;
420 :
421 0 : dpp->lb_pixel_depth_supported =
422 : LB_PIXEL_DEPTH_18BPP |
423 : LB_PIXEL_DEPTH_24BPP |
424 : LB_PIXEL_DEPTH_30BPP |
425 : LB_PIXEL_DEPTH_36BPP;
426 :
427 0 : dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
428 0 : dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
429 :
430 0 : return true;
431 : }
432 :
|
