Line data Source code
1 : /*
2 : * Copyright 2012-2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dcn20_hubp.h"
27 :
28 : #include "dm_services.h"
29 : #include "dce_calcs.h"
30 : #include "reg_helper.h"
31 : #include "basics/conversion.h"
32 :
33 : #define DC_LOGGER_INIT(logger)
34 :
35 : #define REG(reg)\
36 : hubp2->hubp_regs->reg
37 :
38 : #define CTX \
39 : hubp2->base.ctx
40 :
41 : #undef FN
42 : #define FN(reg_name, field_name) \
43 : hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
44 :
45 0 : void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
46 : struct vm_system_aperture_param *apt)
47 : {
48 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
49 :
50 : PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
51 : PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
52 : PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
53 :
54 : // The format of default addr is 48:12 of the 48 bit addr
55 0 : mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
56 :
57 : // The format of high/low are 48:18 of the 48 bit addr
58 0 : mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
59 0 : mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
60 :
61 0 : REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
62 : DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
63 : DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
64 :
65 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
66 : DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
67 :
68 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
69 : MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
70 :
71 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
72 : MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
73 :
74 0 : REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
75 : ENABLE_L1_TLB, 1,
76 : SYSTEM_ACCESS_MODE, 0x3);
77 0 : }
78 :
79 0 : void hubp2_program_deadline(
80 : struct hubp *hubp,
81 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
82 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
83 : {
84 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
85 :
86 : /* DLG - Per hubp */
87 0 : REG_SET_2(BLANK_OFFSET_0, 0,
88 : REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
89 : DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
90 :
91 0 : REG_SET(BLANK_OFFSET_1, 0,
92 : MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
93 :
94 0 : REG_SET(DST_DIMENSIONS, 0,
95 : REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
96 :
97 0 : REG_SET_2(DST_AFTER_SCALER, 0,
98 : REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
99 : DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
100 :
101 0 : REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
102 : REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
103 :
104 : /* DLG - Per luma/chroma */
105 0 : REG_SET(VBLANK_PARAMETERS_1, 0,
106 : REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
107 :
108 0 : if (REG(NOM_PARAMETERS_0))
109 0 : REG_SET(NOM_PARAMETERS_0, 0,
110 : DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
111 :
112 0 : if (REG(NOM_PARAMETERS_1))
113 0 : REG_SET(NOM_PARAMETERS_1, 0,
114 : REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
115 :
116 0 : REG_SET(NOM_PARAMETERS_4, 0,
117 : DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
118 :
119 0 : REG_SET(NOM_PARAMETERS_5, 0,
120 : REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
121 :
122 0 : REG_SET_2(PER_LINE_DELIVERY, 0,
123 : REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
124 : REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
125 :
126 0 : REG_SET(VBLANK_PARAMETERS_2, 0,
127 : REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
128 :
129 0 : if (REG(NOM_PARAMETERS_2))
130 0 : REG_SET(NOM_PARAMETERS_2, 0,
131 : DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
132 :
133 0 : if (REG(NOM_PARAMETERS_3))
134 0 : REG_SET(NOM_PARAMETERS_3, 0,
135 : REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
136 :
137 0 : REG_SET(NOM_PARAMETERS_6, 0,
138 : DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
139 :
140 0 : REG_SET(NOM_PARAMETERS_7, 0,
141 : REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
142 :
143 : /* TTU - per hubp */
144 0 : REG_SET_2(DCN_TTU_QOS_WM, 0,
145 : QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
146 : QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
147 :
148 : /* TTU - per luma/chroma */
149 : /* Assumed surf0 is luma and 1 is chroma */
150 :
151 0 : REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
152 : REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
153 : QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
154 : QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
155 :
156 0 : REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
157 : REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
158 : QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
159 : QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
160 :
161 0 : REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
162 : REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
163 : QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
164 : QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
165 :
166 0 : REG_SET(FLIP_PARAMETERS_1, 0,
167 : REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
168 0 : }
169 :
170 0 : void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
171 : struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
172 : {
173 0 : uint32_t value = 0;
174 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
175 : /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
176 0 : REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
177 : /*
178 : if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
179 : <= OTG_V_BLANK_END
180 : Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
181 : else
182 : Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
183 : */
184 0 : if (pipe_dest->htotal != 0) {
185 0 : if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
186 0 : + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
187 : value = 1;
188 : } else
189 0 : value = 0;
190 : }
191 :
192 0 : REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
193 0 : }
194 :
195 0 : static void hubp2_program_requestor(struct hubp *hubp,
196 : struct _vcs_dpi_display_rq_regs_st *rq_regs)
197 : {
198 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
199 :
200 0 : REG_UPDATE(HUBPRET_CONTROL,
201 : DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
202 0 : REG_SET_4(DCN_EXPANSION_MODE, 0,
203 : DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
204 : PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
205 : MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
206 : CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
207 0 : REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
208 : CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
209 : MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
210 : META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
211 : MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
212 : DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
213 : MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
214 : SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
215 : PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
216 0 : REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
217 : CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
218 : MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
219 : META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
220 : MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
221 : DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
222 : MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
223 : SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
224 : PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
225 0 : }
226 :
227 0 : static void hubp2_setup(
228 : struct hubp *hubp,
229 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
230 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
231 : struct _vcs_dpi_display_rq_regs_st *rq_regs,
232 : struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
233 : {
234 : /* otg is locked when this func is called. Register are double buffered.
235 : * disable the requestors is not needed
236 : */
237 :
238 0 : hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
239 0 : hubp2_program_requestor(hubp, rq_regs);
240 0 : hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
241 :
242 0 : }
243 :
244 0 : void hubp2_setup_interdependent(
245 : struct hubp *hubp,
246 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
247 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
248 : {
249 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
250 :
251 0 : REG_SET_2(PREFETCH_SETTINGS, 0,
252 : DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
253 : VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
254 :
255 0 : REG_SET(PREFETCH_SETTINGS_C, 0,
256 : VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
257 :
258 0 : REG_SET_2(VBLANK_PARAMETERS_0, 0,
259 : DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
260 : DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
261 :
262 0 : REG_SET_2(FLIP_PARAMETERS_0, 0,
263 : DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
264 : DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
265 :
266 0 : REG_SET(VBLANK_PARAMETERS_3, 0,
267 : REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
268 :
269 0 : REG_SET(VBLANK_PARAMETERS_4, 0,
270 : REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
271 :
272 0 : REG_SET(FLIP_PARAMETERS_2, 0,
273 : REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
274 :
275 0 : REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
276 : REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
277 : REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
278 :
279 0 : REG_SET(DCN_SURF0_TTU_CNTL1, 0,
280 : REFCYC_PER_REQ_DELIVERY_PRE,
281 : ttu_attr->refcyc_per_req_delivery_pre_l);
282 0 : REG_SET(DCN_SURF1_TTU_CNTL1, 0,
283 : REFCYC_PER_REQ_DELIVERY_PRE,
284 : ttu_attr->refcyc_per_req_delivery_pre_c);
285 0 : REG_SET(DCN_CUR0_TTU_CNTL1, 0,
286 : REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
287 0 : REG_SET(DCN_CUR1_TTU_CNTL1, 0,
288 : REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
289 :
290 0 : REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
291 : MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
292 : QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
293 0 : }
294 :
295 : /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
296 : * NUM_BANKS
297 : * NUM_SE
298 : * NUM_RB_PER_SE
299 : * RB_ALIGNED
300 : * Other things can be defaulted, since they never change:
301 : * PIPE_ALIGNED = 0
302 : * META_LINEAR = 0
303 : * In GFX10, only these apply:
304 : * PIPE_INTERLEAVE
305 : * NUM_PIPES
306 : * MAX_COMPRESSED_FRAGS
307 : * SW_MODE
308 : */
309 0 : static void hubp2_program_tiling(
310 : struct dcn20_hubp *hubp2,
311 : const union dc_tiling_info *info,
312 : const enum surface_pixel_format pixel_format)
313 : {
314 0 : REG_UPDATE_3(DCSURF_ADDR_CONFIG,
315 : NUM_PIPES, log_2(info->gfx9.num_pipes),
316 : PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
317 : MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
318 :
319 0 : REG_UPDATE_4(DCSURF_TILING_CONFIG,
320 : SW_MODE, info->gfx9.swizzle,
321 : META_LINEAR, 0,
322 : RB_ALIGNED, 0,
323 : PIPE_ALIGNED, 0);
324 0 : }
325 :
326 0 : void hubp2_program_size(
327 : struct hubp *hubp,
328 : enum surface_pixel_format format,
329 : const struct plane_size *plane_size,
330 : struct dc_plane_dcc_param *dcc)
331 : {
332 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
333 : uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
334 0 : bool use_pitch_c = false;
335 :
336 : /* Program data and meta surface pitch (calculation from addrlib)
337 : * 444 or 420 luma
338 : */
339 0 : use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
340 0 : && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
341 0 : use_pitch_c = use_pitch_c
342 0 : || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
343 0 : if (use_pitch_c) {
344 0 : ASSERT(plane_size->chroma_pitch != 0);
345 : /* Chroma pitch zero can cause system hang! */
346 :
347 0 : pitch = plane_size->surface_pitch - 1;
348 0 : meta_pitch = dcc->meta_pitch - 1;
349 0 : pitch_c = plane_size->chroma_pitch - 1;
350 0 : meta_pitch_c = dcc->meta_pitch_c - 1;
351 : } else {
352 0 : pitch = plane_size->surface_pitch - 1;
353 0 : meta_pitch = dcc->meta_pitch - 1;
354 0 : pitch_c = 0;
355 0 : meta_pitch_c = 0;
356 : }
357 :
358 0 : if (!dcc->enable) {
359 0 : meta_pitch = 0;
360 0 : meta_pitch_c = 0;
361 : }
362 :
363 0 : REG_UPDATE_2(DCSURF_SURFACE_PITCH,
364 : PITCH, pitch, META_PITCH, meta_pitch);
365 :
366 0 : use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
367 0 : use_pitch_c = use_pitch_c
368 0 : || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
369 0 : if (use_pitch_c)
370 0 : REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
371 : PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
372 0 : }
373 :
374 0 : void hubp2_program_rotation(
375 : struct hubp *hubp,
376 : enum dc_rotation_angle rotation,
377 : bool horizontal_mirror)
378 : {
379 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
380 : uint32_t mirror;
381 :
382 :
383 0 : if (horizontal_mirror)
384 : mirror = 1;
385 : else
386 0 : mirror = 0;
387 :
388 : /* Program rotation angle and horz mirror - no mirror */
389 0 : if (rotation == ROTATION_ANGLE_0)
390 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
391 : ROTATION_ANGLE, 0,
392 : H_MIRROR_EN, mirror);
393 0 : else if (rotation == ROTATION_ANGLE_90)
394 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
395 : ROTATION_ANGLE, 1,
396 : H_MIRROR_EN, mirror);
397 0 : else if (rotation == ROTATION_ANGLE_180)
398 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
399 : ROTATION_ANGLE, 2,
400 : H_MIRROR_EN, mirror);
401 0 : else if (rotation == ROTATION_ANGLE_270)
402 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
403 : ROTATION_ANGLE, 3,
404 : H_MIRROR_EN, mirror);
405 0 : }
406 :
407 0 : void hubp2_dcc_control(struct hubp *hubp, bool enable,
408 : enum hubp_ind_block_size independent_64b_blks)
409 : {
410 0 : uint32_t dcc_en = enable ? 1 : 0;
411 0 : uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
412 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
413 :
414 0 : REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
415 : PRIMARY_SURFACE_DCC_EN, dcc_en,
416 : PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
417 : SECONDARY_SURFACE_DCC_EN, dcc_en,
418 : SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
419 0 : }
420 :
421 0 : void hubp2_program_pixel_format(
422 : struct hubp *hubp,
423 : enum surface_pixel_format format)
424 : {
425 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
426 0 : uint32_t red_bar = 3;
427 0 : uint32_t blue_bar = 2;
428 :
429 : /* swap for ABGR format */
430 0 : if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
431 0 : || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
432 0 : || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
433 0 : || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
434 0 : || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
435 0 : red_bar = 2;
436 0 : blue_bar = 3;
437 : }
438 :
439 0 : REG_UPDATE_2(HUBPRET_CONTROL,
440 : CROSSBAR_SRC_CB_B, blue_bar,
441 : CROSSBAR_SRC_CR_R, red_bar);
442 :
443 : /* Mapping is same as ipp programming (cnvc) */
444 :
445 0 : switch (format) {
446 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
447 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
448 : SURFACE_PIXEL_FORMAT, 1);
449 0 : break;
450 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
451 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
452 : SURFACE_PIXEL_FORMAT, 3);
453 0 : break;
454 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
455 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
456 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
457 : SURFACE_PIXEL_FORMAT, 8);
458 0 : break;
459 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
460 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
461 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
462 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
463 : SURFACE_PIXEL_FORMAT, 10);
464 0 : break;
465 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
466 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
467 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
468 : SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
469 0 : break;
470 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
471 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
472 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
473 : SURFACE_PIXEL_FORMAT, 24);
474 0 : break;
475 :
476 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
477 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
478 : SURFACE_PIXEL_FORMAT, 65);
479 0 : break;
480 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
481 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
482 : SURFACE_PIXEL_FORMAT, 64);
483 0 : break;
484 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
485 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
486 : SURFACE_PIXEL_FORMAT, 67);
487 0 : break;
488 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
489 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
490 : SURFACE_PIXEL_FORMAT, 66);
491 0 : break;
492 : case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
493 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
494 : SURFACE_PIXEL_FORMAT, 12);
495 0 : break;
496 : case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
497 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
498 : SURFACE_PIXEL_FORMAT, 112);
499 0 : break;
500 : case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
501 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
502 : SURFACE_PIXEL_FORMAT, 113);
503 0 : break;
504 : case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
505 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
506 : SURFACE_PIXEL_FORMAT, 114);
507 0 : break;
508 : case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
509 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
510 : SURFACE_PIXEL_FORMAT, 118);
511 0 : break;
512 : case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
513 0 : REG_UPDATE(DCSURF_SURFACE_CONFIG,
514 : SURFACE_PIXEL_FORMAT, 119);
515 0 : break;
516 : case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
517 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
518 : SURFACE_PIXEL_FORMAT, 116,
519 : ALPHA_PLANE_EN, 0);
520 0 : break;
521 : case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
522 0 : REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
523 : SURFACE_PIXEL_FORMAT, 116,
524 : ALPHA_PLANE_EN, 1);
525 0 : break;
526 : default:
527 0 : BREAK_TO_DEBUGGER();
528 0 : break;
529 : }
530 :
531 : /* don't see the need of program the xbar in DCN 1.0 */
532 0 : }
533 :
534 0 : void hubp2_program_surface_config(
535 : struct hubp *hubp,
536 : enum surface_pixel_format format,
537 : union dc_tiling_info *tiling_info,
538 : struct plane_size *plane_size,
539 : enum dc_rotation_angle rotation,
540 : struct dc_plane_dcc_param *dcc,
541 : bool horizontal_mirror,
542 : unsigned int compat_level)
543 : {
544 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
545 :
546 0 : hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
547 0 : hubp2_program_tiling(hubp2, tiling_info, format);
548 0 : hubp2_program_size(hubp, format, plane_size, dcc);
549 0 : hubp2_program_rotation(hubp, rotation, horizontal_mirror);
550 0 : hubp2_program_pixel_format(hubp, format);
551 0 : }
552 :
553 0 : enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
554 : unsigned int cursor_width,
555 : enum dc_cursor_color_format cursor_mode)
556 : {
557 0 : enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
558 :
559 0 : if (cursor_mode == CURSOR_MODE_MONO)
560 : line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
561 0 : else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
562 0 : cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
563 : cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
564 0 : if (cursor_width >= 1 && cursor_width <= 32)
565 : line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
566 0 : else if (cursor_width >= 33 && cursor_width <= 64)
567 : line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
568 0 : else if (cursor_width >= 65 && cursor_width <= 128)
569 : line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
570 0 : else if (cursor_width >= 129 && cursor_width <= 256)
571 0 : line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
572 0 : } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
573 : cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
574 0 : if (cursor_width >= 1 && cursor_width <= 16)
575 : line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
576 0 : else if (cursor_width >= 17 && cursor_width <= 32)
577 : line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
578 0 : else if (cursor_width >= 33 && cursor_width <= 64)
579 : line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
580 0 : else if (cursor_width >= 65 && cursor_width <= 128)
581 : line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
582 0 : else if (cursor_width >= 129 && cursor_width <= 256)
583 0 : line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
584 : }
585 :
586 0 : return line_per_chunk;
587 : }
588 :
589 0 : void hubp2_cursor_set_attributes(
590 : struct hubp *hubp,
591 : const struct dc_cursor_attributes *attr)
592 : {
593 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
594 0 : enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
595 0 : enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
596 : attr->width, attr->color_format);
597 :
598 0 : hubp->curs_attr = *attr;
599 :
600 0 : REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
601 : CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
602 0 : REG_UPDATE(CURSOR_SURFACE_ADDRESS,
603 : CURSOR_SURFACE_ADDRESS, attr->address.low_part);
604 :
605 0 : REG_UPDATE_2(CURSOR_SIZE,
606 : CURSOR_WIDTH, attr->width,
607 : CURSOR_HEIGHT, attr->height);
608 :
609 0 : REG_UPDATE_4(CURSOR_CONTROL,
610 : CURSOR_MODE, attr->color_format,
611 : CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
612 : CURSOR_PITCH, hw_pitch,
613 : CURSOR_LINES_PER_CHUNK, lpc);
614 :
615 0 : REG_SET_2(CURSOR_SETTINGS, 0,
616 : /* no shift of the cursor HDL schedule */
617 : CURSOR0_DST_Y_OFFSET, 0,
618 : /* used to shift the cursor chunk request deadline */
619 : CURSOR0_CHUNK_HDL_ADJUST, 3);
620 0 : }
621 :
622 0 : void hubp2_dmdata_set_attributes(
623 : struct hubp *hubp,
624 : const struct dc_dmdata_attributes *attr)
625 : {
626 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
627 :
628 0 : if (attr->dmdata_mode == DMDATA_HW_MODE) {
629 : /* set to HW mode */
630 0 : REG_UPDATE(DMDATA_CNTL,
631 : DMDATA_MODE, 1);
632 :
633 : /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
634 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
635 :
636 : /* toggle DMDATA_UPDATED and set repeat and size */
637 0 : REG_UPDATE(DMDATA_CNTL,
638 : DMDATA_UPDATED, 0);
639 0 : REG_UPDATE_3(DMDATA_CNTL,
640 : DMDATA_UPDATED, 1,
641 : DMDATA_REPEAT, attr->dmdata_repeat,
642 : DMDATA_SIZE, attr->dmdata_size);
643 :
644 : /* set DMDATA address */
645 0 : REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
646 0 : REG_UPDATE(DMDATA_ADDRESS_HIGH,
647 : DMDATA_ADDRESS_HIGH, attr->address.high_part);
648 :
649 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
650 :
651 : } else {
652 : /* set to SW mode before loading data */
653 0 : REG_SET(DMDATA_CNTL, 0,
654 : DMDATA_MODE, 0);
655 : /* toggle DMDATA_SW_UPDATED to start loading sequence */
656 0 : REG_UPDATE(DMDATA_SW_CNTL,
657 : DMDATA_SW_UPDATED, 0);
658 0 : REG_UPDATE_3(DMDATA_SW_CNTL,
659 : DMDATA_SW_UPDATED, 1,
660 : DMDATA_SW_REPEAT, attr->dmdata_repeat,
661 : DMDATA_SW_SIZE, attr->dmdata_size);
662 : /* load data into hubp dmdata buffer */
663 0 : hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
664 : }
665 :
666 : /* Note that DL_DELTA must be programmed if we want to use TTU mode */
667 0 : REG_SET_3(DMDATA_QOS_CNTL, 0,
668 : DMDATA_QOS_MODE, attr->dmdata_qos_mode,
669 : DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
670 : DMDATA_DL_DELTA, attr->dmdata_dl_delta);
671 0 : }
672 :
673 0 : void hubp2_dmdata_load(
674 : struct hubp *hubp,
675 : uint32_t dmdata_sw_size,
676 : const uint32_t *dmdata_sw_data)
677 : {
678 : int i;
679 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
680 :
681 : /* load dmdata into HUBP buffer in SW mode */
682 0 : for (i = 0; i < dmdata_sw_size / 4; i++)
683 0 : REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
684 0 : }
685 :
686 0 : bool hubp2_dmdata_status_done(struct hubp *hubp)
687 : {
688 : uint32_t status;
689 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
690 :
691 0 : REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
692 0 : return (status == 1);
693 : }
694 :
695 0 : bool hubp2_program_surface_flip_and_addr(
696 : struct hubp *hubp,
697 : const struct dc_plane_address *address,
698 : bool flip_immediate)
699 : {
700 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
701 :
702 : //program flip type
703 0 : REG_UPDATE(DCSURF_FLIP_CONTROL,
704 : SURFACE_FLIP_TYPE, flip_immediate);
705 :
706 : // Program VMID reg
707 0 : REG_UPDATE(VMID_SETTINGS_0,
708 : VMID, address->vmid);
709 :
710 :
711 : /* HW automatically latch rest of address register on write to
712 : * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
713 : *
714 : * program high first and then the low addr, order matters!
715 : */
716 0 : switch (address->type) {
717 : case PLN_ADDR_TYPE_GRAPHICS:
718 : /* DCN1.0 does not support const color
719 : * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
720 : * base on address->grph.dcc_const_color
721 : * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
722 : * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
723 : */
724 :
725 0 : if (address->grph.addr.quad_part == 0)
726 : break;
727 :
728 0 : REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
729 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
730 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
731 :
732 0 : if (address->grph.meta_addr.quad_part != 0) {
733 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
734 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
735 : address->grph.meta_addr.high_part);
736 :
737 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
738 : PRIMARY_META_SURFACE_ADDRESS,
739 : address->grph.meta_addr.low_part);
740 : }
741 :
742 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
743 : PRIMARY_SURFACE_ADDRESS_HIGH,
744 : address->grph.addr.high_part);
745 :
746 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
747 : PRIMARY_SURFACE_ADDRESS,
748 : address->grph.addr.low_part);
749 0 : break;
750 : case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
751 0 : if (address->video_progressive.luma_addr.quad_part == 0
752 0 : || address->video_progressive.chroma_addr.quad_part == 0)
753 : break;
754 :
755 0 : REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
756 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
757 : PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
758 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
759 : PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
760 :
761 0 : if (address->video_progressive.luma_meta_addr.quad_part != 0) {
762 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
763 : PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
764 : address->video_progressive.chroma_meta_addr.high_part);
765 :
766 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
767 : PRIMARY_META_SURFACE_ADDRESS_C,
768 : address->video_progressive.chroma_meta_addr.low_part);
769 :
770 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
771 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
772 : address->video_progressive.luma_meta_addr.high_part);
773 :
774 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
775 : PRIMARY_META_SURFACE_ADDRESS,
776 : address->video_progressive.luma_meta_addr.low_part);
777 : }
778 :
779 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
780 : PRIMARY_SURFACE_ADDRESS_HIGH_C,
781 : address->video_progressive.chroma_addr.high_part);
782 :
783 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
784 : PRIMARY_SURFACE_ADDRESS_C,
785 : address->video_progressive.chroma_addr.low_part);
786 :
787 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
788 : PRIMARY_SURFACE_ADDRESS_HIGH,
789 : address->video_progressive.luma_addr.high_part);
790 :
791 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
792 : PRIMARY_SURFACE_ADDRESS,
793 : address->video_progressive.luma_addr.low_part);
794 0 : break;
795 : case PLN_ADDR_TYPE_GRPH_STEREO:
796 0 : if (address->grph_stereo.left_addr.quad_part == 0)
797 : break;
798 0 : if (address->grph_stereo.right_addr.quad_part == 0)
799 : break;
800 :
801 0 : REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
802 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
803 : PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
804 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
805 : PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
806 : SECONDARY_SURFACE_TMZ, address->tmz_surface,
807 : SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
808 : SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
809 : SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
810 :
811 0 : if (address->grph_stereo.right_meta_addr.quad_part != 0) {
812 :
813 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
814 : SECONDARY_META_SURFACE_ADDRESS_HIGH,
815 : address->grph_stereo.right_meta_addr.high_part);
816 :
817 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
818 : SECONDARY_META_SURFACE_ADDRESS,
819 : address->grph_stereo.right_meta_addr.low_part);
820 : }
821 0 : if (address->grph_stereo.left_meta_addr.quad_part != 0) {
822 :
823 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
824 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
825 : address->grph_stereo.left_meta_addr.high_part);
826 :
827 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
828 : PRIMARY_META_SURFACE_ADDRESS,
829 : address->grph_stereo.left_meta_addr.low_part);
830 : }
831 :
832 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
833 : SECONDARY_SURFACE_ADDRESS_HIGH,
834 : address->grph_stereo.right_addr.high_part);
835 :
836 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
837 : SECONDARY_SURFACE_ADDRESS,
838 : address->grph_stereo.right_addr.low_part);
839 :
840 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
841 : PRIMARY_SURFACE_ADDRESS_HIGH,
842 : address->grph_stereo.left_addr.high_part);
843 :
844 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
845 : PRIMARY_SURFACE_ADDRESS,
846 : address->grph_stereo.left_addr.low_part);
847 0 : break;
848 : default:
849 0 : BREAK_TO_DEBUGGER();
850 0 : break;
851 : }
852 :
853 0 : hubp->request_address = *address;
854 :
855 0 : return true;
856 : }
857 :
858 0 : void hubp2_enable_triplebuffer(
859 : struct hubp *hubp,
860 : bool enable)
861 : {
862 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
863 0 : uint32_t triple_buffer_en = 0;
864 : bool tri_buffer_en;
865 :
866 0 : REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
867 0 : tri_buffer_en = (triple_buffer_en == 1);
868 0 : if (tri_buffer_en != enable) {
869 0 : REG_UPDATE(DCSURF_FLIP_CONTROL2,
870 : SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
871 : }
872 0 : }
873 :
874 0 : bool hubp2_is_triplebuffer_enabled(
875 : struct hubp *hubp)
876 : {
877 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
878 0 : uint32_t triple_buffer_en = 0;
879 :
880 0 : REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
881 :
882 0 : return (bool)triple_buffer_en;
883 : }
884 :
885 0 : void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
886 : {
887 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
888 :
889 0 : REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
890 0 : }
891 :
892 0 : bool hubp2_is_flip_pending(struct hubp *hubp)
893 : {
894 0 : uint32_t flip_pending = 0;
895 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
896 : struct dc_plane_address earliest_inuse_address;
897 :
898 0 : if (hubp && hubp->power_gated)
899 : return false;
900 :
901 0 : REG_GET(DCSURF_FLIP_CONTROL,
902 : SURFACE_FLIP_PENDING, &flip_pending);
903 :
904 0 : REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
905 : SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
906 :
907 0 : REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
908 : SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
909 :
910 0 : if (flip_pending)
911 : return true;
912 :
913 0 : if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
914 : return true;
915 :
916 0 : return false;
917 : }
918 :
919 0 : void hubp2_set_blank(struct hubp *hubp, bool blank)
920 : {
921 0 : hubp2_set_blank_regs(hubp, blank);
922 :
923 0 : if (blank) {
924 0 : hubp->mpcc_id = 0xf;
925 0 : hubp->opp_id = OPP_ID_INVALID;
926 : }
927 0 : }
928 :
929 0 : void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
930 : {
931 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
932 0 : uint32_t blank_en = blank ? 1 : 0;
933 :
934 0 : if (blank) {
935 0 : uint32_t reg_val = REG_READ(DCHUBP_CNTL);
936 :
937 0 : if (reg_val) {
938 : /* init sequence workaround: in case HUBP is
939 : * power gated, this wait would timeout.
940 : *
941 : * we just wrote reg_val to non-0, if it stay 0
942 : * it means HUBP is gated
943 : */
944 0 : REG_WAIT(DCHUBP_CNTL,
945 : HUBP_NO_OUTSTANDING_REQ, 1,
946 : 1, 100000);
947 : }
948 : }
949 :
950 0 : REG_UPDATE_2(DCHUBP_CNTL,
951 : HUBP_BLANK_EN, blank_en,
952 : HUBP_TTU_DISABLE, 0);
953 0 : }
954 :
955 0 : void hubp2_cursor_set_position(
956 : struct hubp *hubp,
957 : const struct dc_cursor_position *pos,
958 : const struct dc_cursor_mi_param *param)
959 : {
960 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
961 0 : int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
962 0 : int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
963 0 : int x_hotspot = pos->x_hotspot;
964 0 : int y_hotspot = pos->y_hotspot;
965 0 : int cursor_height = (int)hubp->curs_attr.height;
966 0 : int cursor_width = (int)hubp->curs_attr.width;
967 : uint32_t dst_x_offset;
968 0 : uint32_t cur_en = pos->enable ? 1 : 0;
969 :
970 0 : hubp->curs_pos = *pos;
971 :
972 : /*
973 : * Guard aganst cursor_set_position() from being called with invalid
974 : * attributes
975 : *
976 : * TODO: Look at combining cursor_set_position() and
977 : * cursor_set_attributes() into cursor_update()
978 : */
979 0 : if (hubp->curs_attr.address.quad_part == 0)
980 : return;
981 :
982 : // Rotated cursor width/height and hotspots tweaks for offset calculation
983 0 : if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
984 0 : swap(cursor_height, cursor_width);
985 0 : if (param->rotation == ROTATION_ANGLE_90) {
986 0 : src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
987 0 : src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
988 : }
989 0 : } else if (param->rotation == ROTATION_ANGLE_180) {
990 0 : if (!param->mirror)
991 0 : src_x_offset = pos->x - param->viewport.x;
992 :
993 0 : src_y_offset = pos->y - param->viewport.y;
994 : }
995 :
996 0 : dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
997 0 : dst_x_offset *= param->ref_clk_khz;
998 0 : dst_x_offset /= param->pixel_clk_khz;
999 :
1000 0 : ASSERT(param->h_scale_ratio.value);
1001 :
1002 0 : if (param->h_scale_ratio.value)
1003 0 : dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1004 : dc_fixpt_from_int(dst_x_offset),
1005 : param->h_scale_ratio));
1006 :
1007 0 : if (src_x_offset >= (int)param->viewport.width)
1008 0 : cur_en = 0; /* not visible beyond right edge*/
1009 :
1010 0 : if (src_x_offset + cursor_width <= 0)
1011 0 : cur_en = 0; /* not visible beyond left edge*/
1012 :
1013 0 : if (src_y_offset >= (int)param->viewport.height)
1014 0 : cur_en = 0; /* not visible beyond bottom edge*/
1015 :
1016 0 : if (src_y_offset + cursor_height <= 0)
1017 0 : cur_en = 0; /* not visible beyond top edge*/
1018 :
1019 0 : if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1020 0 : hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1021 :
1022 0 : REG_UPDATE(CURSOR_CONTROL,
1023 : CURSOR_ENABLE, cur_en);
1024 :
1025 0 : REG_SET_2(CURSOR_POSITION, 0,
1026 : CURSOR_X_POSITION, pos->x,
1027 : CURSOR_Y_POSITION, pos->y);
1028 :
1029 0 : REG_SET_2(CURSOR_HOT_SPOT, 0,
1030 : CURSOR_HOT_SPOT_X, x_hotspot,
1031 : CURSOR_HOT_SPOT_Y, y_hotspot);
1032 :
1033 0 : REG_SET(CURSOR_DST_OFFSET, 0,
1034 : CURSOR_DST_X_OFFSET, dst_x_offset);
1035 : /* TODO Handle surface pixel formats other than 4:4:4 */
1036 : }
1037 :
1038 0 : void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1039 : {
1040 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1041 0 : uint32_t clk_enable = enable ? 1 : 0;
1042 :
1043 0 : REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1044 0 : }
1045 :
1046 0 : void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1047 : {
1048 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1049 :
1050 0 : REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1051 0 : }
1052 :
1053 0 : void hubp2_clear_underflow(struct hubp *hubp)
1054 : {
1055 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1056 :
1057 0 : REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1058 0 : }
1059 :
1060 0 : void hubp2_read_state_common(struct hubp *hubp)
1061 : {
1062 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1063 0 : struct dcn_hubp_state *s = &hubp2->state;
1064 0 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1065 0 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1066 0 : struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1067 :
1068 : /* Requester */
1069 0 : REG_GET(HUBPRET_CONTROL,
1070 : DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1071 0 : REG_GET_4(DCN_EXPANSION_MODE,
1072 : DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1073 : PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1074 : MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1075 : CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1076 :
1077 0 : REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
1078 : MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
1079 :
1080 0 : REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
1081 : MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
1082 :
1083 : /* DLG - Per hubp */
1084 0 : REG_GET_2(BLANK_OFFSET_0,
1085 : REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1086 : DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1087 :
1088 0 : REG_GET(BLANK_OFFSET_1,
1089 : MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1090 :
1091 0 : REG_GET(DST_DIMENSIONS,
1092 : REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1093 :
1094 0 : REG_GET_2(DST_AFTER_SCALER,
1095 : REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1096 : DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1097 :
1098 0 : if (REG(PREFETCH_SETTINS))
1099 0 : REG_GET_2(PREFETCH_SETTINS,
1100 : DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1101 : VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1102 : else
1103 0 : REG_GET_2(PREFETCH_SETTINGS,
1104 : DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1105 : VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1106 :
1107 0 : REG_GET_2(VBLANK_PARAMETERS_0,
1108 : DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1109 : DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1110 :
1111 0 : REG_GET(REF_FREQ_TO_PIX_FREQ,
1112 : REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1113 :
1114 : /* DLG - Per luma/chroma */
1115 0 : REG_GET(VBLANK_PARAMETERS_1,
1116 : REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1117 :
1118 0 : REG_GET(VBLANK_PARAMETERS_3,
1119 : REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1120 :
1121 0 : if (REG(NOM_PARAMETERS_0))
1122 0 : REG_GET(NOM_PARAMETERS_0,
1123 : DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1124 :
1125 0 : if (REG(NOM_PARAMETERS_1))
1126 0 : REG_GET(NOM_PARAMETERS_1,
1127 : REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1128 :
1129 0 : REG_GET(NOM_PARAMETERS_4,
1130 : DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1131 :
1132 0 : REG_GET(NOM_PARAMETERS_5,
1133 : REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1134 :
1135 0 : REG_GET_2(PER_LINE_DELIVERY_PRE,
1136 : REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1137 : REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1138 :
1139 0 : REG_GET_2(PER_LINE_DELIVERY,
1140 : REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1141 : REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1142 :
1143 0 : if (REG(PREFETCH_SETTINS_C))
1144 0 : REG_GET(PREFETCH_SETTINS_C,
1145 : VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1146 : else
1147 0 : REG_GET(PREFETCH_SETTINGS_C,
1148 : VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1149 :
1150 0 : REG_GET(VBLANK_PARAMETERS_2,
1151 : REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1152 :
1153 0 : REG_GET(VBLANK_PARAMETERS_4,
1154 : REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1155 :
1156 0 : if (REG(NOM_PARAMETERS_2))
1157 0 : REG_GET(NOM_PARAMETERS_2,
1158 : DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1159 :
1160 0 : if (REG(NOM_PARAMETERS_3))
1161 0 : REG_GET(NOM_PARAMETERS_3,
1162 : REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1163 :
1164 0 : REG_GET(NOM_PARAMETERS_6,
1165 : DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1166 :
1167 0 : REG_GET(NOM_PARAMETERS_7,
1168 : REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1169 :
1170 : /* TTU - per hubp */
1171 0 : REG_GET_2(DCN_TTU_QOS_WM,
1172 : QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1173 : QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1174 :
1175 0 : REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1176 : MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1177 : QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1178 :
1179 : /* TTU - per luma/chroma */
1180 : /* Assumed surf0 is luma and 1 is chroma */
1181 :
1182 0 : REG_GET_3(DCN_SURF0_TTU_CNTL0,
1183 : REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1184 : QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1185 : QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1186 :
1187 0 : REG_GET(DCN_SURF0_TTU_CNTL1,
1188 : REFCYC_PER_REQ_DELIVERY_PRE,
1189 : &ttu_attr->refcyc_per_req_delivery_pre_l);
1190 :
1191 0 : REG_GET_3(DCN_SURF1_TTU_CNTL0,
1192 : REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1193 : QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1194 : QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1195 :
1196 0 : REG_GET(DCN_SURF1_TTU_CNTL1,
1197 : REFCYC_PER_REQ_DELIVERY_PRE,
1198 : &ttu_attr->refcyc_per_req_delivery_pre_c);
1199 :
1200 : /* Rest of hubp */
1201 0 : REG_GET(DCSURF_SURFACE_CONFIG,
1202 : SURFACE_PIXEL_FORMAT, &s->pixel_format);
1203 :
1204 0 : REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1205 : SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1206 :
1207 0 : REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1208 : SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1209 :
1210 0 : REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1211 : PRI_VIEWPORT_WIDTH, &s->viewport_width,
1212 : PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1213 :
1214 0 : REG_GET_2(DCSURF_SURFACE_CONFIG,
1215 : ROTATION_ANGLE, &s->rotation_angle,
1216 : H_MIRROR_EN, &s->h_mirror_en);
1217 :
1218 0 : REG_GET(DCSURF_TILING_CONFIG,
1219 : SW_MODE, &s->sw_mode);
1220 :
1221 0 : REG_GET(DCSURF_SURFACE_CONTROL,
1222 : PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1223 :
1224 0 : REG_GET_3(DCHUBP_CNTL,
1225 : HUBP_BLANK_EN, &s->blank_en,
1226 : HUBP_TTU_DISABLE, &s->ttu_disable,
1227 : HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1228 :
1229 0 : REG_GET(HUBP_CLK_CNTL,
1230 : HUBP_CLOCK_ENABLE, &s->clock_en);
1231 :
1232 0 : REG_GET(DCN_GLOBAL_TTU_CNTL,
1233 : MIN_TTU_VBLANK, &s->min_ttu_vblank);
1234 :
1235 0 : REG_GET_2(DCN_TTU_QOS_WM,
1236 : QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1237 : QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1238 :
1239 0 : REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1240 : PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1241 :
1242 0 : REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1243 : PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1244 :
1245 0 : REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1246 : PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1247 :
1248 0 : REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1249 : PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1250 0 : }
1251 :
1252 0 : void hubp2_read_state(struct hubp *hubp)
1253 : {
1254 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1255 0 : struct dcn_hubp_state *s = &hubp2->state;
1256 0 : struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1257 :
1258 0 : hubp2_read_state_common(hubp);
1259 :
1260 0 : REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1261 : CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1262 : MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1263 : META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1264 : MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1265 : DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1266 : MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1267 : SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1268 : PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1269 :
1270 0 : REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1271 : CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1272 : MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1273 : META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1274 : MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1275 : DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1276 : MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1277 : SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1278 : PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1279 :
1280 0 : }
1281 :
1282 0 : static void hubp2_validate_dml_output(struct hubp *hubp,
1283 : struct dc_context *ctx,
1284 : struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1285 : struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1286 : struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1287 : {
1288 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1289 0 : struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1290 0 : struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1291 0 : struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1292 : DC_LOGGER_INIT(ctx->logger);
1293 0 : DC_LOG_DEBUG("DML Validation | Running Validation");
1294 :
1295 : /* Requestor Regs */
1296 0 : REG_GET(HUBPRET_CONTROL,
1297 : DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1298 0 : REG_GET_4(DCN_EXPANSION_MODE,
1299 : DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1300 : PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1301 : MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1302 : CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1303 0 : REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1304 : CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1305 : MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1306 : META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1307 : MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1308 : DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1309 : MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1310 : SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1311 : PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1312 0 : REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1313 : CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1314 : MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1315 : META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1316 : MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1317 : DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1318 : MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1319 : SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1320 : PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1321 :
1322 0 : if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1323 0 : DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
1324 : dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1325 0 : if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1326 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1327 : dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1328 0 : if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1329 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1330 : dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1331 0 : if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1332 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
1333 : dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1334 0 : if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1335 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1336 : dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1337 :
1338 0 : if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1339 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
1340 : dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1341 0 : if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1342 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
1343 : dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1344 0 : if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1345 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
1346 : dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1347 0 : if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1348 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",
1349 : dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1350 0 : if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1351 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
1352 : dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1353 0 : if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1354 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
1355 : dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1356 0 : if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1357 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
1358 : dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1359 0 : if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1360 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",
1361 : dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1362 :
1363 0 : if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1364 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1365 : dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1366 0 : if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1367 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1368 : dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1369 0 : if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1370 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1371 : dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1372 0 : if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1373 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1374 : dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1375 0 : if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1376 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
1377 : dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1378 0 : if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1379 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
1380 : dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1381 0 : if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1382 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",
1383 : dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1384 0 : if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1385 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",
1386 : dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1387 :
1388 : /* DLG - Per hubp */
1389 0 : REG_GET_2(BLANK_OFFSET_0,
1390 : REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1391 : DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1392 0 : REG_GET(BLANK_OFFSET_1,
1393 : MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1394 0 : REG_GET(DST_DIMENSIONS,
1395 : REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1396 0 : REG_GET_2(DST_AFTER_SCALER,
1397 : REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1398 : DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1399 0 : REG_GET(REF_FREQ_TO_PIX_FREQ,
1400 : REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1401 :
1402 0 : if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1403 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",
1404 : dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1405 0 : if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1406 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",
1407 : dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1408 0 : if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1409 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
1410 : dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1411 0 : if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1412 0 : DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",
1413 : dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1414 0 : if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1415 0 : DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",
1416 : dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1417 0 : if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1418 0 : DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",
1419 : dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1420 0 : if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1421 0 : DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",
1422 : dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1423 :
1424 : /* DLG - Per luma/chroma */
1425 0 : REG_GET(VBLANK_PARAMETERS_1,
1426 : REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1427 0 : if (REG(NOM_PARAMETERS_0))
1428 0 : REG_GET(NOM_PARAMETERS_0,
1429 : DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1430 0 : if (REG(NOM_PARAMETERS_1))
1431 0 : REG_GET(NOM_PARAMETERS_1,
1432 : REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1433 0 : REG_GET(NOM_PARAMETERS_4,
1434 : DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1435 0 : REG_GET(NOM_PARAMETERS_5,
1436 : REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1437 0 : REG_GET_2(PER_LINE_DELIVERY,
1438 : REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1439 : REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1440 0 : REG_GET_2(PER_LINE_DELIVERY_PRE,
1441 : REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1442 : REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1443 0 : REG_GET(VBLANK_PARAMETERS_2,
1444 : REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1445 0 : if (REG(NOM_PARAMETERS_2))
1446 0 : REG_GET(NOM_PARAMETERS_2,
1447 : DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1448 0 : if (REG(NOM_PARAMETERS_3))
1449 0 : REG_GET(NOM_PARAMETERS_3,
1450 : REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1451 0 : REG_GET(NOM_PARAMETERS_6,
1452 : DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1453 0 : REG_GET(NOM_PARAMETERS_7,
1454 : REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1455 0 : REG_GET(VBLANK_PARAMETERS_3,
1456 : REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1457 0 : REG_GET(VBLANK_PARAMETERS_4,
1458 : REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1459 :
1460 0 : if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1461 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",
1462 : dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1463 0 : if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1464 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",
1465 : dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1466 0 : if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1467 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",
1468 : dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1469 0 : if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1470 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",
1471 : dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1472 0 : if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1473 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",
1474 : dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1475 0 : if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1476 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",
1477 : dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1478 0 : if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1479 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",
1480 : dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1481 0 : if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1482 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",
1483 : dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1484 0 : if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1485 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",
1486 : dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1487 0 : if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1488 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",
1489 : dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1490 0 : if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1491 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",
1492 : dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1493 0 : if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1494 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",
1495 : dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1496 0 : if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1497 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",
1498 : dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1499 0 : if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1500 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",
1501 : dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1502 0 : if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1503 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",
1504 : dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1505 0 : if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1506 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",
1507 : dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1508 :
1509 : /* TTU - per hubp */
1510 0 : REG_GET_2(DCN_TTU_QOS_WM,
1511 : QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1512 : QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1513 :
1514 0 : if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1515 0 : DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",
1516 : dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1517 0 : if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1518 0 : DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
1519 : dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1520 :
1521 : /* TTU - per luma/chroma */
1522 : /* Assumed surf0 is luma and 1 is chroma */
1523 0 : REG_GET_3(DCN_SURF0_TTU_CNTL0,
1524 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1525 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1526 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1527 0 : REG_GET_3(DCN_SURF1_TTU_CNTL0,
1528 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1529 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1530 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1531 0 : REG_GET_3(DCN_CUR0_TTU_CNTL0,
1532 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1533 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1534 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1535 0 : REG_GET(FLIP_PARAMETERS_1,
1536 : REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1537 0 : REG_GET(DCN_CUR0_TTU_CNTL1,
1538 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1539 0 : REG_GET(DCN_CUR1_TTU_CNTL1,
1540 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1541 0 : REG_GET(DCN_SURF0_TTU_CNTL1,
1542 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1543 0 : REG_GET(DCN_SURF1_TTU_CNTL1,
1544 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1545 :
1546 0 : if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1547 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1548 : dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1549 0 : if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1550 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1551 : dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1552 0 : if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1553 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1554 : dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1555 0 : if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1556 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1557 : dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1558 0 : if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1559 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1560 : dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1561 0 : if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1562 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1563 : dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1564 0 : if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1565 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1566 : dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1567 0 : if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1568 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1569 : dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1570 0 : if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1571 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1572 : dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1573 0 : if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1574 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",
1575 : dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1576 0 : if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1577 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1578 : dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1579 0 : if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1580 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1581 : dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1582 0 : if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1583 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1584 : dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1585 0 : if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1586 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1587 : dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1588 0 : }
1589 :
1590 : static struct hubp_funcs dcn20_hubp_funcs = {
1591 : .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1592 : .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1593 : .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1594 : .hubp_program_surface_config = hubp2_program_surface_config,
1595 : .hubp_is_flip_pending = hubp2_is_flip_pending,
1596 : .hubp_setup = hubp2_setup,
1597 : .hubp_setup_interdependent = hubp2_setup_interdependent,
1598 : .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1599 : .set_blank = hubp2_set_blank,
1600 : .set_blank_regs = hubp2_set_blank_regs,
1601 : .dcc_control = hubp2_dcc_control,
1602 : .mem_program_viewport = min_set_viewport,
1603 : .set_cursor_attributes = hubp2_cursor_set_attributes,
1604 : .set_cursor_position = hubp2_cursor_set_position,
1605 : .hubp_clk_cntl = hubp2_clk_cntl,
1606 : .hubp_vtg_sel = hubp2_vtg_sel,
1607 : .dmdata_set_attributes = hubp2_dmdata_set_attributes,
1608 : .dmdata_load = hubp2_dmdata_load,
1609 : .dmdata_status_done = hubp2_dmdata_status_done,
1610 : .hubp_read_state = hubp2_read_state,
1611 : .hubp_clear_underflow = hubp2_clear_underflow,
1612 : .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1613 : .hubp_init = hubp1_init,
1614 : .validate_dml_output = hubp2_validate_dml_output,
1615 : .hubp_in_blank = hubp1_in_blank,
1616 : .hubp_soft_reset = hubp1_soft_reset,
1617 : .hubp_set_flip_int = hubp1_set_flip_int,
1618 : };
1619 :
1620 :
1621 0 : bool hubp2_construct(
1622 : struct dcn20_hubp *hubp2,
1623 : struct dc_context *ctx,
1624 : uint32_t inst,
1625 : const struct dcn_hubp2_registers *hubp_regs,
1626 : const struct dcn_hubp2_shift *hubp_shift,
1627 : const struct dcn_hubp2_mask *hubp_mask)
1628 : {
1629 0 : hubp2->base.funcs = &dcn20_hubp_funcs;
1630 0 : hubp2->base.ctx = ctx;
1631 0 : hubp2->hubp_regs = hubp_regs;
1632 0 : hubp2->hubp_shift = hubp_shift;
1633 0 : hubp2->hubp_mask = hubp_mask;
1634 0 : hubp2->base.inst = inst;
1635 0 : hubp2->base.opp_id = OPP_ID_INVALID;
1636 0 : hubp2->base.mpcc_id = 0xf;
1637 :
1638 0 : return true;
1639 : }
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