Line data Source code
1 : /*
2 : * Copyright 2012-15 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include <linux/delay.h>
27 :
28 : #include "dc_bios_types.h"
29 : #include "dcn20_stream_encoder.h"
30 : #include "reg_helper.h"
31 : #include "hw_shared.h"
32 : #include "inc/link_dpcd.h"
33 : #include "dpcd_defs.h"
34 :
35 : #define DC_LOGGER \
36 : enc1->base.ctx->logger
37 :
38 : #define REG(reg)\
39 : (enc1->regs->reg)
40 :
41 : #undef FN
42 : #define FN(reg_name, field_name) \
43 : enc1->se_shift->field_name, enc1->se_mask->field_name
44 :
45 :
46 : #define CTX \
47 : enc1->base.ctx
48 :
49 :
50 0 : static void enc2_update_hdmi_info_packet(
51 : struct dcn10_stream_encoder *enc1,
52 : uint32_t packet_index,
53 : const struct dc_info_packet *info_packet)
54 : {
55 : uint32_t cont, send, line;
56 :
57 0 : if (info_packet->valid) {
58 0 : enc1_update_generic_info_packet(
59 : enc1,
60 : packet_index,
61 : info_packet);
62 :
63 : /* enable transmission of packet(s) -
64 : * packet transmission begins on the next frame */
65 0 : cont = 1;
66 : /* send packet(s) every frame */
67 0 : send = 1;
68 : /* select line number to send packets on */
69 0 : line = 2;
70 : } else {
71 : cont = 0;
72 : send = 0;
73 : line = 0;
74 : }
75 :
76 : /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
77 :
78 : /* choose which generic packet control to use */
79 0 : switch (packet_index) {
80 : case 0:
81 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
82 : HDMI_GENERIC0_CONT, cont,
83 : HDMI_GENERIC0_SEND, send);
84 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
85 : HDMI_GENERIC0_LINE, line);
86 0 : break;
87 : case 1:
88 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
89 : HDMI_GENERIC1_CONT, cont,
90 : HDMI_GENERIC1_SEND, send);
91 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
92 : HDMI_GENERIC1_LINE, line);
93 0 : break;
94 : case 2:
95 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
96 : HDMI_GENERIC2_CONT, cont,
97 : HDMI_GENERIC2_SEND, send);
98 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
99 : HDMI_GENERIC2_LINE, line);
100 0 : break;
101 : case 3:
102 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
103 : HDMI_GENERIC3_CONT, cont,
104 : HDMI_GENERIC3_SEND, send);
105 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
106 : HDMI_GENERIC3_LINE, line);
107 0 : break;
108 : case 4:
109 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
110 : HDMI_GENERIC4_CONT, cont,
111 : HDMI_GENERIC4_SEND, send);
112 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
113 : HDMI_GENERIC4_LINE, line);
114 0 : break;
115 : case 5:
116 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
117 : HDMI_GENERIC5_CONT, cont,
118 : HDMI_GENERIC5_SEND, send);
119 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
120 : HDMI_GENERIC5_LINE, line);
121 0 : break;
122 : case 6:
123 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
124 : HDMI_GENERIC6_CONT, cont,
125 : HDMI_GENERIC6_SEND, send);
126 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
127 : HDMI_GENERIC6_LINE, line);
128 0 : break;
129 : case 7:
130 0 : REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
131 : HDMI_GENERIC7_CONT, cont,
132 : HDMI_GENERIC7_SEND, send);
133 0 : REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
134 : HDMI_GENERIC7_LINE, line);
135 0 : break;
136 : default:
137 : /* invalid HW packet index */
138 0 : DC_LOG_WARNING(
139 : "Invalid HW packet index: %s()\n",
140 : __func__);
141 0 : return;
142 : }
143 : }
144 :
145 0 : static void enc2_stream_encoder_update_hdmi_info_packets(
146 : struct stream_encoder *enc,
147 : const struct encoder_info_frame *info_frame)
148 : {
149 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
150 :
151 : /* for bring up, disable dp double TODO */
152 0 : REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
153 :
154 : /*Always add mandatory packets first followed by optional ones*/
155 0 : enc2_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
156 0 : enc2_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
157 0 : enc2_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
158 0 : enc2_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
159 0 : enc2_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
160 0 : enc2_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
161 0 : enc2_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
162 0 : }
163 :
164 0 : static void enc2_stream_encoder_stop_hdmi_info_packets(
165 : struct stream_encoder *enc)
166 : {
167 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
168 :
169 : /* stop generic packets 0,1 on HDMI */
170 0 : REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
171 : HDMI_GENERIC0_CONT, 0,
172 : HDMI_GENERIC0_SEND, 0,
173 : HDMI_GENERIC1_CONT, 0,
174 : HDMI_GENERIC1_SEND, 0);
175 0 : REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
176 : HDMI_GENERIC0_LINE, 0,
177 : HDMI_GENERIC1_LINE, 0);
178 :
179 : /* stop generic packets 2,3 on HDMI */
180 0 : REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
181 : HDMI_GENERIC2_CONT, 0,
182 : HDMI_GENERIC2_SEND, 0,
183 : HDMI_GENERIC3_CONT, 0,
184 : HDMI_GENERIC3_SEND, 0);
185 0 : REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
186 : HDMI_GENERIC2_LINE, 0,
187 : HDMI_GENERIC3_LINE, 0);
188 :
189 : /* stop generic packets 4,5 on HDMI */
190 0 : REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
191 : HDMI_GENERIC4_CONT, 0,
192 : HDMI_GENERIC4_SEND, 0,
193 : HDMI_GENERIC5_CONT, 0,
194 : HDMI_GENERIC5_SEND, 0);
195 0 : REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
196 : HDMI_GENERIC4_LINE, 0,
197 : HDMI_GENERIC5_LINE, 0);
198 :
199 : /* stop generic packets 6,7 on HDMI */
200 0 : REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
201 : HDMI_GENERIC6_CONT, 0,
202 : HDMI_GENERIC6_SEND, 0,
203 : HDMI_GENERIC7_CONT, 0,
204 : HDMI_GENERIC7_SEND, 0);
205 0 : REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
206 : HDMI_GENERIC6_LINE, 0,
207 : HDMI_GENERIC7_LINE, 0);
208 0 : }
209 :
210 :
211 : /* Update GSP7 SDP 128 byte long */
212 0 : static void enc2_update_gsp7_128_info_packet(
213 : struct dcn10_stream_encoder *enc1,
214 : const struct dc_info_packet_128 *info_packet,
215 : bool immediate_update)
216 : {
217 : uint32_t i;
218 :
219 : /* TODOFPGA Figure out a proper number for max_retries polling for lock
220 : * use 50 for now.
221 : */
222 0 : uint32_t max_retries = 50;
223 0 : const uint32_t *content = (const uint32_t *) &info_packet->sb[0];
224 :
225 0 : ASSERT(info_packet->hb1 == DC_DP_INFOFRAME_TYPE_PPS);
226 :
227 : /* Configure for PPS packet size (128 bytes) */
228 0 : REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1);
229 :
230 : /* We need turn on clock before programming AFMT block*/
231 0 : REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
232 :
233 : /* Poll dig_update_lock is not locked -> asic internal signal
234 : * assumes otg master lock will unlock it
235 : */
236 : /*REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 0, 10, max_retries);*/
237 :
238 : /* Wait for HW/SW GSP memory access conflict to go away */
239 0 : REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
240 : 0, 10, max_retries);
241 :
242 : /* Clear HW/SW memory access conflict flag */
243 0 : REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
244 :
245 : /* write generic packet header */
246 0 : REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);
247 0 : REG_SET_4(AFMT_GENERIC_HDR, 0,
248 : AFMT_GENERIC_HB0, info_packet->hb0,
249 : AFMT_GENERIC_HB1, info_packet->hb1,
250 : AFMT_GENERIC_HB2, info_packet->hb2,
251 : AFMT_GENERIC_HB3, info_packet->hb3);
252 :
253 : /* Write generic packet content 128 bytes long. Four sets are used (indexes 7
254 : * through 10) to fit 128 bytes.
255 : */
256 0 : for (i = 0; i < 4; i++) {
257 0 : uint32_t packet_index = 7 + i;
258 0 : REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);
259 :
260 0 : REG_WRITE(AFMT_GENERIC_0, *content++);
261 0 : REG_WRITE(AFMT_GENERIC_1, *content++);
262 0 : REG_WRITE(AFMT_GENERIC_2, *content++);
263 0 : REG_WRITE(AFMT_GENERIC_3, *content++);
264 0 : REG_WRITE(AFMT_GENERIC_4, *content++);
265 0 : REG_WRITE(AFMT_GENERIC_5, *content++);
266 0 : REG_WRITE(AFMT_GENERIC_6, *content++);
267 0 : REG_WRITE(AFMT_GENERIC_7, *content++);
268 : }
269 :
270 0 : REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL1,
271 : AFMT_GENERIC7_FRAME_UPDATE, !immediate_update,
272 : AFMT_GENERIC7_IMMEDIATE_UPDATE, immediate_update);
273 0 : }
274 :
275 : /* Set DSC-related configuration.
276 : * dsc_mode: 0 disables DSC, other values enable DSC in specified format
277 : * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
278 : * dsc_slice_width: Slice width in pixels
279 : */
280 0 : static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
281 : enum optc_dsc_mode dsc_mode,
282 : uint32_t dsc_bytes_per_pixel,
283 : uint32_t dsc_slice_width)
284 : {
285 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
286 :
287 0 : REG_UPDATE_2(DP_DSC_CNTL,
288 : DP_DSC_MODE, dsc_mode,
289 : DP_DSC_SLICE_WIDTH, dsc_slice_width);
290 :
291 0 : REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
292 : DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
293 0 : }
294 :
295 :
296 0 : static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
297 : bool enable,
298 : uint8_t *dsc_packed_pps,
299 : bool immediate_update)
300 : {
301 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
302 :
303 0 : if (enable) {
304 : struct dc_info_packet_128 pps_sdp;
305 :
306 0 : ASSERT(dsc_packed_pps);
307 :
308 : /* Load PPS into infoframe (SDP) registers */
309 0 : pps_sdp.valid = true;
310 0 : pps_sdp.hb0 = 0;
311 0 : pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
312 0 : pps_sdp.hb2 = 127;
313 0 : pps_sdp.hb3 = 0;
314 0 : memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
315 0 : enc2_update_gsp7_128_info_packet(enc1, &pps_sdp, immediate_update);
316 :
317 : /* Enable Generic Stream Packet 7 (GSP) transmission */
318 : //REG_UPDATE(DP_SEC_CNTL,
319 : // DP_SEC_GSP7_ENABLE, 1);
320 :
321 : /* SW should make sure VBID[6] update line number is bigger
322 : * than PPS transmit line number
323 : */
324 0 : REG_UPDATE(DP_SEC_CNTL6,
325 : DP_SEC_GSP7_LINE_NUM, 2);
326 0 : REG_UPDATE_2(DP_MSA_VBID_MISC,
327 : DP_VBID6_LINE_REFERENCE, 0,
328 : DP_VBID6_LINE_NUM, 3);
329 :
330 : /* Send PPS data at the line number specified above.
331 : * DP spec requires PPS to be sent only when it changes, however since
332 : * decoder has to be able to handle its change on every frame, we're
333 : * sending it always (i.e. on every frame) to reduce the chance it'd be
334 : * missed by decoder. If it turns out required to send PPS only when it
335 : * changes, we can use DP_SEC_GSP7_SEND register.
336 : */
337 0 : REG_UPDATE_2(DP_SEC_CNTL,
338 : DP_SEC_GSP7_ENABLE, 1,
339 : DP_SEC_STREAM_ENABLE, 1);
340 : } else {
341 : /* Disable Generic Stream Packet 7 (GSP) transmission */
342 0 : REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0);
343 0 : REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);
344 : }
345 0 : }
346 :
347 :
348 : /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
349 : * into a dcn_dsc_state struct.
350 : */
351 0 : static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s)
352 : {
353 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
354 :
355 : //if dsc is enabled, continue to read
356 0 : REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
357 0 : if (s->dsc_mode) {
358 0 : REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
359 0 : REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num);
360 :
361 0 : REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
362 0 : REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
363 :
364 0 : REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable);
365 0 : REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
366 : }
367 0 : }
368 :
369 : /* Set Dynamic Metadata-configuration.
370 : * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME
371 : * hubp_requestor_id: HUBP physical instance that is the source of dynamic metadata
372 : * only needs to be set when enable_dme is TRUE
373 : * dmdata_mode: dynamic metadata packet type: DP, HDMI, or Dolby Vision
374 : *
375 : * Ensure the OTG master update lock is set when changing DME configuration.
376 : */
377 0 : void enc2_set_dynamic_metadata(struct stream_encoder *enc,
378 : bool enable_dme,
379 : uint32_t hubp_requestor_id,
380 : enum dynamic_metadata_mode dmdata_mode)
381 : {
382 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
383 :
384 0 : if (enable_dme) {
385 0 : REG_UPDATE_2(DME_CONTROL,
386 : METADATA_HUBP_REQUESTOR_ID, hubp_requestor_id,
387 : METADATA_STREAM_TYPE, (dmdata_mode == dmdata_dolby_vision) ? 1 : 0);
388 :
389 : /* Use default line reference DP_SOF for bringup.
390 : * Should use OTG_SOF for DRR cases
391 : */
392 0 : if (dmdata_mode == dmdata_dp)
393 0 : REG_UPDATE_3(DP_SEC_METADATA_TRANSMISSION,
394 : DP_SEC_METADATA_PACKET_ENABLE, 1,
395 : DP_SEC_METADATA_PACKET_LINE_REFERENCE, 0,
396 : DP_SEC_METADATA_PACKET_LINE, 20);
397 : else {
398 0 : REG_UPDATE_3(HDMI_METADATA_PACKET_CONTROL,
399 : HDMI_METADATA_PACKET_ENABLE, 1,
400 : HDMI_METADATA_PACKET_LINE_REFERENCE, 0,
401 : HDMI_METADATA_PACKET_LINE, 2);
402 :
403 0 : if (dmdata_mode == dmdata_dolby_vision)
404 0 : REG_UPDATE(DIG_FE_CNTL,
405 : DOLBY_VISION_EN, 1);
406 : }
407 :
408 0 : REG_UPDATE(DME_CONTROL,
409 : METADATA_ENGINE_EN, 1);
410 : } else {
411 0 : REG_UPDATE(DME_CONTROL,
412 : METADATA_ENGINE_EN, 0);
413 :
414 0 : if (dmdata_mode == dmdata_dp)
415 0 : REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,
416 : DP_SEC_METADATA_PACKET_ENABLE, 0);
417 : else {
418 0 : REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,
419 : HDMI_METADATA_PACKET_ENABLE, 0);
420 0 : REG_UPDATE(DIG_FE_CNTL,
421 : DOLBY_VISION_EN, 0);
422 : }
423 : }
424 0 : }
425 :
426 0 : static void enc2_stream_encoder_update_dp_info_packets(
427 : struct stream_encoder *enc,
428 : const struct encoder_info_frame *info_frame)
429 : {
430 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
431 0 : uint32_t dmdata_packet_enabled = 0;
432 :
433 0 : enc1_stream_encoder_update_dp_info_packets(enc, info_frame);
434 :
435 : /* check if dynamic metadata packet transmission is enabled */
436 0 : REG_GET(DP_SEC_METADATA_TRANSMISSION,
437 : DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
438 :
439 0 : if (dmdata_packet_enabled)
440 0 : REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
441 0 : }
442 :
443 : static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
444 : {
445 0 : bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
446 :
447 0 : two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
448 0 : && !timing->dsc_cfg.ycbcr422_simple);
449 : return two_pix;
450 : }
451 :
452 0 : void enc2_stream_encoder_dp_unblank(
453 : struct dc_link *link,
454 : struct stream_encoder *enc,
455 : const struct encoder_unblank_param *param)
456 : {
457 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
458 :
459 0 : if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
460 0 : uint32_t n_vid = 0x8000;
461 : uint32_t m_vid;
462 0 : uint32_t n_multiply = 0;
463 0 : uint64_t m_vid_l = n_vid;
464 :
465 : /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
466 0 : if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
467 : /*this logic should be the same in get_pixel_clock_parameters() */
468 0 : n_multiply = 1;
469 : }
470 : /* M / N = Fstream / Flink
471 : * m_vid / n_vid = pixel rate / link rate
472 : */
473 :
474 0 : m_vid_l *= param->timing.pix_clk_100hz / 10;
475 0 : m_vid_l = div_u64(m_vid_l,
476 : param->link_settings.link_rate
477 : * LINK_RATE_REF_FREQ_IN_KHZ);
478 :
479 0 : m_vid = (uint32_t) m_vid_l;
480 :
481 : /* enable auto measurement */
482 :
483 0 : REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
484 :
485 : /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
486 : * therefore program initial value for Mvid and Nvid
487 : */
488 :
489 0 : REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
490 :
491 0 : REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
492 :
493 0 : REG_UPDATE_2(DP_VID_TIMING,
494 : DP_VID_M_N_GEN_EN, 1,
495 : DP_VID_N_MUL, n_multiply);
496 : }
497 :
498 : /* make sure stream is disabled before resetting steer fifo */
499 0 : REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
500 0 : REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
501 :
502 : /* set DIG_START to 0x1 to reset FIFO */
503 0 : REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
504 0 : udelay(1);
505 :
506 : /* write 0 to take the FIFO out of reset */
507 :
508 0 : REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
509 :
510 : /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
511 : * that it overflows during mode transition, and sometimes doesn't recover.
512 : */
513 0 : REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
514 0 : udelay(10);
515 :
516 0 : REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
517 :
518 : /* wait 100us for DIG/DP logic to prime
519 : * (i.e. a few video lines)
520 : */
521 0 : udelay(100);
522 :
523 : /* the hardware would start sending video at the start of the next DP
524 : * frame (i.e. rising edge of the vblank).
525 : * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
526 : * register has no effect on enable transition! HW always guarantees
527 : * VID_STREAM enable at start of next frame, and this is not
528 : * programmable
529 : */
530 :
531 0 : REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
532 :
533 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
534 0 : }
535 :
536 0 : static void enc2_dp_set_odm_combine(
537 : struct stream_encoder *enc,
538 : bool odm_combine)
539 : {
540 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
541 :
542 0 : REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
543 0 : }
544 :
545 0 : void enc2_stream_encoder_dp_set_stream_attribute(
546 : struct stream_encoder *enc,
547 : struct dc_crtc_timing *crtc_timing,
548 : enum dc_color_space output_color_space,
549 : bool use_vsc_sdp_for_colorimetry,
550 : uint32_t enable_sdp_splitting)
551 : {
552 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
553 :
554 0 : enc1_stream_encoder_dp_set_stream_attribute(enc,
555 : crtc_timing,
556 : output_color_space,
557 : use_vsc_sdp_for_colorimetry,
558 : enable_sdp_splitting);
559 :
560 0 : REG_UPDATE(DP_SEC_FRAMING4,
561 : DP_SST_SDP_SPLITTING, enable_sdp_splitting);
562 0 : }
563 :
564 0 : uint32_t enc2_get_fifo_cal_average_level(
565 : struct stream_encoder *enc)
566 : {
567 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
568 : uint32_t fifo_level;
569 :
570 0 : REG_GET(DIG_FIFO_STATUS,
571 : DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level);
572 0 : return fifo_level;
573 : }
574 :
575 : static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
576 : .dp_set_odm_combine =
577 : enc2_dp_set_odm_combine,
578 : .dp_set_stream_attribute =
579 : enc2_stream_encoder_dp_set_stream_attribute,
580 : .hdmi_set_stream_attribute =
581 : enc1_stream_encoder_hdmi_set_stream_attribute,
582 : .dvi_set_stream_attribute =
583 : enc1_stream_encoder_dvi_set_stream_attribute,
584 : .set_throttled_vcp_size =
585 : enc1_stream_encoder_set_throttled_vcp_size,
586 : .update_hdmi_info_packets =
587 : enc2_stream_encoder_update_hdmi_info_packets,
588 : .stop_hdmi_info_packets =
589 : enc2_stream_encoder_stop_hdmi_info_packets,
590 : .update_dp_info_packets =
591 : enc2_stream_encoder_update_dp_info_packets,
592 : .send_immediate_sdp_message =
593 : enc1_stream_encoder_send_immediate_sdp_message,
594 : .stop_dp_info_packets =
595 : enc1_stream_encoder_stop_dp_info_packets,
596 : .dp_blank =
597 : enc1_stream_encoder_dp_blank,
598 : .dp_unblank =
599 : enc2_stream_encoder_dp_unblank,
600 : .audio_mute_control = enc1_se_audio_mute_control,
601 :
602 : .dp_audio_setup = enc1_se_dp_audio_setup,
603 : .dp_audio_enable = enc1_se_dp_audio_enable,
604 : .dp_audio_disable = enc1_se_dp_audio_disable,
605 :
606 : .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
607 : .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
608 : .setup_stereo_sync = enc1_setup_stereo_sync,
609 : .set_avmute = enc1_stream_encoder_set_avmute,
610 : .dig_connect_to_otg = enc1_dig_connect_to_otg,
611 : .dig_source_otg = enc1_dig_source_otg,
612 :
613 : .dp_get_pixel_format =
614 : enc1_stream_encoder_dp_get_pixel_format,
615 :
616 : .enc_read_state = enc2_read_state,
617 : .dp_set_dsc_config = enc2_dp_set_dsc_config,
618 : .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
619 : .set_dynamic_metadata = enc2_set_dynamic_metadata,
620 : .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
621 : .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
622 : };
623 :
624 0 : void dcn20_stream_encoder_construct(
625 : struct dcn10_stream_encoder *enc1,
626 : struct dc_context *ctx,
627 : struct dc_bios *bp,
628 : enum engine_id eng_id,
629 : const struct dcn10_stream_enc_registers *regs,
630 : const struct dcn10_stream_encoder_shift *se_shift,
631 : const struct dcn10_stream_encoder_mask *se_mask)
632 : {
633 0 : enc1->base.funcs = &dcn20_str_enc_funcs;
634 0 : enc1->base.ctx = ctx;
635 0 : enc1->base.id = eng_id;
636 0 : enc1->base.bp = bp;
637 0 : enc1->regs = regs;
638 0 : enc1->se_shift = se_shift;
639 0 : enc1->se_mask = se_mask;
640 0 : enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
641 0 : }
642 :
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