Line data Source code
1 : /*
2 : * Copyright 2012-17 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 : #include "dcn201_hubp.h"
26 :
27 : #include "dm_services.h"
28 : #include "dce_calcs.h"
29 : #include "reg_helper.h"
30 : #include "basics/conversion.h"
31 :
32 : #define REG(reg)\
33 : hubp201->hubp_regs->reg
34 :
35 : #define CTX \
36 : hubp201->base.ctx
37 :
38 : #undef FN
39 : #define FN(reg_name, field_name) \
40 : hubp201->hubp_shift->field_name, hubp201->hubp_mask->field_name
41 :
42 0 : static void hubp201_program_surface_config(
43 : struct hubp *hubp,
44 : enum surface_pixel_format format,
45 : union dc_tiling_info *tiling_info,
46 : struct plane_size *plane_size,
47 : enum dc_rotation_angle rotation,
48 : struct dc_plane_dcc_param *dcc,
49 : bool horizontal_mirror,
50 : unsigned int compat_level)
51 : {
52 0 : hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
53 0 : hubp1_program_tiling(hubp, tiling_info, format);
54 0 : hubp1_program_size(hubp, format, plane_size, dcc);
55 0 : hubp1_program_pixel_format(hubp, format);
56 0 : }
57 :
58 : static void hubp201_program_deadline(
59 : struct hubp *hubp,
60 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
61 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
62 : {
63 0 : hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
64 : }
65 :
66 0 : static void hubp201_program_requestor(struct hubp *hubp,
67 : struct _vcs_dpi_display_rq_regs_st *rq_regs)
68 : {
69 0 : struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);
70 :
71 0 : REG_UPDATE(HUBPRET_CONTROL,
72 : DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
73 :
74 0 : REG_SET_4(DCN_EXPANSION_MODE, 0,
75 : DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
76 : PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
77 : MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
78 : CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
79 :
80 0 : REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,
81 : CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
82 : MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
83 : META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
84 : MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
85 : SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height);
86 :
87 0 : REG_SET_5(DCHUBP_REQ_SIZE_CONFIG_C, 0,
88 : CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
89 : MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
90 : META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
91 : MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
92 : SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height);
93 0 : }
94 :
95 0 : static void hubp201_setup(
96 : struct hubp *hubp,
97 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
98 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
99 : struct _vcs_dpi_display_rq_regs_st *rq_regs,
100 : struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
101 : {
102 0 : hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
103 0 : hubp201_program_requestor(hubp, rq_regs);
104 0 : hubp201_program_deadline(hubp, dlg_attr, ttu_attr);
105 0 : }
106 :
107 : static struct hubp_funcs dcn201_hubp_funcs = {
108 : .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
109 : .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
110 : .hubp_program_surface_flip_and_addr = hubp1_program_surface_flip_and_addr,
111 : .hubp_program_surface_config = hubp201_program_surface_config,
112 : .hubp_is_flip_pending = hubp1_is_flip_pending,
113 : .hubp_setup = hubp201_setup,
114 : .hubp_setup_interdependent = hubp2_setup_interdependent,
115 : .set_cursor_attributes = hubp2_cursor_set_attributes,
116 : .set_cursor_position = hubp1_cursor_set_position,
117 : .set_blank = hubp1_set_blank,
118 : .dcc_control = hubp1_dcc_control,
119 : .mem_program_viewport = min_set_viewport,
120 : .hubp_clk_cntl = hubp1_clk_cntl,
121 : .hubp_vtg_sel = hubp1_vtg_sel,
122 : .dmdata_set_attributes = hubp2_dmdata_set_attributes,
123 : .dmdata_load = hubp2_dmdata_load,
124 : .dmdata_status_done = hubp2_dmdata_status_done,
125 : .hubp_read_state = hubp2_read_state,
126 : .hubp_clear_underflow = hubp1_clear_underflow,
127 : .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
128 : .hubp_init = hubp1_init,
129 : };
130 :
131 0 : bool dcn201_hubp_construct(
132 : struct dcn201_hubp *hubp201,
133 : struct dc_context *ctx,
134 : uint32_t inst,
135 : const struct dcn201_hubp_registers *hubp_regs,
136 : const struct dcn201_hubp_shift *hubp_shift,
137 : const struct dcn201_hubp_mask *hubp_mask)
138 : {
139 0 : hubp201->base.funcs = &dcn201_hubp_funcs;
140 0 : hubp201->base.ctx = ctx;
141 0 : hubp201->hubp_regs = hubp_regs;
142 0 : hubp201->hubp_shift = hubp_shift;
143 0 : hubp201->hubp_mask = hubp_mask;
144 0 : hubp201->base.inst = inst;
145 0 : hubp201->base.opp_id = OPP_ID_INVALID;
146 0 : hubp201->base.mpcc_id = 0xf;
147 :
148 0 : return true;
149 : }
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