Line data    Source code

       1             : /*
       2             :  * Copyright 2012-15 Advanced Micro Devices, Inc.
       3             :  *
       4             :  * Permission is hereby granted, free of charge, to any person obtaining a
       5             :  * copy of this software and associated documentation files (the "Software"),
       6             :  * to deal in the Software without restriction, including without limitation
       7             :  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
       8             :  * and/or sell copies of the Software, and to permit persons to whom the
       9             :  * Software is furnished to do so, subject to the following conditions:
      10             :  *
      11             :  * The above copyright notice and this permission notice shall be included in
      12             :  * all copies or substantial portions of the Software.
      13             :  *
      14             :  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
      15             :  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
      16             :  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
      17             :  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
      18             :  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
      19             :  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
      20             :  * OTHER DEALINGS IN THE SOFTWARE.
      21             :  *
      22             :  * Authors: AMD
      23             :  *
      24             :  */
      25             : 
      26             : #include "reg_helper.h"
      27             : #include "dcn201_mpc.h"
      28             : 
      29             : #define REG(reg)\
      30             :         mpc201->mpc_regs->reg
      31             : 
      32             : #define CTX \
      33             :         mpc201->base.ctx
      34             : 
      35             : #define DC_LOGGER \
      36             :         mpc201->base.ctx->logger
      37             : 
      38             : #undef FN
      39             : #define FN(reg_name, field_name) \
      40             :         mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
      41             : 
      42           0 : static void mpc201_set_out_rate_control(
      43             :         struct mpc *mpc,
      44             :         int opp_id,
      45             :         bool enable,
      46             :         bool rate_2x_mode,
      47             :         struct mpc_dwb_flow_control *flow_control)
      48             : {
      49           0 :         struct dcn201_mpc *mpc201 = TO_DCN201_MPC(mpc);
      50             : 
      51           0 :         REG_UPDATE_2(MUX[opp_id],
      52             :                         MPC_OUT_RATE_CONTROL_DISABLE, !enable,
      53             :                         MPC_OUT_RATE_CONTROL, rate_2x_mode);
      54             : 
      55           0 :         if (flow_control)
      56           0 :                 REG_UPDATE_3(MUX[opp_id],
      57             :                         MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode,
      58             :                         MPC_OUT_FLOW_CONTROL_COUNT0, flow_control->flow_ctrl_cnt0,
      59             :                         MPC_OUT_FLOW_CONTROL_COUNT1, flow_control->flow_ctrl_cnt1);
      60           0 : }
      61             : 
      62             : static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
      63             : {
      64           0 :         mpcc->mpcc_id = mpcc_inst;
      65           0 :         mpcc->dpp_id = 0xf;
      66           0 :         mpcc->mpcc_bot = NULL;
      67           0 :         mpcc->blnd_cfg.overlap_only = false;
      68           0 :         mpcc->blnd_cfg.global_alpha = 0xff;
      69           0 :         mpcc->blnd_cfg.global_gain = 0xff;
      70           0 :         mpcc->blnd_cfg.background_color_bpc = 4;
      71           0 :         mpcc->blnd_cfg.bottom_gain_mode = 0;
      72           0 :         mpcc->blnd_cfg.top_gain = 0x1f000;
      73           0 :         mpcc->blnd_cfg.bottom_inside_gain = 0x1f000;
      74           0 :         mpcc->blnd_cfg.bottom_outside_gain = 0x1f000;
      75           0 :         mpcc->sm_cfg.enable = false;
      76           0 :         mpcc->shared_bottom = false;
      77             : }
      78             : 
      79             : const struct mpc_funcs dcn201_mpc_funcs = {
      80             :         .read_mpcc_state = mpc1_read_mpcc_state,
      81             :         .insert_plane = mpc1_insert_plane,
      82             :         .remove_mpcc = mpc1_remove_mpcc,
      83             :         .mpc_init = mpc1_mpc_init,
      84             :         .mpc_init_single_inst = mpc1_mpc_init_single_inst,
      85             :         .update_blending = mpc2_update_blending,
      86             :         .cursor_lock = mpc1_cursor_lock,
      87             :         .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
      88             :         .get_mpcc_for_dpp_from_secondary = NULL,
      89             :         .wait_for_idle = mpc2_assert_idle_mpcc,
      90             :         .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
      91             :         .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
      92             :         .set_denorm = mpc2_set_denorm,
      93             :         .set_denorm_clamp = mpc2_set_denorm_clamp,
      94             :         .set_output_csc = mpc2_set_output_csc,
      95             :         .set_ocsc_default = mpc2_set_ocsc_default,
      96             :         .set_output_gamma = mpc2_set_output_gamma,
      97             :         .set_out_rate_control = mpc201_set_out_rate_control,
      98             :         .power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
      99             :         .get_mpc_out_mux = mpc1_get_mpc_out_mux,
     100             :         .set_bg_color = mpc1_set_bg_color,
     101             : };
     102             : 
     103           0 : void dcn201_mpc_construct(struct dcn201_mpc *mpc201,
     104             :         struct dc_context *ctx,
     105             :         const struct dcn201_mpc_registers *mpc_regs,
     106             :         const struct dcn201_mpc_shift *mpc_shift,
     107             :         const struct dcn201_mpc_mask *mpc_mask,
     108             :         int num_mpcc)
     109             : {
     110             :         int i;
     111             : 
     112           0 :         mpc201->base.ctx = ctx;
     113             : 
     114           0 :         mpc201->base.funcs = &dcn201_mpc_funcs;
     115             : 
     116           0 :         mpc201->mpc_regs = mpc_regs;
     117           0 :         mpc201->mpc_shift = mpc_shift;
     118           0 :         mpc201->mpc_mask = mpc_mask;
     119             : 
     120           0 :         mpc201->mpcc_in_use_mask = 0;
     121           0 :         mpc201->num_mpcc = num_mpcc;
     122             : 
     123           0 :         for (i = 0; i < MAX_MPCC; i++)
     124           0 :                 mpc201_init_mpcc(&mpc201->base.mpcc_array[i], i);
     125           0 : }