Line data Source code
1 : /*
2 : * Copyright 2016 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dm_services.h"
27 : #include "dc.h"
28 :
29 : #include "dcn201_init.h"
30 : #include "dml/dcn20/dcn20_fpu.h"
31 : #include "resource.h"
32 : #include "include/irq_service_interface.h"
33 : #include "dcn201_resource.h"
34 :
35 : #include "dcn20/dcn20_resource.h"
36 :
37 : #include "dcn10/dcn10_hubp.h"
38 : #include "dcn10/dcn10_ipp.h"
39 : #include "dcn201_mpc.h"
40 : #include "dcn201_hubp.h"
41 : #include "irq/dcn201/irq_service_dcn201.h"
42 : #include "dcn201/dcn201_dpp.h"
43 : #include "dcn201/dcn201_hubbub.h"
44 : #include "dcn201_dccg.h"
45 : #include "dcn201_optc.h"
46 : #include "dcn201_hwseq.h"
47 : #include "dce110/dce110_hw_sequencer.h"
48 : #include "dcn201_opp.h"
49 : #include "dcn201/dcn201_link_encoder.h"
50 : #include "dcn20/dcn20_stream_encoder.h"
51 : #include "dce/dce_clock_source.h"
52 : #include "dce/dce_audio.h"
53 : #include "dce/dce_hwseq.h"
54 : #include "virtual/virtual_stream_encoder.h"
55 : #include "dce110/dce110_resource.h"
56 : #include "dce/dce_aux.h"
57 : #include "dce/dce_i2c.h"
58 : #include "dcn201_hubbub.h"
59 : #include "dcn10/dcn10_resource.h"
60 :
61 : #include "cyan_skillfish_ip_offset.h"
62 :
63 : #include "dcn/dcn_2_0_3_offset.h"
64 : #include "dcn/dcn_2_0_3_sh_mask.h"
65 : #include "dpcs/dpcs_2_0_3_offset.h"
66 : #include "dpcs/dpcs_2_0_3_sh_mask.h"
67 :
68 : #include "mmhub/mmhub_2_0_0_offset.h"
69 : #include "mmhub/mmhub_2_0_0_sh_mask.h"
70 : #include "nbio/nbio_7_4_offset.h"
71 :
72 : #include "reg_helper.h"
73 :
74 : #define MIN_DISP_CLK_KHZ 100000
75 : #define MIN_DPP_CLK_KHZ 100000
76 :
77 : struct _vcs_dpi_ip_params_st dcn201_ip = {
78 : .gpuvm_enable = 0,
79 : .hostvm_enable = 0,
80 : .gpuvm_max_page_table_levels = 4,
81 : .hostvm_max_page_table_levels = 4,
82 : .hostvm_cached_page_table_levels = 0,
83 : .pte_group_size_bytes = 2048,
84 : .rob_buffer_size_kbytes = 168,
85 : .det_buffer_size_kbytes = 164,
86 : .dpte_buffer_size_in_pte_reqs_luma = 84,
87 : .pde_proc_buffer_size_64k_reqs = 48,
88 : .dpp_output_buffer_pixels = 2560,
89 : .opp_output_buffer_lines = 1,
90 : .pixel_chunk_size_kbytes = 8,
91 : .pte_chunk_size_kbytes = 2,
92 : .meta_chunk_size_kbytes = 2,
93 : .writeback_chunk_size_kbytes = 2,
94 : .line_buffer_size_bits = 789504,
95 : .is_line_buffer_bpp_fixed = 0,
96 : .line_buffer_fixed_bpp = 0,
97 : .dcc_supported = true,
98 : .max_line_buffer_lines = 12,
99 : .writeback_luma_buffer_size_kbytes = 12,
100 : .writeback_chroma_buffer_size_kbytes = 8,
101 : .writeback_chroma_line_buffer_width_pixels = 4,
102 : .writeback_max_hscl_ratio = 1,
103 : .writeback_max_vscl_ratio = 1,
104 : .writeback_min_hscl_ratio = 1,
105 : .writeback_min_vscl_ratio = 1,
106 : .writeback_max_hscl_taps = 12,
107 : .writeback_max_vscl_taps = 12,
108 : .writeback_line_buffer_luma_buffer_size = 0,
109 : .writeback_line_buffer_chroma_buffer_size = 9600,
110 : .cursor_buffer_size = 8,
111 : .cursor_chunk_size = 2,
112 : .max_num_otg = 2,
113 : .max_num_dpp = 4,
114 : .max_num_wb = 0,
115 : .max_dchub_pscl_bw_pix_per_clk = 4,
116 : .max_pscl_lb_bw_pix_per_clk = 2,
117 : .max_lb_vscl_bw_pix_per_clk = 4,
118 : .max_vscl_hscl_bw_pix_per_clk = 4,
119 : .max_hscl_ratio = 8,
120 : .max_vscl_ratio = 8,
121 : .hscl_mults = 4,
122 : .vscl_mults = 4,
123 : .max_hscl_taps = 8,
124 : .max_vscl_taps = 8,
125 : .dispclk_ramp_margin_percent = 1,
126 : .underscan_factor = 1.10,
127 : .min_vblank_lines = 30,
128 : .dppclk_delay_subtotal = 77,
129 : .dppclk_delay_scl_lb_only = 16,
130 : .dppclk_delay_scl = 50,
131 : .dppclk_delay_cnvc_formatter = 8,
132 : .dppclk_delay_cnvc_cursor = 6,
133 : .dispclk_delay_subtotal = 87,
134 : .dcfclk_cstate_latency = 10,
135 : .max_inter_dcn_tile_repeaters = 8,
136 : .number_of_cursors = 1,
137 : };
138 :
139 : struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
140 : .clock_limits = {
141 : {
142 : .state = 0,
143 : .dscclk_mhz = 400.0,
144 : .dcfclk_mhz = 1000.0,
145 : .fabricclk_mhz = 200.0,
146 : .dispclk_mhz = 300.0,
147 : .dppclk_mhz = 300.0,
148 : .phyclk_mhz = 810.0,
149 : .socclk_mhz = 1254.0,
150 : .dram_speed_mts = 2000.0,
151 : },
152 : {
153 : .state = 1,
154 : .dscclk_mhz = 400.0,
155 : .dcfclk_mhz = 1000.0,
156 : .fabricclk_mhz = 250.0,
157 : .dispclk_mhz = 1200.0,
158 : .dppclk_mhz = 1200.0,
159 : .phyclk_mhz = 810.0,
160 : .socclk_mhz = 1254.0,
161 : .dram_speed_mts = 3600.0,
162 : },
163 : {
164 : .state = 2,
165 : .dscclk_mhz = 400.0,
166 : .dcfclk_mhz = 1000.0,
167 : .fabricclk_mhz = 750.0,
168 : .dispclk_mhz = 1200.0,
169 : .dppclk_mhz = 1200.0,
170 : .phyclk_mhz = 810.0,
171 : .socclk_mhz = 1254.0,
172 : .dram_speed_mts = 6800.0,
173 : },
174 : {
175 : .state = 3,
176 : .dscclk_mhz = 400.0,
177 : .dcfclk_mhz = 1000.0,
178 : .fabricclk_mhz = 250.0,
179 : .dispclk_mhz = 1200.0,
180 : .dppclk_mhz = 1200.0,
181 : .phyclk_mhz = 810.0,
182 : .socclk_mhz = 1254.0,
183 : .dram_speed_mts = 14000.0,
184 : },
185 : {
186 : .state = 4,
187 : .dscclk_mhz = 400.0,
188 : .dcfclk_mhz = 1000.0,
189 : .fabricclk_mhz = 750.0,
190 : .dispclk_mhz = 1200.0,
191 : .dppclk_mhz = 1200.0,
192 : .phyclk_mhz = 810.0,
193 : .socclk_mhz = 1254.0,
194 : .dram_speed_mts = 14000.0,
195 : }
196 : },
197 : .num_states = 4,
198 : .sr_exit_time_us = 9.0,
199 : .sr_enter_plus_exit_time_us = 11.0,
200 : .urgent_latency_us = 4.0,
201 : .urgent_latency_pixel_data_only_us = 4.0,
202 : .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
203 : .urgent_latency_vm_data_only_us = 4.0,
204 : .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
205 : .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
206 : .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
207 : .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
208 : .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
209 : .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
210 : .max_avg_sdp_bw_use_normal_percent = 80.0,
211 : .max_avg_dram_bw_use_normal_percent = 69.0,
212 : .writeback_latency_us = 12.0,
213 : .ideal_dram_bw_after_urgent_percent = 80.0,
214 : .max_request_size_bytes = 256,
215 : .dram_channel_width_bytes = 2,
216 : .fabric_datapath_to_dcn_data_return_bytes = 64,
217 : .dcn_downspread_percent = 0.3,
218 : .downspread_percent = 0.3,
219 : .dram_page_open_time_ns = 50.0,
220 : .dram_rw_turnaround_time_ns = 17.5,
221 : .dram_return_buffer_per_channel_bytes = 8192,
222 : .round_trip_ping_latency_dcfclk_cycles = 128,
223 : .urgent_out_of_order_return_per_channel_bytes = 256,
224 : .channel_interleave_bytes = 256,
225 : .num_banks = 8,
226 : .num_chans = 16,
227 : .vmm_page_size_bytes = 4096,
228 : .dram_clock_change_latency_us = 250.0,
229 : .writeback_dram_clock_change_latency_us = 23.0,
230 : .return_bus_width_bytes = 64,
231 : .dispclk_dppclk_vco_speed_mhz = 3000,
232 : .use_urgent_burst_bw = 0,
233 : };
234 :
235 : enum dcn20_clk_src_array_id {
236 : DCN20_CLK_SRC_PLL0,
237 : DCN20_CLK_SRC_PLL1,
238 : DCN20_CLK_SRC_TOTAL_DCN201
239 : };
240 :
241 : /* begin *********************
242 : * macros to expend register list macro defined in HW object header file */
243 :
244 : /* DCN */
245 :
246 : #undef BASE_INNER
247 : #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
248 :
249 : #define BASE(seg) BASE_INNER(seg)
250 :
251 : #define SR(reg_name)\
252 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 : mm ## reg_name
254 :
255 : #define SRI(reg_name, block, id)\
256 : .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 : mm ## block ## id ## _ ## reg_name
258 :
259 : #define SRIR(var_name, reg_name, block, id)\
260 : .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 : mm ## block ## id ## _ ## reg_name
262 :
263 : #define SRII(reg_name, block, id)\
264 : .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
265 : mm ## block ## id ## _ ## reg_name
266 :
267 : #define SRI_IX(reg_name, block, id)\
268 : .reg_name = ix ## block ## id ## _ ## reg_name
269 :
270 : #define DCCG_SRII(reg_name, block, id)\
271 : .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
272 : mm ## block ## id ## _ ## reg_name
273 :
274 : #define VUPDATE_SRII(reg_name, block, id)\
275 : .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
276 : mm ## reg_name ## _ ## block ## id
277 :
278 : /* NBIO */
279 : #define NBIO_BASE_INNER(seg) \
280 : NBIO_BASE__INST0_SEG ## seg
281 :
282 : #define NBIO_BASE(seg) \
283 : NBIO_BASE_INNER(seg)
284 :
285 : #define NBIO_SR(reg_name)\
286 : .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
287 : mm ## reg_name
288 :
289 : /* MMHUB */
290 : #define MMHUB_BASE_INNER(seg) \
291 : MMHUB_BASE__INST0_SEG ## seg
292 :
293 : #define MMHUB_BASE(seg) \
294 : MMHUB_BASE_INNER(seg)
295 :
296 : #define MMHUB_SR(reg_name)\
297 : .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
298 : mmMM ## reg_name
299 :
300 : static const struct bios_registers bios_regs = {
301 : NBIO_SR(BIOS_SCRATCH_3),
302 : NBIO_SR(BIOS_SCRATCH_6)
303 : };
304 :
305 : #define clk_src_regs(index, pllid)\
306 : [index] = {\
307 : CS_COMMON_REG_LIST_DCN201(index, pllid),\
308 : }
309 :
310 : static const struct dce110_clk_src_regs clk_src_regs[] = {
311 : clk_src_regs(0, A),
312 : clk_src_regs(1, B)
313 : };
314 :
315 : static const struct dce110_clk_src_shift cs_shift = {
316 : CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
317 : };
318 :
319 : static const struct dce110_clk_src_mask cs_mask = {
320 : CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
321 : };
322 :
323 : #define audio_regs(id)\
324 : [id] = {\
325 : AUD_COMMON_REG_LIST(id)\
326 : }
327 :
328 : static const struct dce_audio_registers audio_regs[] = {
329 : audio_regs(0),
330 : audio_regs(1),
331 : };
332 :
333 : #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
334 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
335 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
336 : AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
337 :
338 : static const struct dce_audio_shift audio_shift = {
339 : DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
340 : };
341 :
342 : static const struct dce_audio_mask audio_mask = {
343 : DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
344 : };
345 :
346 : #define stream_enc_regs(id)\
347 : [id] = {\
348 : SE_DCN2_REG_LIST(id)\
349 : }
350 :
351 : static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
352 : stream_enc_regs(0),
353 : stream_enc_regs(1)
354 : };
355 :
356 : static const struct dcn10_stream_encoder_shift se_shift = {
357 : SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
358 : };
359 :
360 : static const struct dcn10_stream_encoder_mask se_mask = {
361 : SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
362 : };
363 :
364 : static const struct dce110_aux_registers_shift aux_shift = {
365 : DCN_AUX_MASK_SH_LIST(__SHIFT)
366 : };
367 :
368 : static const struct dce110_aux_registers_mask aux_mask = {
369 : DCN_AUX_MASK_SH_LIST(_MASK)
370 : };
371 :
372 : #define aux_regs(id)\
373 : [id] = {\
374 : DCN2_AUX_REG_LIST(id)\
375 : }
376 :
377 : static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
378 : aux_regs(0),
379 : aux_regs(1),
380 : };
381 :
382 : #define hpd_regs(id)\
383 : [id] = {\
384 : HPD_REG_LIST(id)\
385 : }
386 :
387 : static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
388 : hpd_regs(0),
389 : hpd_regs(1),
390 : };
391 :
392 : #define link_regs(id, phyid)\
393 : [id] = {\
394 : LE_DCN_COMMON_REG_LIST(id), \
395 : UNIPHY_DCN2_REG_LIST(phyid) \
396 : }
397 :
398 : static const struct dcn10_link_enc_registers link_enc_regs[] = {
399 : link_regs(0, A),
400 : link_regs(1, B),
401 : };
402 :
403 : #define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh)\
404 : LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
405 :
406 : static const struct dcn10_link_enc_shift le_shift = {
407 : LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
408 : };
409 :
410 : static const struct dcn10_link_enc_mask le_mask = {
411 : LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
412 : };
413 :
414 : #define ipp_regs(id)\
415 : [id] = {\
416 : IPP_REG_LIST_DCN201(id),\
417 : }
418 :
419 : static const struct dcn10_ipp_registers ipp_regs[] = {
420 : ipp_regs(0),
421 : ipp_regs(1),
422 : ipp_regs(2),
423 : ipp_regs(3),
424 : };
425 :
426 : static const struct dcn10_ipp_shift ipp_shift = {
427 : IPP_MASK_SH_LIST_DCN201(__SHIFT)
428 : };
429 :
430 : static const struct dcn10_ipp_mask ipp_mask = {
431 : IPP_MASK_SH_LIST_DCN201(_MASK)
432 : };
433 :
434 : #define opp_regs(id)\
435 : [id] = {\
436 : OPP_REG_LIST_DCN201(id),\
437 : }
438 :
439 : static const struct dcn201_opp_registers opp_regs[] = {
440 : opp_regs(0),
441 : opp_regs(1),
442 : };
443 :
444 : static const struct dcn201_opp_shift opp_shift = {
445 : OPP_MASK_SH_LIST_DCN201(__SHIFT)
446 : };
447 :
448 : static const struct dcn201_opp_mask opp_mask = {
449 : OPP_MASK_SH_LIST_DCN201(_MASK)
450 : };
451 :
452 : #define aux_engine_regs(id)\
453 : [id] = {\
454 : AUX_COMMON_REG_LIST0(id), \
455 : .AUX_RESET_MASK = 0 \
456 : }
457 :
458 : static const struct dce110_aux_registers aux_engine_regs[] = {
459 : aux_engine_regs(0),
460 : aux_engine_regs(1)
461 : };
462 :
463 : #define tf_regs(id)\
464 : [id] = {\
465 : TF_REG_LIST_DCN201(id),\
466 : }
467 :
468 : static const struct dcn201_dpp_registers tf_regs[] = {
469 : tf_regs(0),
470 : tf_regs(1),
471 : tf_regs(2),
472 : tf_regs(3),
473 : };
474 :
475 : static const struct dcn201_dpp_shift tf_shift = {
476 : TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
477 : };
478 :
479 : static const struct dcn201_dpp_mask tf_mask = {
480 : TF_REG_LIST_SH_MASK_DCN201(_MASK)
481 : };
482 :
483 : static const struct dcn201_mpc_registers mpc_regs = {
484 : MPC_REG_LIST_DCN201(0),
485 : MPC_REG_LIST_DCN201(1),
486 : MPC_REG_LIST_DCN201(2),
487 : MPC_REG_LIST_DCN201(3),
488 : MPC_REG_LIST_DCN201(4),
489 : MPC_OUT_MUX_REG_LIST_DCN201(0),
490 : MPC_OUT_MUX_REG_LIST_DCN201(1),
491 : };
492 :
493 : static const struct dcn201_mpc_shift mpc_shift = {
494 : MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
495 : };
496 :
497 : static const struct dcn201_mpc_mask mpc_mask = {
498 : MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)
499 : };
500 :
501 : #define tg_regs_dcn201(id)\
502 : [id] = {TG_COMMON_REG_LIST_DCN201(id)}
503 :
504 : static const struct dcn_optc_registers tg_regs[] = {
505 : tg_regs_dcn201(0),
506 : tg_regs_dcn201(1)
507 : };
508 :
509 : static const struct dcn_optc_shift tg_shift = {
510 : TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
511 : };
512 :
513 : static const struct dcn_optc_mask tg_mask = {
514 : TG_COMMON_MASK_SH_LIST_DCN201(_MASK)
515 : };
516 :
517 : #define hubp_regsDCN201(id)\
518 : [id] = {\
519 : HUBP_REG_LIST_DCN201(id)\
520 : }
521 :
522 : static const struct dcn201_hubp_registers hubp_regs[] = {
523 : hubp_regsDCN201(0),
524 : hubp_regsDCN201(1),
525 : hubp_regsDCN201(2),
526 : hubp_regsDCN201(3)
527 : };
528 :
529 : static const struct dcn201_hubp_shift hubp_shift = {
530 : HUBP_MASK_SH_LIST_DCN201(__SHIFT)
531 : };
532 :
533 : static const struct dcn201_hubp_mask hubp_mask = {
534 : HUBP_MASK_SH_LIST_DCN201(_MASK)
535 : };
536 :
537 : static const struct dcn_hubbub_registers hubbub_reg = {
538 : HUBBUB_REG_LIST_DCN201(0)
539 : };
540 :
541 : static const struct dcn_hubbub_shift hubbub_shift = {
542 : HUBBUB_MASK_SH_LIST_DCN201(__SHIFT)
543 : };
544 :
545 : static const struct dcn_hubbub_mask hubbub_mask = {
546 : HUBBUB_MASK_SH_LIST_DCN201(_MASK)
547 : };
548 :
549 :
550 : static const struct dccg_registers dccg_regs = {
551 : DCCG_COMMON_REG_LIST_DCN_BASE()
552 : };
553 :
554 : static const struct dccg_shift dccg_shift = {
555 : DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT)
556 : };
557 :
558 : static const struct dccg_mask dccg_mask = {
559 : DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)
560 : };
561 :
562 : static const struct resource_caps res_cap_dnc201 = {
563 : .num_timing_generator = 2,
564 : .num_opp = 2,
565 : .num_video_plane = 4,
566 : .num_audio = 2,
567 : .num_stream_encoder = 2,
568 : .num_pll = 2,
569 : .num_ddc = 2,
570 : };
571 :
572 : static const struct dc_plane_cap plane_cap = {
573 : .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
574 : .blends_with_above = true,
575 : .blends_with_below = true,
576 : .per_pixel_alpha = true,
577 :
578 : .pixel_format_support = {
579 : .argb8888 = true,
580 : .nv12 = false,
581 : .fp16 = true,
582 : .p010 = false,
583 : },
584 :
585 : .max_upscale_factor = {
586 : .argb8888 = 16000,
587 : .nv12 = 16000,
588 : .fp16 = 1
589 : },
590 :
591 : .max_downscale_factor = {
592 : .argb8888 = 250,
593 : .nv12 = 250,
594 : .fp16 = 250
595 : },
596 : 64,
597 : 64
598 : };
599 :
600 : static const struct dc_debug_options debug_defaults_drv = {
601 : .disable_dmcu = true,
602 : .force_abm_enable = false,
603 : .timing_trace = false,
604 : .clock_trace = true,
605 : .disable_pplib_clock_request = true,
606 : .pipe_split_policy = MPC_SPLIT_DYNAMIC,
607 : .force_single_disp_pipe_split = false,
608 : .disable_dcc = DCC_ENABLE,
609 : .vsr_support = true,
610 : .performance_trace = false,
611 : .az_endpoint_mute_only = true,
612 : .max_downscale_src_width = 3840,
613 : .disable_pplib_wm_range = true,
614 : .scl_reset_length10 = true,
615 : .sanity_checks = false,
616 : .underflow_assert_delay_us = 0xFFFFFFFF,
617 : .enable_tri_buf = false,
618 : };
619 :
620 : static void dcn201_dpp_destroy(struct dpp **dpp)
621 : {
622 0 : kfree(TO_DCN201_DPP(*dpp));
623 0 : *dpp = NULL;
624 : }
625 :
626 0 : static struct dpp *dcn201_dpp_create(
627 : struct dc_context *ctx,
628 : uint32_t inst)
629 : {
630 0 : struct dcn201_dpp *dpp =
631 : kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC);
632 :
633 0 : if (!dpp)
634 : return NULL;
635 :
636 0 : if (dpp201_construct(dpp, ctx, inst,
637 : &tf_regs[inst], &tf_shift, &tf_mask))
638 0 : return &dpp->base;
639 :
640 0 : kfree(dpp);
641 0 : return NULL;
642 : }
643 :
644 0 : static struct input_pixel_processor *dcn201_ipp_create(
645 : struct dc_context *ctx, uint32_t inst)
646 : {
647 0 : struct dcn10_ipp *ipp =
648 : kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
649 :
650 0 : if (!ipp) {
651 : return NULL;
652 : }
653 :
654 0 : dcn20_ipp_construct(ipp, ctx, inst,
655 : &ipp_regs[inst], &ipp_shift, &ipp_mask);
656 0 : return &ipp->base;
657 : }
658 :
659 :
660 0 : static struct output_pixel_processor *dcn201_opp_create(
661 : struct dc_context *ctx, uint32_t inst)
662 : {
663 0 : struct dcn201_opp *opp =
664 : kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC);
665 :
666 0 : if (!opp) {
667 : return NULL;
668 : }
669 :
670 0 : dcn201_opp_construct(opp, ctx, inst,
671 : &opp_regs[inst], &opp_shift, &opp_mask);
672 0 : return &opp->base;
673 : }
674 :
675 0 : static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
676 : uint32_t inst)
677 : {
678 0 : struct aux_engine_dce110 *aux_engine =
679 : kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
680 :
681 0 : if (!aux_engine)
682 : return NULL;
683 :
684 0 : dce110_aux_engine_construct(aux_engine, ctx, inst,
685 : SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
686 : &aux_engine_regs[inst],
687 : &aux_mask,
688 : &aux_shift,
689 0 : ctx->dc->caps.extended_aux_timeout_support);
690 :
691 0 : return &aux_engine->base;
692 : }
693 : #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
694 :
695 : static const struct dce_i2c_registers i2c_hw_regs[] = {
696 : i2c_inst_regs(1),
697 : i2c_inst_regs(2),
698 : };
699 :
700 : static const struct dce_i2c_shift i2c_shifts = {
701 : I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
702 : };
703 :
704 : static const struct dce_i2c_mask i2c_masks = {
705 : I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
706 : };
707 :
708 0 : static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
709 : uint32_t inst)
710 : {
711 0 : struct dce_i2c_hw *dce_i2c_hw =
712 : kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
713 :
714 0 : if (!dce_i2c_hw)
715 : return NULL;
716 :
717 0 : dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
718 : &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
719 :
720 0 : return dce_i2c_hw;
721 : }
722 :
723 0 : static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
724 : {
725 0 : struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),
726 : GFP_ATOMIC);
727 :
728 0 : if (!mpc201)
729 : return NULL;
730 :
731 0 : dcn201_mpc_construct(mpc201, ctx,
732 : &mpc_regs,
733 : &mpc_shift,
734 : &mpc_mask,
735 : num_mpcc);
736 :
737 0 : return &mpc201->base;
738 : }
739 :
740 0 : static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
741 : {
742 0 : struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
743 : GFP_ATOMIC);
744 :
745 0 : if (!hubbub)
746 : return NULL;
747 :
748 0 : hubbub201_construct(hubbub, ctx,
749 : &hubbub_reg,
750 : &hubbub_shift,
751 : &hubbub_mask);
752 :
753 0 : return &hubbub->base;
754 : }
755 :
756 0 : static struct timing_generator *dcn201_timing_generator_create(
757 : struct dc_context *ctx,
758 : uint32_t instance)
759 : {
760 0 : struct optc *tgn10 =
761 : kzalloc(sizeof(struct optc), GFP_ATOMIC);
762 :
763 0 : if (!tgn10)
764 : return NULL;
765 :
766 0 : tgn10->base.inst = instance;
767 0 : tgn10->base.ctx = ctx;
768 :
769 0 : tgn10->tg_regs = &tg_regs[instance];
770 0 : tgn10->tg_shift = &tg_shift;
771 0 : tgn10->tg_mask = &tg_mask;
772 :
773 0 : dcn201_timing_generator_init(tgn10);
774 :
775 0 : return &tgn10->base;
776 : }
777 :
778 : static const struct encoder_feature_support link_enc_feature = {
779 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
780 : .max_hdmi_pixel_clock = 600000,
781 : .hdmi_ycbcr420_supported = true,
782 : .dp_ycbcr420_supported = true,
783 : .fec_supported = true,
784 : .flags.bits.IS_HBR2_CAPABLE = true,
785 : .flags.bits.IS_HBR3_CAPABLE = true,
786 : .flags.bits.IS_TPS3_CAPABLE = true,
787 : .flags.bits.IS_TPS4_CAPABLE = true
788 : };
789 :
790 0 : static struct link_encoder *dcn201_link_encoder_create(
791 : struct dc_context *ctx,
792 : const struct encoder_init_data *enc_init_data)
793 : {
794 0 : struct dcn20_link_encoder *enc20 =
795 : kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
796 0 : struct dcn10_link_encoder *enc10 = &enc20->enc10;
797 :
798 0 : if (!enc20)
799 : return NULL;
800 :
801 0 : dcn201_link_encoder_construct(enc20,
802 : enc_init_data,
803 : &link_enc_feature,
804 0 : &link_enc_regs[enc_init_data->transmitter],
805 0 : &link_enc_aux_regs[enc_init_data->channel - 1],
806 0 : &link_enc_hpd_regs[enc_init_data->hpd_source],
807 : &le_shift,
808 : &le_mask);
809 :
810 0 : return &enc10->base;
811 : }
812 :
813 0 : static struct clock_source *dcn201_clock_source_create(
814 : struct dc_context *ctx,
815 : struct dc_bios *bios,
816 : enum clock_source_id id,
817 : const struct dce110_clk_src_regs *regs,
818 : bool dp_clk_src)
819 : {
820 0 : struct dce110_clk_src *clk_src =
821 : kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
822 :
823 0 : if (!clk_src)
824 : return NULL;
825 :
826 0 : if (dce112_clk_src_construct(clk_src, ctx, bios, id,
827 : regs, &cs_shift, &cs_mask)) {
828 0 : clk_src->base.dp_clk_src = dp_clk_src;
829 0 : return &clk_src->base;
830 : }
831 0 : kfree(clk_src);
832 0 : return NULL;
833 : }
834 :
835 0 : static void read_dce_straps(
836 : struct dc_context *ctx,
837 : struct resource_straps *straps)
838 : {
839 0 : generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
840 :
841 : FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
842 0 : }
843 :
844 0 : static struct audio *dcn201_create_audio(
845 : struct dc_context *ctx, unsigned int inst)
846 : {
847 0 : return dce_audio_create(ctx, inst,
848 : &audio_regs[inst], &audio_shift, &audio_mask);
849 : }
850 :
851 0 : static struct stream_encoder *dcn201_stream_encoder_create(
852 : enum engine_id eng_id,
853 : struct dc_context *ctx)
854 : {
855 0 : struct dcn10_stream_encoder *enc1 =
856 : kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC);
857 :
858 0 : if (!enc1)
859 : return NULL;
860 :
861 0 : dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
862 : &stream_enc_regs[eng_id],
863 : &se_shift, &se_mask);
864 :
865 0 : return &enc1->base;
866 : }
867 :
868 : static const struct dce_hwseq_registers hwseq_reg = {
869 : HWSEQ_DCN201_REG_LIST()
870 : };
871 :
872 : static const struct dce_hwseq_shift hwseq_shift = {
873 : HWSEQ_DCN201_MASK_SH_LIST(__SHIFT)
874 : };
875 :
876 : static const struct dce_hwseq_mask hwseq_mask = {
877 : HWSEQ_DCN201_MASK_SH_LIST(_MASK)
878 : };
879 :
880 0 : static struct dce_hwseq *dcn201_hwseq_create(
881 : struct dc_context *ctx)
882 : {
883 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC);
884 :
885 0 : if (hws) {
886 0 : hws->ctx = ctx;
887 0 : hws->regs = &hwseq_reg;
888 0 : hws->shifts = &hwseq_shift;
889 0 : hws->masks = &hwseq_mask;
890 : }
891 0 : return hws;
892 : }
893 :
894 : static const struct resource_create_funcs res_create_funcs = {
895 : .read_dce_straps = read_dce_straps,
896 : .create_audio = dcn201_create_audio,
897 : .create_stream_encoder = dcn201_stream_encoder_create,
898 : .create_hwseq = dcn201_hwseq_create,
899 : };
900 :
901 : static const struct resource_create_funcs res_create_maximus_funcs = {
902 : .read_dce_straps = NULL,
903 : .create_audio = NULL,
904 : .create_stream_encoder = NULL,
905 : .create_hwseq = dcn201_hwseq_create,
906 : };
907 :
908 : static void dcn201_clock_source_destroy(struct clock_source **clk_src)
909 : {
910 0 : kfree(TO_DCE110_CLK_SRC(*clk_src));
911 0 : *clk_src = NULL;
912 : }
913 :
914 0 : static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
915 : {
916 : unsigned int i;
917 :
918 0 : for (i = 0; i < pool->base.stream_enc_count; i++) {
919 0 : if (pool->base.stream_enc[i] != NULL) {
920 0 : kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
921 0 : pool->base.stream_enc[i] = NULL;
922 : }
923 : }
924 :
925 :
926 0 : if (pool->base.mpc != NULL) {
927 0 : kfree(TO_DCN201_MPC(pool->base.mpc));
928 0 : pool->base.mpc = NULL;
929 : }
930 :
931 0 : if (pool->base.hubbub != NULL) {
932 0 : kfree(pool->base.hubbub);
933 0 : pool->base.hubbub = NULL;
934 : }
935 :
936 0 : for (i = 0; i < pool->base.pipe_count; i++) {
937 0 : if (pool->base.dpps[i] != NULL)
938 0 : dcn201_dpp_destroy(&pool->base.dpps[i]);
939 :
940 0 : if (pool->base.ipps[i] != NULL)
941 0 : pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
942 :
943 0 : if (pool->base.hubps[i] != NULL) {
944 0 : kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
945 0 : pool->base.hubps[i] = NULL;
946 : }
947 :
948 0 : if (pool->base.irqs != NULL) {
949 0 : dal_irq_service_destroy(&pool->base.irqs);
950 : }
951 : }
952 :
953 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
954 0 : if (pool->base.opps[i] != NULL)
955 0 : pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
956 : }
957 :
958 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
959 0 : if (pool->base.timing_generators[i] != NULL) {
960 0 : kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
961 0 : pool->base.timing_generators[i] = NULL;
962 : }
963 : }
964 0 : for (i = 0; i < pool->base.audio_count; i++) {
965 0 : if (pool->base.audios[i])
966 0 : dce_aud_destroy(&pool->base.audios[i]);
967 : }
968 :
969 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
970 0 : if (pool->base.clock_sources[i] != NULL) {
971 0 : dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
972 : pool->base.clock_sources[i] = NULL;
973 : }
974 : }
975 :
976 0 : if (pool->base.dp_clock_source != NULL) {
977 0 : dcn201_clock_source_destroy(&pool->base.dp_clock_source);
978 : pool->base.dp_clock_source = NULL;
979 : }
980 :
981 0 : if (pool->base.dccg != NULL)
982 0 : dcn_dccg_destroy(&pool->base.dccg);
983 0 : }
984 :
985 0 : static struct hubp *dcn201_hubp_create(
986 : struct dc_context *ctx,
987 : uint32_t inst)
988 : {
989 0 : struct dcn201_hubp *hubp201 =
990 : kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC);
991 :
992 0 : if (!hubp201)
993 : return NULL;
994 :
995 0 : if (dcn201_hubp_construct(hubp201, ctx, inst,
996 : &hubp_regs[inst], &hubp_shift, &hubp_mask))
997 0 : return &hubp201->base;
998 :
999 0 : kfree(hubp201);
1000 0 : return NULL;
1001 : }
1002 :
1003 0 : static struct pipe_ctx *dcn201_acquire_idle_pipe_for_layer(
1004 : struct dc_state *context,
1005 : const struct resource_pool *pool,
1006 : struct dc_stream_state *stream)
1007 : {
1008 0 : struct resource_context *res_ctx = &context->res_ctx;
1009 0 : struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1010 0 : struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1011 :
1012 0 : if (!head_pipe)
1013 0 : ASSERT(0);
1014 :
1015 0 : if (!idle_pipe)
1016 : return NULL;
1017 :
1018 0 : idle_pipe->stream = head_pipe->stream;
1019 0 : idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1020 0 : idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1021 :
1022 0 : idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1023 0 : idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1024 0 : idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1025 0 : idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1026 :
1027 0 : return idle_pipe;
1028 : }
1029 :
1030 0 : static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1031 : const struct dc_dcc_surface_param *input,
1032 : struct dc_surface_dcc_cap *output)
1033 : {
1034 0 : return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1035 : dc->res_pool->hubbub,
1036 : input,
1037 : output);
1038 : }
1039 :
1040 0 : static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1041 : struct resource_context *res_ctx,
1042 : display_e2e_pipe_params_st *pipes)
1043 : {
1044 0 : DC_FP_START();
1045 0 : dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1046 0 : DC_FP_END();
1047 0 : }
1048 :
1049 0 : static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1050 : {
1051 0 : struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);
1052 :
1053 0 : dcn201_resource_destruct(dcn201_pool);
1054 0 : kfree(dcn201_pool);
1055 0 : *pool = NULL;
1056 0 : }
1057 :
1058 0 : static void dcn201_link_init(struct dc_link *link)
1059 : {
1060 0 : if (link->ctx->dc_bios->integrated_info)
1061 0 : link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1062 0 : }
1063 :
1064 : static struct dc_cap_funcs cap_funcs = {
1065 : .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1066 : };
1067 :
1068 : static struct resource_funcs dcn201_res_pool_funcs = {
1069 : .link_init = dcn201_link_init,
1070 : .destroy = dcn201_destroy_resource_pool,
1071 : .link_enc_create = dcn201_link_encoder_create,
1072 : .panel_cntl_create = NULL,
1073 : .validate_bandwidth = dcn20_validate_bandwidth,
1074 : .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1075 : .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1076 : .add_dsc_to_stream_resource = NULL,
1077 : .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1078 : .acquire_idle_pipe_for_layer = dcn201_acquire_idle_pipe_for_layer,
1079 : .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1080 : .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1081 : .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1082 : .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1083 : };
1084 :
1085 0 : static bool dcn201_resource_construct(
1086 : uint8_t num_virtual_links,
1087 : struct dc *dc,
1088 : struct dcn201_resource_pool *pool)
1089 : {
1090 : int i;
1091 0 : struct dc_context *ctx = dc->ctx;
1092 :
1093 0 : ctx->dc_bios->regs = &bios_regs;
1094 :
1095 0 : pool->base.res_cap = &res_cap_dnc201;
1096 0 : pool->base.funcs = &dcn201_res_pool_funcs;
1097 :
1098 : /*************************************************
1099 : * Resource + asic cap harcoding *
1100 : *************************************************/
1101 0 : pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1102 :
1103 0 : pool->base.pipe_count = 4;
1104 0 : pool->base.mpcc_count = 5;
1105 0 : dc->caps.max_downscale_ratio = 200;
1106 0 : dc->caps.i2c_speed_in_khz = 100;
1107 0 : dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1108 0 : dc->caps.max_cursor_size = 256;
1109 0 : dc->caps.min_horizontal_blanking_period = 80;
1110 0 : dc->caps.dmdata_alloc_size = 2048;
1111 :
1112 0 : dc->caps.max_slave_planes = 1;
1113 0 : dc->caps.max_slave_yuv_planes = 1;
1114 0 : dc->caps.max_slave_rgb_planes = 1;
1115 0 : dc->caps.post_blend_color_processing = true;
1116 0 : dc->caps.force_dp_tps4_for_cp2520 = true;
1117 0 : dc->caps.extended_aux_timeout_support = true;
1118 :
1119 : /* Color pipeline capabilities */
1120 0 : dc->caps.color.dpp.dcn_arch = 1;
1121 0 : dc->caps.color.dpp.input_lut_shared = 0;
1122 0 : dc->caps.color.dpp.icsc = 1;
1123 0 : dc->caps.color.dpp.dgam_ram = 1;
1124 0 : dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1125 0 : dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1126 0 : dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1127 0 : dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1128 0 : dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1129 0 : dc->caps.color.dpp.post_csc = 0;
1130 0 : dc->caps.color.dpp.gamma_corr = 0;
1131 0 : dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1132 :
1133 0 : dc->caps.color.dpp.hw_3d_lut = 1;
1134 0 : dc->caps.color.dpp.ogam_ram = 1;
1135 : // no OGAM ROM on DCN2
1136 0 : dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1137 0 : dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1138 0 : dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1139 0 : dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1140 0 : dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1141 0 : dc->caps.color.dpp.ocsc = 0;
1142 :
1143 0 : dc->caps.color.mpc.gamut_remap = 0;
1144 0 : dc->caps.color.mpc.num_3dluts = 0;
1145 0 : dc->caps.color.mpc.shared_3d_lut = 0;
1146 0 : dc->caps.color.mpc.ogam_ram = 1;
1147 0 : dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1148 0 : dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1149 0 : dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1150 0 : dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1151 0 : dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1152 0 : dc->caps.color.mpc.ocsc = 1;
1153 :
1154 0 : dc->debug = debug_defaults_drv;
1155 :
1156 : /*a0 only, remove later*/
1157 0 : dc->work_arounds.no_connect_phy_config = true;
1158 0 : dc->work_arounds.dedcn20_305_wa = true;
1159 : /*************************************************
1160 : * Create resources *
1161 : *************************************************/
1162 :
1163 0 : pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1164 0 : dcn201_clock_source_create(ctx, ctx->dc_bios,
1165 : CLOCK_SOURCE_COMBO_PHY_PLL0,
1166 : &clk_src_regs[0], false);
1167 0 : pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1168 0 : dcn201_clock_source_create(ctx, ctx->dc_bios,
1169 : CLOCK_SOURCE_COMBO_PHY_PLL1,
1170 : &clk_src_regs[1], false);
1171 :
1172 0 : pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1173 :
1174 : /* todo: not reuse phy_pll registers */
1175 0 : pool->base.dp_clock_source =
1176 0 : dcn201_clock_source_create(ctx, ctx->dc_bios,
1177 : CLOCK_SOURCE_ID_DP_DTO,
1178 : &clk_src_regs[0], true);
1179 :
1180 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1181 0 : if (pool->base.clock_sources[i] == NULL) {
1182 0 : dm_error("DC: failed to create clock sources!\n");
1183 0 : goto create_fail;
1184 : }
1185 : }
1186 :
1187 0 : pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1188 0 : if (pool->base.dccg == NULL) {
1189 0 : dm_error("DC: failed to create dccg!\n");
1190 0 : goto create_fail;
1191 : }
1192 :
1193 0 : dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1194 0 : dcn201_ip.max_num_dpp = pool->base.pipe_count;
1195 0 : dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1196 : {
1197 : struct irq_service_init_data init_data;
1198 0 : init_data.ctx = dc->ctx;
1199 0 : pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1200 0 : if (!pool->base.irqs)
1201 : goto create_fail;
1202 : }
1203 :
1204 : /* mem input -> ipp -> dpp -> opp -> TG */
1205 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1206 0 : pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1207 0 : if (pool->base.hubps[i] == NULL) {
1208 0 : dm_error(
1209 : "DC: failed to create memory input!\n");
1210 0 : goto create_fail;
1211 : }
1212 :
1213 0 : pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1214 0 : if (pool->base.ipps[i] == NULL) {
1215 0 : dm_error(
1216 : "DC: failed to create input pixel processor!\n");
1217 0 : goto create_fail;
1218 : }
1219 :
1220 0 : pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1221 0 : if (pool->base.dpps[i] == NULL) {
1222 0 : dm_error(
1223 : "DC: failed to create dpps!\n");
1224 0 : goto create_fail;
1225 : }
1226 : }
1227 :
1228 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1229 0 : pool->base.opps[i] = dcn201_opp_create(ctx, i);
1230 0 : if (pool->base.opps[i] == NULL) {
1231 0 : dm_error(
1232 : "DC: failed to create output pixel processor!\n");
1233 0 : goto create_fail;
1234 : }
1235 : }
1236 :
1237 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1238 0 : pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1239 0 : if (pool->base.engines[i] == NULL) {
1240 0 : dm_error(
1241 : "DC:failed to create aux engine!!\n");
1242 0 : goto create_fail;
1243 : }
1244 0 : pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1245 0 : if (pool->base.hw_i2cs[i] == NULL) {
1246 0 : dm_error(
1247 : "DC:failed to create hw i2c!!\n");
1248 0 : goto create_fail;
1249 : }
1250 0 : pool->base.sw_i2cs[i] = NULL;
1251 : }
1252 :
1253 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1254 0 : pool->base.timing_generators[i] = dcn201_timing_generator_create(
1255 : ctx, i);
1256 0 : if (pool->base.timing_generators[i] == NULL) {
1257 0 : dm_error("DC: failed to create tg!\n");
1258 0 : goto create_fail;
1259 : }
1260 : }
1261 :
1262 0 : pool->base.timing_generator_count = i;
1263 :
1264 0 : pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1265 0 : if (pool->base.mpc == NULL) {
1266 0 : dm_error("DC: failed to create mpc!\n");
1267 0 : goto create_fail;
1268 : }
1269 :
1270 0 : pool->base.hubbub = dcn201_hubbub_create(ctx);
1271 0 : if (pool->base.hubbub == NULL) {
1272 0 : dm_error("DC: failed to create hubbub!\n");
1273 0 : goto create_fail;
1274 : }
1275 :
1276 0 : if (!resource_construct(num_virtual_links, dc, &pool->base,
1277 0 : (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1278 : &res_create_funcs : &res_create_maximus_funcs)))
1279 : goto create_fail;
1280 :
1281 0 : dcn201_hw_sequencer_construct(dc);
1282 :
1283 0 : dc->caps.max_planes = pool->base.pipe_count;
1284 :
1285 0 : for (i = 0; i < dc->caps.max_planes; ++i)
1286 0 : dc->caps.planes[i] = plane_cap;
1287 :
1288 0 : dc->cap_funcs = cap_funcs;
1289 :
1290 0 : return true;
1291 :
1292 : create_fail:
1293 :
1294 0 : dcn201_resource_destruct(pool);
1295 :
1296 0 : return false;
1297 : }
1298 :
1299 0 : struct resource_pool *dcn201_create_resource_pool(
1300 : const struct dc_init_data *init_data,
1301 : struct dc *dc)
1302 : {
1303 0 : struct dcn201_resource_pool *pool =
1304 : kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC);
1305 :
1306 0 : if (!pool)
1307 : return NULL;
1308 :
1309 0 : if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1310 0 : return &pool->base;
1311 :
1312 0 : kfree(pool);
1313 0 : return NULL;
1314 : }
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