Line data Source code
1 : /*
2 : * Copyright 2018 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dcn10/dcn10_hubp.h"
27 : #include "dcn21_hubp.h"
28 :
29 : #include "dm_services.h"
30 : #include "reg_helper.h"
31 :
32 : #include "dc_dmub_srv.h"
33 :
34 : #define DC_LOGGER_INIT(logger)
35 :
36 : #define REG(reg)\
37 : hubp21->hubp_regs->reg
38 :
39 : #define CTX \
40 : hubp21->base.ctx
41 :
42 : #undef FN
43 : #define FN(reg_name, field_name) \
44 : hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
45 :
46 : /*
47 : * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
48 : * As a result, if S/W updates any of these registers during a mode change,
49 : * the current frame before the mode change will use the new value right away
50 : * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
51 : *
52 : * REFCYC_PER_VM_GROUP_FLIP[22:0]
53 : * REFCYC_PER_VM_GROUP_VBLANK[22:0]
54 : * REFCYC_PER_VM_REQ_FLIP[22:0]
55 : * REFCYC_PER_VM_REQ_VBLANK[22:0]
56 : *
57 : * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
58 : * when flipping to a new surface
59 : *
60 : * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
61 : * during prefetch period of a frame. The prefetch starts at a pre-determined
62 : * number of lines before the display active per frame
63 : *
64 : * DCN may underflow due to incorrectly programming these registers
65 : * during VM stage of prefetch/iflip. First lines of display active
66 : * or a sub-region of active using a new surface will be corrupted
67 : * until the VM data returns at flip/mode change transitions
68 : *
69 : * Work around:
70 : * workaround is always opt to use the more aggressive settings.
71 : * On any mode switch, if the new reg values are smaller than the current values,
72 : * then update the regs with the new values.
73 : *
74 : * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
75 : *
76 : */
77 0 : void apply_DEDCN21_142_wa_for_hostvm_deadline(
78 : struct hubp *hubp,
79 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
80 : {
81 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
82 : uint32_t refcyc_per_vm_group_vblank;
83 : uint32_t refcyc_per_vm_req_vblank;
84 : uint32_t refcyc_per_vm_group_flip;
85 : uint32_t refcyc_per_vm_req_flip;
86 0 : const uint32_t uninitialized_hw_default = 0;
87 :
88 0 : REG_GET(VBLANK_PARAMETERS_5,
89 : REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank);
90 :
91 0 : if (refcyc_per_vm_group_vblank == uninitialized_hw_default ||
92 0 : refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank)
93 0 : REG_SET(VBLANK_PARAMETERS_5, 0,
94 : REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
95 :
96 0 : REG_GET(VBLANK_PARAMETERS_6,
97 : REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank);
98 :
99 0 : if (refcyc_per_vm_req_vblank == uninitialized_hw_default ||
100 0 : refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank)
101 0 : REG_SET(VBLANK_PARAMETERS_6, 0,
102 : REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
103 :
104 0 : REG_GET(FLIP_PARAMETERS_3,
105 : REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip);
106 :
107 0 : if (refcyc_per_vm_group_flip == uninitialized_hw_default ||
108 0 : refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip)
109 0 : REG_SET(FLIP_PARAMETERS_3, 0,
110 : REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
111 :
112 0 : REG_GET(FLIP_PARAMETERS_4,
113 : REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip);
114 :
115 0 : if (refcyc_per_vm_req_flip == uninitialized_hw_default ||
116 0 : refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip)
117 0 : REG_SET(FLIP_PARAMETERS_4, 0,
118 : REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
119 :
120 0 : REG_SET(FLIP_PARAMETERS_5, 0,
121 : REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
122 :
123 0 : REG_SET(FLIP_PARAMETERS_6, 0,
124 : REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
125 0 : }
126 :
127 0 : void hubp21_program_deadline(
128 : struct hubp *hubp,
129 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
130 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
131 : {
132 0 : hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
133 :
134 0 : apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
135 0 : }
136 :
137 0 : void hubp21_program_requestor(
138 : struct hubp *hubp,
139 : struct _vcs_dpi_display_rq_regs_st *rq_regs)
140 : {
141 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
142 :
143 0 : REG_UPDATE(HUBPRET_CONTROL,
144 : DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
145 0 : REG_SET_4(DCN_EXPANSION_MODE, 0,
146 : DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
147 : PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
148 : MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
149 : CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
150 0 : REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
151 : CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
152 : MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
153 : META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
154 : MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
155 : DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
156 : VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
157 : SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
158 : PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
159 0 : REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
160 : CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
161 : MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
162 : META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
163 : MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
164 : DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
165 : SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
166 : PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
167 0 : }
168 :
169 0 : static void hubp21_setup(
170 : struct hubp *hubp,
171 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
172 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
173 : struct _vcs_dpi_display_rq_regs_st *rq_regs,
174 : struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
175 : {
176 : /* otg is locked when this func is called. Register are double buffered.
177 : * disable the requestors is not needed
178 : */
179 :
180 0 : hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
181 0 : hubp21_program_requestor(hubp, rq_regs);
182 0 : hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
183 :
184 0 : }
185 :
186 0 : static void hubp21_set_viewport(
187 : struct hubp *hubp,
188 : const struct rect *viewport,
189 : const struct rect *viewport_c)
190 : {
191 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
192 :
193 0 : REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
194 : PRI_VIEWPORT_WIDTH, viewport->width,
195 : PRI_VIEWPORT_HEIGHT, viewport->height);
196 :
197 0 : REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
198 : PRI_VIEWPORT_X_START, viewport->x,
199 : PRI_VIEWPORT_Y_START, viewport->y);
200 :
201 : /*for stereo*/
202 0 : REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
203 : SEC_VIEWPORT_WIDTH, viewport->width,
204 : SEC_VIEWPORT_HEIGHT, viewport->height);
205 :
206 0 : REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
207 : SEC_VIEWPORT_X_START, viewport->x,
208 : SEC_VIEWPORT_Y_START, viewport->y);
209 :
210 : /* DC supports NV12 only at the moment */
211 0 : REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
212 : PRI_VIEWPORT_WIDTH_C, viewport_c->width,
213 : PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
214 :
215 0 : REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
216 : PRI_VIEWPORT_X_START_C, viewport_c->x,
217 : PRI_VIEWPORT_Y_START_C, viewport_c->y);
218 :
219 0 : REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
220 : SEC_VIEWPORT_WIDTH_C, viewport_c->width,
221 : SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
222 :
223 0 : REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
224 : SEC_VIEWPORT_X_START_C, viewport_c->x,
225 : SEC_VIEWPORT_Y_START_C, viewport_c->y);
226 0 : }
227 :
228 0 : static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
229 : struct vm_system_aperture_param *apt)
230 : {
231 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
232 :
233 : PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
234 : PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
235 :
236 : // The format of high/low are 48:18 of the 48 bit addr
237 0 : mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
238 0 : mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
239 :
240 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
241 : MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
242 :
243 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
244 : MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
245 :
246 0 : REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
247 : ENABLE_L1_TLB, 1,
248 : SYSTEM_ACCESS_MODE, 0x3);
249 0 : }
250 :
251 0 : static void hubp21_validate_dml_output(struct hubp *hubp,
252 : struct dc_context *ctx,
253 : struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
254 : struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
255 : struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
256 : {
257 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
258 0 : struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
259 0 : struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
260 0 : struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
261 : DC_LOGGER_INIT(ctx->logger);
262 0 : DC_LOG_DEBUG("DML Validation | Running Validation");
263 :
264 : /* Requester - Per hubp */
265 0 : REG_GET(HUBPRET_CONTROL,
266 : DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
267 0 : REG_GET_4(DCN_EXPANSION_MODE,
268 : DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
269 : PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
270 : MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
271 : CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
272 0 : REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
273 : CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
274 : MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
275 : META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
276 : MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
277 : DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
278 : VM_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
279 : SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
280 : PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
281 0 : REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
282 : CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
283 : MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
284 : META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
285 : MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
286 : DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
287 : SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
288 : PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
289 :
290 0 : if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
291 0 : DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
292 : dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
293 0 : if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
294 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
295 : dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
296 0 : if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
297 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
298 : dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
299 0 : if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
300 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
301 : dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
302 0 : if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
303 0 : DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
304 : dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
305 :
306 0 : if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
307 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
308 : dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
309 0 : if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
310 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
311 : dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
312 0 : if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
313 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
314 : dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
315 0 : if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
316 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",
317 : dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
318 0 : if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
319 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
320 : dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
321 0 : if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
322 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:VM_GROUP_SIZE - Expected: %u Actual: %u\n",
323 : dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
324 0 : if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
325 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
326 : dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
327 0 : if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
328 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",
329 : dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
330 :
331 0 : if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
332 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",
333 : dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
334 0 : if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
335 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
336 : dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
337 0 : if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
338 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
339 : dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
340 0 : if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
341 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
342 : dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
343 0 : if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
344 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
345 : dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
346 0 : if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
347 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",
348 : dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
349 0 : if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
350 0 : DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",
351 : dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
352 :
353 :
354 : /* DLG - Per hubp */
355 0 : REG_GET_2(BLANK_OFFSET_0,
356 : REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
357 : DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
358 0 : REG_GET(BLANK_OFFSET_1,
359 : MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
360 0 : REG_GET(DST_DIMENSIONS,
361 : REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
362 0 : REG_GET_2(DST_AFTER_SCALER,
363 : REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
364 : DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
365 0 : REG_GET(REF_FREQ_TO_PIX_FREQ,
366 : REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
367 :
368 0 : if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
369 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",
370 : dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
371 0 : if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
372 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",
373 : dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
374 0 : if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
375 0 : DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
376 : dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
377 0 : if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
378 0 : DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",
379 : dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
380 0 : if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
381 0 : DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",
382 : dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
383 0 : if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
384 0 : DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",
385 : dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
386 0 : if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
387 0 : DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",
388 : dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
389 :
390 : /* DLG - Per luma/chroma */
391 0 : REG_GET(VBLANK_PARAMETERS_1,
392 : REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
393 0 : if (REG(NOM_PARAMETERS_0))
394 0 : REG_GET(NOM_PARAMETERS_0,
395 : DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
396 0 : if (REG(NOM_PARAMETERS_1))
397 0 : REG_GET(NOM_PARAMETERS_1,
398 : REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
399 0 : REG_GET(NOM_PARAMETERS_4,
400 : DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
401 0 : REG_GET(NOM_PARAMETERS_5,
402 : REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
403 0 : REG_GET_2(PER_LINE_DELIVERY,
404 : REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
405 : REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
406 0 : REG_GET_2(PER_LINE_DELIVERY_PRE,
407 : REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
408 : REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
409 0 : REG_GET(VBLANK_PARAMETERS_2,
410 : REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
411 0 : if (REG(NOM_PARAMETERS_2))
412 0 : REG_GET(NOM_PARAMETERS_2,
413 : DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
414 0 : if (REG(NOM_PARAMETERS_3))
415 0 : REG_GET(NOM_PARAMETERS_3,
416 : REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
417 0 : REG_GET(NOM_PARAMETERS_6,
418 : DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
419 0 : REG_GET(NOM_PARAMETERS_7,
420 : REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
421 0 : REG_GET(VBLANK_PARAMETERS_3,
422 : REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
423 0 : REG_GET(VBLANK_PARAMETERS_4,
424 : REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
425 :
426 0 : if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
427 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",
428 : dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
429 0 : if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
430 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",
431 : dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
432 0 : if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
433 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",
434 : dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
435 0 : if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
436 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",
437 : dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
438 0 : if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
439 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",
440 : dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
441 0 : if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
442 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",
443 : dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
444 0 : if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
445 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",
446 : dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
447 0 : if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
448 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",
449 : dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
450 0 : if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
451 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",
452 : dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
453 0 : if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
454 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",
455 : dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
456 0 : if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
457 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",
458 : dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
459 0 : if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
460 0 : DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",
461 : dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
462 0 : if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
463 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",
464 : dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
465 0 : if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
466 0 : DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",
467 : dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
468 0 : if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
469 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",
470 : dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
471 0 : if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
472 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",
473 : dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
474 :
475 : /* TTU - per hubp */
476 0 : REG_GET_2(DCN_TTU_QOS_WM,
477 : QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
478 : QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
479 :
480 0 : if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
481 0 : DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",
482 : dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
483 0 : if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
484 0 : DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
485 : dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
486 :
487 : /* TTU - per luma/chroma */
488 : /* Assumed surf0 is luma and 1 is chroma */
489 0 : REG_GET_3(DCN_SURF0_TTU_CNTL0,
490 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
491 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
492 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
493 0 : REG_GET_3(DCN_SURF1_TTU_CNTL0,
494 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
495 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
496 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
497 0 : REG_GET_3(DCN_CUR0_TTU_CNTL0,
498 : REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
499 : QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
500 : QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
501 0 : REG_GET(FLIP_PARAMETERS_1,
502 : REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
503 0 : REG_GET(DCN_CUR0_TTU_CNTL1,
504 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
505 0 : REG_GET(DCN_CUR1_TTU_CNTL1,
506 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
507 0 : REG_GET(DCN_SURF0_TTU_CNTL1,
508 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
509 0 : REG_GET(DCN_SURF1_TTU_CNTL1,
510 : REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
511 :
512 0 : if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
513 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
514 : dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
515 0 : if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
516 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
517 : dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
518 0 : if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
519 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
520 : dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
521 0 : if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
522 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
523 : dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
524 0 : if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
525 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
526 : dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
527 0 : if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
528 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
529 : dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
530 0 : if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
531 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
532 : dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
533 0 : if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
534 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
535 : dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
536 0 : if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
537 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
538 : dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
539 0 : if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
540 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",
541 : dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
542 0 : if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
543 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
544 : dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
545 0 : if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
546 0 : DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
547 : dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
548 0 : if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
549 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
550 : dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
551 0 : if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
552 0 : DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
553 : dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
554 :
555 : /* Host VM deadline regs */
556 0 : REG_GET(VBLANK_PARAMETERS_5,
557 : REFCYC_PER_VM_GROUP_VBLANK, &dlg_attr.refcyc_per_vm_group_vblank);
558 0 : REG_GET(VBLANK_PARAMETERS_6,
559 : REFCYC_PER_VM_REQ_VBLANK, &dlg_attr.refcyc_per_vm_req_vblank);
560 0 : REG_GET(FLIP_PARAMETERS_3,
561 : REFCYC_PER_VM_GROUP_FLIP, &dlg_attr.refcyc_per_vm_group_flip);
562 0 : REG_GET(FLIP_PARAMETERS_4,
563 : REFCYC_PER_VM_REQ_FLIP, &dlg_attr.refcyc_per_vm_req_flip);
564 0 : REG_GET(FLIP_PARAMETERS_5,
565 : REFCYC_PER_PTE_GROUP_FLIP_C, &dlg_attr.refcyc_per_pte_group_flip_c);
566 0 : REG_GET(FLIP_PARAMETERS_6,
567 : REFCYC_PER_META_CHUNK_FLIP_C, &dlg_attr.refcyc_per_meta_chunk_flip_c);
568 0 : REG_GET(FLIP_PARAMETERS_2,
569 : REFCYC_PER_META_CHUNK_FLIP_L, &dlg_attr.refcyc_per_meta_chunk_flip_l);
570 :
571 0 : if (dlg_attr.refcyc_per_vm_group_vblank != dml_dlg_attr->refcyc_per_vm_group_vblank)
572 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_5:REFCYC_PER_VM_GROUP_VBLANK - Expected: %u Actual: %u\n",
573 : dml_dlg_attr->refcyc_per_vm_group_vblank, dlg_attr.refcyc_per_vm_group_vblank);
574 0 : if (dlg_attr.refcyc_per_vm_req_vblank != dml_dlg_attr->refcyc_per_vm_req_vblank)
575 0 : DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_6:REFCYC_PER_VM_REQ_VBLANK - Expected: %u Actual: %u\n",
576 : dml_dlg_attr->refcyc_per_vm_req_vblank, dlg_attr.refcyc_per_vm_req_vblank);
577 0 : if (dlg_attr.refcyc_per_vm_group_flip != dml_dlg_attr->refcyc_per_vm_group_flip)
578 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_3:REFCYC_PER_VM_GROUP_FLIP - Expected: %u Actual: %u\n",
579 : dml_dlg_attr->refcyc_per_vm_group_flip, dlg_attr.refcyc_per_vm_group_flip);
580 0 : if (dlg_attr.refcyc_per_vm_req_flip != dml_dlg_attr->refcyc_per_vm_req_flip)
581 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_4:REFCYC_PER_VM_REQ_FLIP - Expected: %u Actual: %u\n",
582 : dml_dlg_attr->refcyc_per_vm_req_flip, dlg_attr.refcyc_per_vm_req_flip);
583 0 : if (dlg_attr.refcyc_per_pte_group_flip_c != dml_dlg_attr->refcyc_per_pte_group_flip_c)
584 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_5:REFCYC_PER_PTE_GROUP_FLIP_C - Expected: %u Actual: %u\n",
585 : dml_dlg_attr->refcyc_per_pte_group_flip_c, dlg_attr.refcyc_per_pte_group_flip_c);
586 0 : if (dlg_attr.refcyc_per_meta_chunk_flip_c != dml_dlg_attr->refcyc_per_meta_chunk_flip_c)
587 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_6:REFCYC_PER_META_CHUNK_FLIP_C - Expected: %u Actual: %u\n",
588 : dml_dlg_attr->refcyc_per_meta_chunk_flip_c, dlg_attr.refcyc_per_meta_chunk_flip_c);
589 0 : if (dlg_attr.refcyc_per_meta_chunk_flip_l != dml_dlg_attr->refcyc_per_meta_chunk_flip_l)
590 0 : DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_2:REFCYC_PER_META_CHUNK_FLIP_L - Expected: %u Actual: %u\n",
591 : dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);
592 0 : }
593 :
594 0 : static void program_surface_flip_and_addr(struct hubp *hubp, struct surface_flip_registers *flip_regs)
595 : {
596 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
597 :
598 0 : REG_UPDATE_3(DCSURF_FLIP_CONTROL,
599 : SURFACE_FLIP_TYPE, flip_regs->immediate,
600 : SURFACE_FLIP_MODE_FOR_STEREOSYNC, flip_regs->grph_stereo,
601 : SURFACE_FLIP_IN_STEREOSYNC, flip_regs->grph_stereo);
602 :
603 0 : REG_UPDATE(VMID_SETTINGS_0,
604 : VMID, flip_regs->vmid);
605 :
606 0 : REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
607 : PRIMARY_SURFACE_TMZ, flip_regs->tmz_surface,
608 : PRIMARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
609 : PRIMARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
610 : PRIMARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface,
611 : SECONDARY_SURFACE_TMZ, flip_regs->tmz_surface,
612 : SECONDARY_SURFACE_TMZ_C, flip_regs->tmz_surface,
613 : SECONDARY_META_SURFACE_TMZ, flip_regs->tmz_surface,
614 : SECONDARY_META_SURFACE_TMZ_C, flip_regs->tmz_surface);
615 :
616 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
617 : PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
618 : flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);
619 :
620 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
621 : PRIMARY_META_SURFACE_ADDRESS_C,
622 : flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);
623 :
624 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
625 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
626 : flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);
627 :
628 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
629 : PRIMARY_META_SURFACE_ADDRESS,
630 : flip_regs->DCSURF_PRIMARY_META_SURFACE_ADDRESS);
631 :
632 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
633 : SECONDARY_META_SURFACE_ADDRESS_HIGH,
634 : flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);
635 :
636 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
637 : SECONDARY_META_SURFACE_ADDRESS,
638 : flip_regs->DCSURF_SECONDARY_META_SURFACE_ADDRESS);
639 :
640 :
641 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
642 : SECONDARY_SURFACE_ADDRESS_HIGH,
643 : flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);
644 :
645 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
646 : SECONDARY_SURFACE_ADDRESS,
647 : flip_regs->DCSURF_SECONDARY_SURFACE_ADDRESS);
648 :
649 :
650 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
651 : PRIMARY_SURFACE_ADDRESS_HIGH_C,
652 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);
653 :
654 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
655 : PRIMARY_SURFACE_ADDRESS_C,
656 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C);
657 :
658 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
659 : PRIMARY_SURFACE_ADDRESS_HIGH,
660 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);
661 :
662 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
663 : PRIMARY_SURFACE_ADDRESS,
664 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS);
665 0 : }
666 :
667 0 : static void dmcub_PLAT_54186_wa(struct hubp *hubp,
668 : struct surface_flip_registers *flip_regs)
669 : {
670 0 : struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv;
671 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
672 : union dmub_rb_cmd cmd;
673 :
674 0 : memset(&cmd, 0, sizeof(cmd));
675 :
676 0 : cmd.PLAT_54186_wa.header.type = DMUB_CMD__PLAT_54186_WA;
677 0 : cmd.PLAT_54186_wa.header.payload_bytes = sizeof(cmd.PLAT_54186_wa.flip);
678 0 : cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS =
679 0 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS;
680 0 : cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
681 0 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_C;
682 0 : cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
683 0 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
684 0 : cmd.PLAT_54186_wa.flip.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C =
685 0 : flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
686 0 : cmd.PLAT_54186_wa.flip.flip_params.grph_stereo = flip_regs->grph_stereo;
687 0 : cmd.PLAT_54186_wa.flip.flip_params.hubp_inst = hubp->inst;
688 0 : cmd.PLAT_54186_wa.flip.flip_params.immediate = flip_regs->immediate;
689 0 : cmd.PLAT_54186_wa.flip.flip_params.tmz_surface = flip_regs->tmz_surface;
690 0 : cmd.PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid;
691 :
692 0 : PERF_TRACE(); // TODO: remove after performance is stable.
693 0 : dc_dmub_srv_cmd_queue(dmcub, &cmd);
694 0 : PERF_TRACE(); // TODO: remove after performance is stable.
695 0 : dc_dmub_srv_cmd_execute(dmcub);
696 0 : PERF_TRACE(); // TODO: remove after performance is stable.
697 0 : dc_dmub_srv_wait_idle(dmcub);
698 0 : PERF_TRACE(); // TODO: remove after performance is stable.
699 0 : }
700 :
701 0 : static bool hubp21_program_surface_flip_and_addr(
702 : struct hubp *hubp,
703 : const struct dc_plane_address *address,
704 : bool flip_immediate)
705 : {
706 0 : struct surface_flip_registers flip_regs = { 0 };
707 :
708 0 : flip_regs.vmid = address->vmid;
709 :
710 0 : switch (address->type) {
711 : case PLN_ADDR_TYPE_GRAPHICS:
712 0 : if (address->grph.addr.quad_part == 0) {
713 0 : BREAK_TO_DEBUGGER();
714 0 : break;
715 : }
716 :
717 0 : if (address->grph.meta_addr.quad_part != 0) {
718 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
719 0 : address->grph.meta_addr.low_part;
720 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
721 0 : address->grph.meta_addr.high_part;
722 : }
723 :
724 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
725 0 : address->grph.addr.low_part;
726 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
727 0 : address->grph.addr.high_part;
728 0 : break;
729 : case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
730 0 : if (address->video_progressive.luma_addr.quad_part == 0
731 0 : || address->video_progressive.chroma_addr.quad_part == 0)
732 : break;
733 :
734 0 : if (address->video_progressive.luma_meta_addr.quad_part != 0) {
735 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
736 0 : address->video_progressive.luma_meta_addr.low_part;
737 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
738 0 : address->video_progressive.luma_meta_addr.high_part;
739 :
740 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_C =
741 0 : address->video_progressive.chroma_meta_addr.low_part;
742 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C =
743 0 : address->video_progressive.chroma_meta_addr.high_part;
744 : }
745 :
746 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
747 0 : address->video_progressive.luma_addr.low_part;
748 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
749 0 : address->video_progressive.luma_addr.high_part;
750 :
751 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_C =
752 0 : address->video_progressive.chroma_addr.low_part;
753 :
754 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C =
755 0 : address->video_progressive.chroma_addr.high_part;
756 :
757 0 : break;
758 : case PLN_ADDR_TYPE_GRPH_STEREO:
759 0 : if (address->grph_stereo.left_addr.quad_part == 0)
760 : break;
761 0 : if (address->grph_stereo.right_addr.quad_part == 0)
762 : break;
763 :
764 0 : flip_regs.grph_stereo = true;
765 :
766 0 : if (address->grph_stereo.right_meta_addr.quad_part != 0) {
767 0 : flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS =
768 0 : address->grph_stereo.right_meta_addr.low_part;
769 0 : flip_regs.DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH =
770 0 : address->grph_stereo.right_meta_addr.high_part;
771 : }
772 :
773 0 : if (address->grph_stereo.left_meta_addr.quad_part != 0) {
774 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS =
775 0 : address->grph_stereo.left_meta_addr.low_part;
776 0 : flip_regs.DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH =
777 0 : address->grph_stereo.left_meta_addr.high_part;
778 : }
779 :
780 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS =
781 0 : address->grph_stereo.left_addr.low_part;
782 0 : flip_regs.DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH =
783 0 : address->grph_stereo.left_addr.high_part;
784 :
785 0 : flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS =
786 0 : address->grph_stereo.right_addr.low_part;
787 0 : flip_regs.DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH =
788 0 : address->grph_stereo.right_addr.high_part;
789 :
790 0 : break;
791 : default:
792 0 : BREAK_TO_DEBUGGER();
793 0 : break;
794 : }
795 :
796 0 : flip_regs.tmz_surface = address->tmz_surface;
797 0 : flip_regs.immediate = flip_immediate;
798 :
799 0 : if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
800 0 : dmcub_PLAT_54186_wa(hubp, &flip_regs);
801 : else
802 0 : program_surface_flip_and_addr(hubp, &flip_regs);
803 :
804 0 : hubp->request_address = *address;
805 :
806 0 : return true;
807 : }
808 :
809 0 : static void hubp21_init(struct hubp *hubp)
810 : {
811 : // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
812 : // This is a chicken bit to enable the ECO fix.
813 :
814 0 : struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
815 : //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
816 0 : REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
817 0 : }
818 : static struct hubp_funcs dcn21_hubp_funcs = {
819 : .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
820 : .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
821 : .hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr,
822 : .hubp_program_surface_config = hubp1_program_surface_config,
823 : .hubp_is_flip_pending = hubp1_is_flip_pending,
824 : .hubp_setup = hubp21_setup,
825 : .hubp_setup_interdependent = hubp2_setup_interdependent,
826 : .hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
827 : .set_blank = hubp1_set_blank,
828 : .dcc_control = hubp1_dcc_control,
829 : .mem_program_viewport = hubp21_set_viewport,
830 : .set_cursor_attributes = hubp2_cursor_set_attributes,
831 : .set_cursor_position = hubp1_cursor_set_position,
832 : .hubp_clk_cntl = hubp1_clk_cntl,
833 : .hubp_vtg_sel = hubp1_vtg_sel,
834 : .dmdata_set_attributes = hubp2_dmdata_set_attributes,
835 : .dmdata_load = hubp2_dmdata_load,
836 : .dmdata_status_done = hubp2_dmdata_status_done,
837 : .hubp_read_state = hubp2_read_state,
838 : .hubp_clear_underflow = hubp1_clear_underflow,
839 : .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
840 : .hubp_init = hubp21_init,
841 : .validate_dml_output = hubp21_validate_dml_output,
842 : .hubp_set_flip_int = hubp1_set_flip_int,
843 : };
844 :
845 0 : bool hubp21_construct(
846 : struct dcn21_hubp *hubp21,
847 : struct dc_context *ctx,
848 : uint32_t inst,
849 : const struct dcn_hubp2_registers *hubp_regs,
850 : const struct dcn_hubp2_shift *hubp_shift,
851 : const struct dcn_hubp2_mask *hubp_mask)
852 : {
853 0 : hubp21->base.funcs = &dcn21_hubp_funcs;
854 0 : hubp21->base.ctx = ctx;
855 0 : hubp21->hubp_regs = hubp_regs;
856 0 : hubp21->hubp_shift = hubp_shift;
857 0 : hubp21->hubp_mask = hubp_mask;
858 0 : hubp21->base.inst = inst;
859 0 : hubp21->base.opp_id = OPP_ID_INVALID;
860 0 : hubp21->base.mpcc_id = 0xf;
861 :
862 0 : return true;
863 : }
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