Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dcn30_hubp.h"
27 :
28 : #include "dm_services.h"
29 : #include "dce_calcs.h"
30 : #include "reg_helper.h"
31 : #include "basics/conversion.h"
32 : #include "dcn20/dcn20_hubp.h"
33 : #include "dcn21/dcn21_hubp.h"
34 :
35 : #define REG(reg)\
36 : hubp2->hubp_regs->reg
37 :
38 : #define CTX \
39 : hubp2->base.ctx
40 :
41 : #undef FN
42 : #define FN(reg_name, field_name) \
43 : hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
44 :
45 0 : void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
46 : struct vm_system_aperture_param *apt)
47 : {
48 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
49 :
50 : PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
51 : PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
52 : PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
53 :
54 : // The format of default addr is 48:12 of the 48 bit addr
55 0 : mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
56 :
57 : // The format of high/low are 48:18 of the 48 bit addr
58 0 : mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
59 0 : mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
60 :
61 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
62 : MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
63 :
64 0 : REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
65 : MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
66 :
67 0 : REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
68 : ENABLE_L1_TLB, 1,
69 : SYSTEM_ACCESS_MODE, 0x3);
70 0 : }
71 :
72 0 : bool hubp3_program_surface_flip_and_addr(
73 : struct hubp *hubp,
74 : const struct dc_plane_address *address,
75 : bool flip_immediate)
76 : {
77 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
78 :
79 : //program flip type
80 0 : REG_UPDATE(DCSURF_FLIP_CONTROL,
81 : SURFACE_FLIP_TYPE, flip_immediate);
82 :
83 : // Program VMID reg
84 0 : if (flip_immediate == 0)
85 0 : REG_UPDATE(VMID_SETTINGS_0,
86 : VMID, address->vmid);
87 :
88 0 : if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
89 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);
90 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
91 :
92 : } else {
93 : // turn off stereo if not in stereo
94 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
95 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
96 : }
97 :
98 : /* HW automatically latch rest of address register on write to
99 : * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
100 : *
101 : * program high first and then the low addr, order matters!
102 : */
103 0 : switch (address->type) {
104 : case PLN_ADDR_TYPE_GRAPHICS:
105 : /* DCN1.0 does not support const color
106 : * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
107 : * base on address->grph.dcc_const_color
108 : * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
109 : * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
110 : */
111 :
112 0 : if (address->grph.addr.quad_part == 0)
113 : break;
114 :
115 0 : REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
116 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
117 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
118 :
119 0 : if (address->grph.meta_addr.quad_part != 0) {
120 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
121 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
122 : address->grph.meta_addr.high_part);
123 :
124 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
125 : PRIMARY_META_SURFACE_ADDRESS,
126 : address->grph.meta_addr.low_part);
127 : }
128 :
129 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
130 : PRIMARY_SURFACE_ADDRESS_HIGH,
131 : address->grph.addr.high_part);
132 :
133 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
134 : PRIMARY_SURFACE_ADDRESS,
135 : address->grph.addr.low_part);
136 0 : break;
137 : case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
138 0 : if (address->video_progressive.luma_addr.quad_part == 0
139 0 : || address->video_progressive.chroma_addr.quad_part == 0)
140 : break;
141 :
142 0 : REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
143 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
144 : PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
145 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
146 : PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
147 :
148 0 : if (address->video_progressive.luma_meta_addr.quad_part != 0) {
149 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
150 : PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
151 : address->video_progressive.chroma_meta_addr.high_part);
152 :
153 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
154 : PRIMARY_META_SURFACE_ADDRESS_C,
155 : address->video_progressive.chroma_meta_addr.low_part);
156 :
157 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
158 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
159 : address->video_progressive.luma_meta_addr.high_part);
160 :
161 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
162 : PRIMARY_META_SURFACE_ADDRESS,
163 : address->video_progressive.luma_meta_addr.low_part);
164 : }
165 :
166 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
167 : PRIMARY_SURFACE_ADDRESS_HIGH_C,
168 : address->video_progressive.chroma_addr.high_part);
169 :
170 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
171 : PRIMARY_SURFACE_ADDRESS_C,
172 : address->video_progressive.chroma_addr.low_part);
173 :
174 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
175 : PRIMARY_SURFACE_ADDRESS_HIGH,
176 : address->video_progressive.luma_addr.high_part);
177 :
178 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
179 : PRIMARY_SURFACE_ADDRESS,
180 : address->video_progressive.luma_addr.low_part);
181 0 : break;
182 : case PLN_ADDR_TYPE_GRPH_STEREO:
183 0 : if (address->grph_stereo.left_addr.quad_part == 0)
184 : break;
185 0 : if (address->grph_stereo.right_addr.quad_part == 0)
186 : break;
187 :
188 0 : REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
189 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
190 : PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
191 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
192 : PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
193 : SECONDARY_SURFACE_TMZ, address->tmz_surface,
194 : SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
195 : SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
196 : SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
197 :
198 0 : if (address->grph_stereo.right_meta_addr.quad_part != 0) {
199 :
200 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,
201 : SECONDARY_META_SURFACE_ADDRESS_HIGH_C,
202 : address->grph_stereo.right_alpha_meta_addr.high_part);
203 :
204 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,
205 : SECONDARY_META_SURFACE_ADDRESS_C,
206 : address->grph_stereo.right_alpha_meta_addr.low_part);
207 :
208 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
209 : SECONDARY_META_SURFACE_ADDRESS_HIGH,
210 : address->grph_stereo.right_meta_addr.high_part);
211 :
212 0 : REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
213 : SECONDARY_META_SURFACE_ADDRESS,
214 : address->grph_stereo.right_meta_addr.low_part);
215 : }
216 0 : if (address->grph_stereo.left_meta_addr.quad_part != 0) {
217 :
218 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
219 : PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
220 : address->grph_stereo.left_alpha_meta_addr.high_part);
221 :
222 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
223 : PRIMARY_META_SURFACE_ADDRESS_C,
224 : address->grph_stereo.left_alpha_meta_addr.low_part);
225 :
226 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
227 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
228 : address->grph_stereo.left_meta_addr.high_part);
229 :
230 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
231 : PRIMARY_META_SURFACE_ADDRESS,
232 : address->grph_stereo.left_meta_addr.low_part);
233 : }
234 :
235 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,
236 : SECONDARY_SURFACE_ADDRESS_HIGH_C,
237 : address->grph_stereo.right_alpha_addr.high_part);
238 :
239 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,
240 : SECONDARY_SURFACE_ADDRESS_C,
241 : address->grph_stereo.right_alpha_addr.low_part);
242 :
243 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
244 : SECONDARY_SURFACE_ADDRESS_HIGH,
245 : address->grph_stereo.right_addr.high_part);
246 :
247 0 : REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
248 : SECONDARY_SURFACE_ADDRESS,
249 : address->grph_stereo.right_addr.low_part);
250 :
251 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
252 : PRIMARY_SURFACE_ADDRESS_HIGH_C,
253 : address->grph_stereo.left_alpha_addr.high_part);
254 :
255 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
256 : PRIMARY_SURFACE_ADDRESS_C,
257 : address->grph_stereo.left_alpha_addr.low_part);
258 :
259 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
260 : PRIMARY_SURFACE_ADDRESS_HIGH,
261 : address->grph_stereo.left_addr.high_part);
262 :
263 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
264 : PRIMARY_SURFACE_ADDRESS,
265 : address->grph_stereo.left_addr.low_part);
266 0 : break;
267 : case PLN_ADDR_TYPE_RGBEA:
268 0 : if (address->rgbea.addr.quad_part == 0
269 0 : || address->rgbea.alpha_addr.quad_part == 0)
270 : break;
271 :
272 0 : REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
273 : PRIMARY_SURFACE_TMZ, address->tmz_surface,
274 : PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
275 : PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
276 : PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
277 :
278 0 : if (address->rgbea.meta_addr.quad_part != 0) {
279 :
280 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
281 : PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
282 : address->rgbea.alpha_meta_addr.high_part);
283 :
284 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
285 : PRIMARY_META_SURFACE_ADDRESS_C,
286 : address->rgbea.alpha_meta_addr.low_part);
287 :
288 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
289 : PRIMARY_META_SURFACE_ADDRESS_HIGH,
290 : address->rgbea.meta_addr.high_part);
291 :
292 0 : REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
293 : PRIMARY_META_SURFACE_ADDRESS,
294 : address->rgbea.meta_addr.low_part);
295 : }
296 :
297 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
298 : PRIMARY_SURFACE_ADDRESS_HIGH_C,
299 : address->rgbea.alpha_addr.high_part);
300 :
301 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
302 : PRIMARY_SURFACE_ADDRESS_C,
303 : address->rgbea.alpha_addr.low_part);
304 :
305 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
306 : PRIMARY_SURFACE_ADDRESS_HIGH,
307 : address->rgbea.addr.high_part);
308 :
309 0 : REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
310 : PRIMARY_SURFACE_ADDRESS,
311 : address->rgbea.addr.low_part);
312 0 : break;
313 : default:
314 0 : BREAK_TO_DEBUGGER();
315 0 : break;
316 : }
317 :
318 0 : hubp->request_address = *address;
319 :
320 0 : return true;
321 : }
322 :
323 0 : static void hubp3_program_tiling(
324 : struct dcn20_hubp *hubp2,
325 : const union dc_tiling_info *info,
326 : const enum surface_pixel_format pixel_format)
327 : {
328 0 : REG_UPDATE_4(DCSURF_ADDR_CONFIG,
329 : NUM_PIPES, log_2(info->gfx9.num_pipes),
330 : PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
331 : MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
332 : NUM_PKRS, log_2(info->gfx9.num_pkrs));
333 :
334 0 : REG_UPDATE_3(DCSURF_TILING_CONFIG,
335 : SW_MODE, info->gfx9.swizzle,
336 : META_LINEAR, info->gfx9.meta_linear,
337 : PIPE_ALIGNED, info->gfx9.pipe_aligned);
338 :
339 0 : }
340 :
341 0 : void hubp3_dcc_control(struct hubp *hubp, bool enable,
342 : enum hubp_ind_block_size blk_size)
343 : {
344 0 : uint32_t dcc_en = enable ? 1 : 0;
345 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
346 :
347 0 : REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
348 : PRIMARY_SURFACE_DCC_EN, dcc_en,
349 : PRIMARY_SURFACE_DCC_IND_BLK, blk_size,
350 : SECONDARY_SURFACE_DCC_EN, dcc_en,
351 : SECONDARY_SURFACE_DCC_IND_BLK, blk_size);
352 0 : }
353 :
354 0 : void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
355 : struct dc_plane_dcc_param *dcc)
356 : {
357 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
358 :
359 0 : REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
360 : PRIMARY_SURFACE_DCC_EN, dcc->enable,
361 : PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
362 : PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c,
363 : SECONDARY_SURFACE_DCC_EN, dcc->enable,
364 : SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
365 : SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c);
366 0 : }
367 :
368 0 : void hubp3_dmdata_set_attributes(
369 : struct hubp *hubp,
370 : const struct dc_dmdata_attributes *attr)
371 : {
372 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
373 :
374 : /*always HW mode */
375 0 : REG_UPDATE(DMDATA_CNTL,
376 : DMDATA_MODE, 1);
377 :
378 : /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
379 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
380 :
381 : /* toggle DMDATA_UPDATED and set repeat and size */
382 0 : REG_UPDATE(DMDATA_CNTL,
383 : DMDATA_UPDATED, 0);
384 0 : REG_UPDATE_3(DMDATA_CNTL,
385 : DMDATA_UPDATED, 1,
386 : DMDATA_REPEAT, attr->dmdata_repeat,
387 : DMDATA_SIZE, attr->dmdata_size);
388 :
389 : /* set DMDATA address */
390 0 : REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
391 0 : REG_UPDATE(DMDATA_ADDRESS_HIGH,
392 : DMDATA_ADDRESS_HIGH, attr->address.high_part);
393 :
394 0 : REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
395 :
396 0 : }
397 :
398 :
399 0 : void hubp3_program_surface_config(
400 : struct hubp *hubp,
401 : enum surface_pixel_format format,
402 : union dc_tiling_info *tiling_info,
403 : struct plane_size *plane_size,
404 : enum dc_rotation_angle rotation,
405 : struct dc_plane_dcc_param *dcc,
406 : bool horizontal_mirror,
407 : unsigned int compat_level)
408 : {
409 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
410 :
411 0 : hubp3_dcc_control_sienna_cichlid(hubp, dcc);
412 0 : hubp3_program_tiling(hubp2, tiling_info, format);
413 0 : hubp2_program_size(hubp, format, plane_size, dcc);
414 0 : hubp2_program_rotation(hubp, rotation, horizontal_mirror);
415 0 : hubp2_program_pixel_format(hubp, format);
416 0 : }
417 :
418 0 : static void hubp3_program_deadline(
419 : struct hubp *hubp,
420 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
421 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
422 : {
423 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
424 :
425 0 : hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
426 0 : REG_UPDATE(DCN_DMDATA_VM_CNTL,
427 : REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata);
428 0 : }
429 :
430 0 : void hubp3_read_state(struct hubp *hubp)
431 : {
432 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
433 0 : struct dcn_hubp_state *s = &hubp2->state;
434 0 : struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
435 :
436 0 : hubp2_read_state_common(hubp);
437 :
438 0 : REG_GET_7(DCHUBP_REQ_SIZE_CONFIG,
439 : CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
440 : MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
441 : META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
442 : MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
443 : DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
444 : SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
445 : PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
446 :
447 0 : REG_GET_7(DCHUBP_REQ_SIZE_CONFIG_C,
448 : CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
449 : MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
450 : META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
451 : MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
452 : DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
453 : SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
454 : PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
455 :
456 0 : }
457 :
458 0 : void hubp3_setup(
459 : struct hubp *hubp,
460 : struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
461 : struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
462 : struct _vcs_dpi_display_rq_regs_st *rq_regs,
463 : struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
464 : {
465 : /* otg is locked when this func is called. Register are double buffered.
466 : * disable the requestors is not needed
467 : */
468 0 : hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
469 0 : hubp21_program_requestor(hubp, rq_regs);
470 0 : hubp3_program_deadline(hubp, dlg_attr, ttu_attr);
471 0 : }
472 :
473 0 : void hubp3_init(struct hubp *hubp)
474 : {
475 : // DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
476 : // This is a chicken bit to enable the ECO fix.
477 :
478 0 : struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
479 : //hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
480 0 : REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
481 0 : }
482 :
483 : static struct hubp_funcs dcn30_hubp_funcs = {
484 : .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
485 : .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
486 : .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
487 : .hubp_program_surface_config = hubp3_program_surface_config,
488 : .hubp_is_flip_pending = hubp2_is_flip_pending,
489 : .hubp_setup = hubp3_setup,
490 : .hubp_setup_interdependent = hubp2_setup_interdependent,
491 : .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
492 : .set_blank = hubp2_set_blank,
493 : .set_blank_regs = hubp2_set_blank_regs,
494 : .dcc_control = hubp3_dcc_control,
495 : .mem_program_viewport = min_set_viewport,
496 : .set_cursor_attributes = hubp2_cursor_set_attributes,
497 : .set_cursor_position = hubp2_cursor_set_position,
498 : .hubp_clk_cntl = hubp2_clk_cntl,
499 : .hubp_vtg_sel = hubp2_vtg_sel,
500 : .dmdata_set_attributes = hubp3_dmdata_set_attributes,
501 : .dmdata_load = hubp2_dmdata_load,
502 : .dmdata_status_done = hubp2_dmdata_status_done,
503 : .hubp_read_state = hubp3_read_state,
504 : .hubp_clear_underflow = hubp2_clear_underflow,
505 : .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
506 : .hubp_init = hubp3_init,
507 : .hubp_in_blank = hubp1_in_blank,
508 : .hubp_soft_reset = hubp1_soft_reset,
509 : .hubp_set_flip_int = hubp1_set_flip_int,
510 : };
511 :
512 0 : bool hubp3_construct(
513 : struct dcn20_hubp *hubp2,
514 : struct dc_context *ctx,
515 : uint32_t inst,
516 : const struct dcn_hubp2_registers *hubp_regs,
517 : const struct dcn_hubp2_shift *hubp_shift,
518 : const struct dcn_hubp2_mask *hubp_mask)
519 : {
520 0 : hubp2->base.funcs = &dcn30_hubp_funcs;
521 0 : hubp2->base.ctx = ctx;
522 0 : hubp2->hubp_regs = hubp_regs;
523 0 : hubp2->hubp_shift = hubp_shift;
524 0 : hubp2->hubp_mask = hubp_mask;
525 0 : hubp2->base.inst = inst;
526 0 : hubp2->base.opp_id = OPP_ID_INVALID;
527 0 : hubp2->base.mpcc_id = 0xf;
528 :
529 0 : return true;
530 : }
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