Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 :
27 : #include "dm_services.h"
28 : #include "dc.h"
29 :
30 : #include "dcn30_init.h"
31 :
32 : #include "resource.h"
33 : #include "include/irq_service_interface.h"
34 : #include "dcn20/dcn20_resource.h"
35 :
36 : #include "dcn30_resource.h"
37 :
38 : #include "dcn10/dcn10_ipp.h"
39 : #include "dcn30/dcn30_hubbub.h"
40 : #include "dcn30/dcn30_mpc.h"
41 : #include "dcn30/dcn30_hubp.h"
42 : #include "irq/dcn30/irq_service_dcn30.h"
43 : #include "dcn30/dcn30_dpp.h"
44 : #include "dcn30/dcn30_optc.h"
45 : #include "dcn20/dcn20_hwseq.h"
46 : #include "dcn30/dcn30_hwseq.h"
47 : #include "dce110/dce110_hw_sequencer.h"
48 : #include "dcn30/dcn30_opp.h"
49 : #include "dcn20/dcn20_dsc.h"
50 : #include "dcn30/dcn30_vpg.h"
51 : #include "dcn30/dcn30_afmt.h"
52 : #include "dcn30/dcn30_dio_stream_encoder.h"
53 : #include "dcn30/dcn30_dio_link_encoder.h"
54 : #include "dce/dce_clock_source.h"
55 : #include "dce/dce_audio.h"
56 : #include "dce/dce_hwseq.h"
57 : #include "clk_mgr.h"
58 : #include "virtual/virtual_stream_encoder.h"
59 : #include "dce110/dce110_resource.h"
60 : #include "dml/display_mode_vba.h"
61 : #include "dcn30/dcn30_dccg.h"
62 : #include "dcn10/dcn10_resource.h"
63 : #include "dc_link_ddc.h"
64 : #include "dce/dce_panel_cntl.h"
65 :
66 : #include "dcn30/dcn30_dwb.h"
67 : #include "dcn30/dcn30_mmhubbub.h"
68 :
69 : #include "sienna_cichlid_ip_offset.h"
70 : #include "dcn/dcn_3_0_0_offset.h"
71 : #include "dcn/dcn_3_0_0_sh_mask.h"
72 :
73 : #include "nbio/nbio_7_4_offset.h"
74 :
75 : #include "dpcs/dpcs_3_0_0_offset.h"
76 : #include "dpcs/dpcs_3_0_0_sh_mask.h"
77 :
78 : #include "mmhub/mmhub_2_0_0_offset.h"
79 : #include "mmhub/mmhub_2_0_0_sh_mask.h"
80 :
81 : #include "reg_helper.h"
82 : #include "dce/dmub_abm.h"
83 : #include "dce/dmub_psr.h"
84 : #include "dce/dce_aux.h"
85 : #include "dce/dce_i2c.h"
86 :
87 : #include "dml/dcn30/dcn30_fpu.h"
88 : #include "dml/dcn30/display_mode_vba_30.h"
89 : #include "vm_helper.h"
90 : #include "dcn20/dcn20_vmid.h"
91 : #include "amdgpu_socbb.h"
92 : #include "dc_dmub_srv.h"
93 :
94 : #define DC_LOGGER_INIT(logger)
95 :
96 : enum dcn30_clk_src_array_id {
97 : DCN30_CLK_SRC_PLL0,
98 : DCN30_CLK_SRC_PLL1,
99 : DCN30_CLK_SRC_PLL2,
100 : DCN30_CLK_SRC_PLL3,
101 : DCN30_CLK_SRC_PLL4,
102 : DCN30_CLK_SRC_PLL5,
103 : DCN30_CLK_SRC_TOTAL
104 : };
105 :
106 : /* begin *********************
107 : * macros to expend register list macro defined in HW object header file
108 : */
109 :
110 : /* DCN */
111 : /* TODO awful hack. fixup dcn20_dwb.h */
112 : #undef BASE_INNER
113 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
114 :
115 : #define BASE(seg) BASE_INNER(seg)
116 :
117 : #define SR(reg_name)\
118 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 : mm ## reg_name
120 :
121 : #define SRI(reg_name, block, id)\
122 : .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 : mm ## block ## id ## _ ## reg_name
124 :
125 : #define SRI2(reg_name, block, id)\
126 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
127 : mm ## reg_name
128 :
129 : #define SRIR(var_name, reg_name, block, id)\
130 : .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 : mm ## block ## id ## _ ## reg_name
132 :
133 : #define SRII(reg_name, block, id)\
134 : .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 : mm ## block ## id ## _ ## reg_name
136 :
137 : #define SRII_MPC_RMU(reg_name, block, id)\
138 : .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 : mm ## block ## id ## _ ## reg_name
140 :
141 : #define SRII_DWB(reg_name, temp_name, block, id)\
142 : .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
143 : mm ## block ## id ## _ ## temp_name
144 :
145 : #define DCCG_SRII(reg_name, block, id)\
146 : .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 : mm ## block ## id ## _ ## reg_name
148 :
149 : #define VUPDATE_SRII(reg_name, block, id)\
150 : .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
151 : mm ## reg_name ## _ ## block ## id
152 :
153 : /* NBIO */
154 : #define NBIO_BASE_INNER(seg) \
155 : NBIO_BASE__INST0_SEG ## seg
156 :
157 : #define NBIO_BASE(seg) \
158 : NBIO_BASE_INNER(seg)
159 :
160 : #define NBIO_SR(reg_name)\
161 : .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
162 : mm ## reg_name
163 :
164 : /* MMHUB */
165 : #define MMHUB_BASE_INNER(seg) \
166 : MMHUB_BASE__INST0_SEG ## seg
167 :
168 : #define MMHUB_BASE(seg) \
169 : MMHUB_BASE_INNER(seg)
170 :
171 : #define MMHUB_SR(reg_name)\
172 : .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
173 : mmMM ## reg_name
174 :
175 : /* CLOCK */
176 : #define CLK_BASE_INNER(seg) \
177 : CLK_BASE__INST0_SEG ## seg
178 :
179 : #define CLK_BASE(seg) \
180 : CLK_BASE_INNER(seg)
181 :
182 : #define CLK_SRI(reg_name, block, inst)\
183 : .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
184 : mm ## block ## _ ## inst ## _ ## reg_name
185 :
186 :
187 : static const struct bios_registers bios_regs = {
188 : NBIO_SR(BIOS_SCRATCH_3),
189 : NBIO_SR(BIOS_SCRATCH_6)
190 : };
191 :
192 : #define clk_src_regs(index, pllid)\
193 : [index] = {\
194 : CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
195 : }
196 :
197 : static const struct dce110_clk_src_regs clk_src_regs[] = {
198 : clk_src_regs(0, A),
199 : clk_src_regs(1, B),
200 : clk_src_regs(2, C),
201 : clk_src_regs(3, D),
202 : clk_src_regs(4, E),
203 : clk_src_regs(5, F)
204 : };
205 :
206 : static const struct dce110_clk_src_shift cs_shift = {
207 : CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
208 : };
209 :
210 : static const struct dce110_clk_src_mask cs_mask = {
211 : CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
212 : };
213 :
214 : #define abm_regs(id)\
215 : [id] = {\
216 : ABM_DCN30_REG_LIST(id)\
217 : }
218 :
219 : static const struct dce_abm_registers abm_regs[] = {
220 : abm_regs(0),
221 : abm_regs(1),
222 : abm_regs(2),
223 : abm_regs(3),
224 : abm_regs(4),
225 : abm_regs(5),
226 : };
227 :
228 : static const struct dce_abm_shift abm_shift = {
229 : ABM_MASK_SH_LIST_DCN30(__SHIFT)
230 : };
231 :
232 : static const struct dce_abm_mask abm_mask = {
233 : ABM_MASK_SH_LIST_DCN30(_MASK)
234 : };
235 :
236 :
237 :
238 : #define audio_regs(id)\
239 : [id] = {\
240 : AUD_COMMON_REG_LIST(id)\
241 : }
242 :
243 : static const struct dce_audio_registers audio_regs[] = {
244 : audio_regs(0),
245 : audio_regs(1),
246 : audio_regs(2),
247 : audio_regs(3),
248 : audio_regs(4),
249 : audio_regs(5),
250 : audio_regs(6)
251 : };
252 :
253 : #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
254 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
255 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
256 : AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
257 :
258 : static const struct dce_audio_shift audio_shift = {
259 : DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
260 : };
261 :
262 : static const struct dce_audio_mask audio_mask = {
263 : DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
264 : };
265 :
266 : #define vpg_regs(id)\
267 : [id] = {\
268 : VPG_DCN3_REG_LIST(id)\
269 : }
270 :
271 : static const struct dcn30_vpg_registers vpg_regs[] = {
272 : vpg_regs(0),
273 : vpg_regs(1),
274 : vpg_regs(2),
275 : vpg_regs(3),
276 : vpg_regs(4),
277 : vpg_regs(5),
278 : vpg_regs(6),
279 : };
280 :
281 : static const struct dcn30_vpg_shift vpg_shift = {
282 : DCN3_VPG_MASK_SH_LIST(__SHIFT)
283 : };
284 :
285 : static const struct dcn30_vpg_mask vpg_mask = {
286 : DCN3_VPG_MASK_SH_LIST(_MASK)
287 : };
288 :
289 : #define afmt_regs(id)\
290 : [id] = {\
291 : AFMT_DCN3_REG_LIST(id)\
292 : }
293 :
294 : static const struct dcn30_afmt_registers afmt_regs[] = {
295 : afmt_regs(0),
296 : afmt_regs(1),
297 : afmt_regs(2),
298 : afmt_regs(3),
299 : afmt_regs(4),
300 : afmt_regs(5),
301 : afmt_regs(6),
302 : };
303 :
304 : static const struct dcn30_afmt_shift afmt_shift = {
305 : DCN3_AFMT_MASK_SH_LIST(__SHIFT)
306 : };
307 :
308 : static const struct dcn30_afmt_mask afmt_mask = {
309 : DCN3_AFMT_MASK_SH_LIST(_MASK)
310 : };
311 :
312 : #define stream_enc_regs(id)\
313 : [id] = {\
314 : SE_DCN3_REG_LIST(id)\
315 : }
316 :
317 : static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
318 : stream_enc_regs(0),
319 : stream_enc_regs(1),
320 : stream_enc_regs(2),
321 : stream_enc_regs(3),
322 : stream_enc_regs(4),
323 : stream_enc_regs(5)
324 : };
325 :
326 : static const struct dcn10_stream_encoder_shift se_shift = {
327 : SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
328 : };
329 :
330 : static const struct dcn10_stream_encoder_mask se_mask = {
331 : SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
332 : };
333 :
334 :
335 : #define aux_regs(id)\
336 : [id] = {\
337 : DCN2_AUX_REG_LIST(id)\
338 : }
339 :
340 : static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
341 : aux_regs(0),
342 : aux_regs(1),
343 : aux_regs(2),
344 : aux_regs(3),
345 : aux_regs(4),
346 : aux_regs(5)
347 : };
348 :
349 : #define hpd_regs(id)\
350 : [id] = {\
351 : HPD_REG_LIST(id)\
352 : }
353 :
354 : static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
355 : hpd_regs(0),
356 : hpd_regs(1),
357 : hpd_regs(2),
358 : hpd_regs(3),
359 : hpd_regs(4),
360 : hpd_regs(5)
361 : };
362 :
363 : #define link_regs(id, phyid)\
364 : [id] = {\
365 : LE_DCN3_REG_LIST(id), \
366 : UNIPHY_DCN2_REG_LIST(phyid), \
367 : DPCS_DCN2_REG_LIST(id), \
368 : SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
369 : }
370 :
371 : static const struct dce110_aux_registers_shift aux_shift = {
372 : DCN_AUX_MASK_SH_LIST(__SHIFT)
373 : };
374 :
375 : static const struct dce110_aux_registers_mask aux_mask = {
376 : DCN_AUX_MASK_SH_LIST(_MASK)
377 : };
378 :
379 : static const struct dcn10_link_enc_registers link_enc_regs[] = {
380 : link_regs(0, A),
381 : link_regs(1, B),
382 : link_regs(2, C),
383 : link_regs(3, D),
384 : link_regs(4, E),
385 : link_regs(5, F)
386 : };
387 :
388 : static const struct dcn10_link_enc_shift le_shift = {
389 : LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
390 : DPCS_DCN2_MASK_SH_LIST(__SHIFT)
391 : };
392 :
393 : static const struct dcn10_link_enc_mask le_mask = {
394 : LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
395 : DPCS_DCN2_MASK_SH_LIST(_MASK)
396 : };
397 :
398 :
399 : static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
400 : { DCN_PANEL_CNTL_REG_LIST() }
401 : };
402 :
403 : static const struct dce_panel_cntl_shift panel_cntl_shift = {
404 : DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
405 : };
406 :
407 : static const struct dce_panel_cntl_mask panel_cntl_mask = {
408 : DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
409 : };
410 :
411 : #define dpp_regs(id)\
412 : [id] = {\
413 : DPP_REG_LIST_DCN30(id),\
414 : }
415 :
416 : static const struct dcn3_dpp_registers dpp_regs[] = {
417 : dpp_regs(0),
418 : dpp_regs(1),
419 : dpp_regs(2),
420 : dpp_regs(3),
421 : dpp_regs(4),
422 : dpp_regs(5),
423 : };
424 :
425 : static const struct dcn3_dpp_shift tf_shift = {
426 : DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
427 : };
428 :
429 : static const struct dcn3_dpp_mask tf_mask = {
430 : DPP_REG_LIST_SH_MASK_DCN30(_MASK)
431 : };
432 :
433 : #define opp_regs(id)\
434 : [id] = {\
435 : OPP_REG_LIST_DCN30(id),\
436 : }
437 :
438 : static const struct dcn20_opp_registers opp_regs[] = {
439 : opp_regs(0),
440 : opp_regs(1),
441 : opp_regs(2),
442 : opp_regs(3),
443 : opp_regs(4),
444 : opp_regs(5)
445 : };
446 :
447 : static const struct dcn20_opp_shift opp_shift = {
448 : OPP_MASK_SH_LIST_DCN20(__SHIFT)
449 : };
450 :
451 : static const struct dcn20_opp_mask opp_mask = {
452 : OPP_MASK_SH_LIST_DCN20(_MASK)
453 : };
454 :
455 : #define aux_engine_regs(id)\
456 : [id] = {\
457 : AUX_COMMON_REG_LIST0(id), \
458 : .AUXN_IMPCAL = 0, \
459 : .AUXP_IMPCAL = 0, \
460 : .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
461 : }
462 :
463 : static const struct dce110_aux_registers aux_engine_regs[] = {
464 : aux_engine_regs(0),
465 : aux_engine_regs(1),
466 : aux_engine_regs(2),
467 : aux_engine_regs(3),
468 : aux_engine_regs(4),
469 : aux_engine_regs(5)
470 : };
471 :
472 : #define dwbc_regs_dcn3(id)\
473 : [id] = {\
474 : DWBC_COMMON_REG_LIST_DCN30(id),\
475 : }
476 :
477 : static const struct dcn30_dwbc_registers dwbc30_regs[] = {
478 : dwbc_regs_dcn3(0),
479 : };
480 :
481 : static const struct dcn30_dwbc_shift dwbc30_shift = {
482 : DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
483 : };
484 :
485 : static const struct dcn30_dwbc_mask dwbc30_mask = {
486 : DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
487 : };
488 :
489 : #define mcif_wb_regs_dcn3(id)\
490 : [id] = {\
491 : MCIF_WB_COMMON_REG_LIST_DCN30(id),\
492 : }
493 :
494 : static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
495 : mcif_wb_regs_dcn3(0)
496 : };
497 :
498 : static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
499 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
500 : };
501 :
502 : static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
503 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
504 : };
505 :
506 : #define dsc_regsDCN20(id)\
507 : [id] = {\
508 : DSC_REG_LIST_DCN20(id)\
509 : }
510 :
511 : static const struct dcn20_dsc_registers dsc_regs[] = {
512 : dsc_regsDCN20(0),
513 : dsc_regsDCN20(1),
514 : dsc_regsDCN20(2),
515 : dsc_regsDCN20(3),
516 : dsc_regsDCN20(4),
517 : dsc_regsDCN20(5)
518 : };
519 :
520 : static const struct dcn20_dsc_shift dsc_shift = {
521 : DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
522 : };
523 :
524 : static const struct dcn20_dsc_mask dsc_mask = {
525 : DSC_REG_LIST_SH_MASK_DCN20(_MASK)
526 : };
527 :
528 : static const struct dcn30_mpc_registers mpc_regs = {
529 : MPC_REG_LIST_DCN3_0(0),
530 : MPC_REG_LIST_DCN3_0(1),
531 : MPC_REG_LIST_DCN3_0(2),
532 : MPC_REG_LIST_DCN3_0(3),
533 : MPC_REG_LIST_DCN3_0(4),
534 : MPC_REG_LIST_DCN3_0(5),
535 : MPC_OUT_MUX_REG_LIST_DCN3_0(0),
536 : MPC_OUT_MUX_REG_LIST_DCN3_0(1),
537 : MPC_OUT_MUX_REG_LIST_DCN3_0(2),
538 : MPC_OUT_MUX_REG_LIST_DCN3_0(3),
539 : MPC_OUT_MUX_REG_LIST_DCN3_0(4),
540 : MPC_OUT_MUX_REG_LIST_DCN3_0(5),
541 : MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
542 : MPC_RMU_REG_LIST_DCN3AG(0),
543 : MPC_RMU_REG_LIST_DCN3AG(1),
544 : MPC_RMU_REG_LIST_DCN3AG(2),
545 : MPC_DWB_MUX_REG_LIST_DCN3_0(0),
546 : };
547 :
548 : static const struct dcn30_mpc_shift mpc_shift = {
549 : MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
550 : };
551 :
552 : static const struct dcn30_mpc_mask mpc_mask = {
553 : MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
554 : };
555 :
556 : #define optc_regs(id)\
557 : [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
558 :
559 :
560 : static const struct dcn_optc_registers optc_regs[] = {
561 : optc_regs(0),
562 : optc_regs(1),
563 : optc_regs(2),
564 : optc_regs(3),
565 : optc_regs(4),
566 : optc_regs(5)
567 : };
568 :
569 : static const struct dcn_optc_shift optc_shift = {
570 : OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
571 : };
572 :
573 : static const struct dcn_optc_mask optc_mask = {
574 : OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
575 : };
576 :
577 : #define hubp_regs(id)\
578 : [id] = {\
579 : HUBP_REG_LIST_DCN30(id)\
580 : }
581 :
582 : static const struct dcn_hubp2_registers hubp_regs[] = {
583 : hubp_regs(0),
584 : hubp_regs(1),
585 : hubp_regs(2),
586 : hubp_regs(3),
587 : hubp_regs(4),
588 : hubp_regs(5)
589 : };
590 :
591 : static const struct dcn_hubp2_shift hubp_shift = {
592 : HUBP_MASK_SH_LIST_DCN30(__SHIFT)
593 : };
594 :
595 : static const struct dcn_hubp2_mask hubp_mask = {
596 : HUBP_MASK_SH_LIST_DCN30(_MASK)
597 : };
598 :
599 : static const struct dcn_hubbub_registers hubbub_reg = {
600 : HUBBUB_REG_LIST_DCN30(0)
601 : };
602 :
603 : static const struct dcn_hubbub_shift hubbub_shift = {
604 : HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
605 : };
606 :
607 : static const struct dcn_hubbub_mask hubbub_mask = {
608 : HUBBUB_MASK_SH_LIST_DCN30(_MASK)
609 : };
610 :
611 : static const struct dccg_registers dccg_regs = {
612 : DCCG_REG_LIST_DCN30()
613 : };
614 :
615 : static const struct dccg_shift dccg_shift = {
616 : DCCG_MASK_SH_LIST_DCN3(__SHIFT)
617 : };
618 :
619 : static const struct dccg_mask dccg_mask = {
620 : DCCG_MASK_SH_LIST_DCN3(_MASK)
621 : };
622 :
623 : static const struct dce_hwseq_registers hwseq_reg = {
624 : HWSEQ_DCN30_REG_LIST()
625 : };
626 :
627 : static const struct dce_hwseq_shift hwseq_shift = {
628 : HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
629 : };
630 :
631 : static const struct dce_hwseq_mask hwseq_mask = {
632 : HWSEQ_DCN30_MASK_SH_LIST(_MASK)
633 : };
634 : #define vmid_regs(id)\
635 : [id] = {\
636 : DCN20_VMID_REG_LIST(id)\
637 : }
638 :
639 : static const struct dcn_vmid_registers vmid_regs[] = {
640 : vmid_regs(0),
641 : vmid_regs(1),
642 : vmid_regs(2),
643 : vmid_regs(3),
644 : vmid_regs(4),
645 : vmid_regs(5),
646 : vmid_regs(6),
647 : vmid_regs(7),
648 : vmid_regs(8),
649 : vmid_regs(9),
650 : vmid_regs(10),
651 : vmid_regs(11),
652 : vmid_regs(12),
653 : vmid_regs(13),
654 : vmid_regs(14),
655 : vmid_regs(15)
656 : };
657 :
658 : static const struct dcn20_vmid_shift vmid_shifts = {
659 : DCN20_VMID_MASK_SH_LIST(__SHIFT)
660 : };
661 :
662 : static const struct dcn20_vmid_mask vmid_masks = {
663 : DCN20_VMID_MASK_SH_LIST(_MASK)
664 : };
665 :
666 : static const struct resource_caps res_cap_dcn3 = {
667 : .num_timing_generator = 6,
668 : .num_opp = 6,
669 : .num_video_plane = 6,
670 : .num_audio = 6,
671 : .num_stream_encoder = 6,
672 : .num_pll = 6,
673 : .num_dwb = 1,
674 : .num_ddc = 6,
675 : .num_vmid = 16,
676 : .num_mpc_3dlut = 3,
677 : .num_dsc = 6,
678 : };
679 :
680 : static const struct dc_plane_cap plane_cap = {
681 : .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
682 : .blends_with_above = true,
683 : .blends_with_below = true,
684 : .per_pixel_alpha = true,
685 :
686 : .pixel_format_support = {
687 : .argb8888 = true,
688 : .nv12 = true,
689 : .fp16 = true,
690 : .p010 = true,
691 : .ayuv = false,
692 : },
693 :
694 : .max_upscale_factor = {
695 : .argb8888 = 16000,
696 : .nv12 = 16000,
697 : .fp16 = 16000
698 : },
699 :
700 : /* 6:1 downscaling ratio: 1000/6 = 166.666 */
701 : .max_downscale_factor = {
702 : .argb8888 = 167,
703 : .nv12 = 167,
704 : .fp16 = 167
705 : }
706 : };
707 :
708 : static const struct dc_debug_options debug_defaults_drv = {
709 : .disable_dmcu = true, //No DMCU on DCN30
710 : .force_abm_enable = false,
711 : .timing_trace = false,
712 : .clock_trace = true,
713 : .disable_pplib_clock_request = true,
714 : .pipe_split_policy = MPC_SPLIT_DYNAMIC,
715 : .force_single_disp_pipe_split = false,
716 : .disable_dcc = DCC_ENABLE,
717 : .vsr_support = true,
718 : .performance_trace = false,
719 : .max_downscale_src_width = 7680,/*upto 8K*/
720 : .disable_pplib_wm_range = false,
721 : .scl_reset_length10 = true,
722 : .sanity_checks = false,
723 : .underflow_assert_delay_us = 0xFFFFFFFF,
724 : .dwb_fi_phase = -1, // -1 = disable,
725 : .dmub_command_table = true,
726 : .disable_psr = false,
727 : .use_max_lb = true
728 : };
729 :
730 : static const struct dc_debug_options debug_defaults_diags = {
731 : .disable_dmcu = true, //No dmcu on DCN30
732 : .force_abm_enable = false,
733 : .timing_trace = true,
734 : .clock_trace = true,
735 : .disable_dpp_power_gate = true,
736 : .disable_hubp_power_gate = true,
737 : .disable_clock_gate = true,
738 : .disable_pplib_clock_request = true,
739 : .disable_pplib_wm_range = true,
740 : .disable_stutter = false,
741 : .scl_reset_length10 = true,
742 : .dwb_fi_phase = -1, // -1 = disable
743 : .dmub_command_table = true,
744 : .disable_psr = true,
745 : .enable_tri_buf = true,
746 : .use_max_lb = true
747 : };
748 :
749 : static void dcn30_dpp_destroy(struct dpp **dpp)
750 : {
751 0 : kfree(TO_DCN20_DPP(*dpp));
752 0 : *dpp = NULL;
753 : }
754 :
755 0 : static struct dpp *dcn30_dpp_create(
756 : struct dc_context *ctx,
757 : uint32_t inst)
758 : {
759 0 : struct dcn3_dpp *dpp =
760 : kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
761 :
762 0 : if (!dpp)
763 : return NULL;
764 :
765 0 : if (dpp3_construct(dpp, ctx, inst,
766 : &dpp_regs[inst], &tf_shift, &tf_mask))
767 0 : return &dpp->base;
768 :
769 0 : BREAK_TO_DEBUGGER();
770 0 : kfree(dpp);
771 0 : return NULL;
772 : }
773 :
774 0 : static struct output_pixel_processor *dcn30_opp_create(
775 : struct dc_context *ctx, uint32_t inst)
776 : {
777 0 : struct dcn20_opp *opp =
778 : kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
779 :
780 0 : if (!opp) {
781 0 : BREAK_TO_DEBUGGER();
782 0 : return NULL;
783 : }
784 :
785 0 : dcn20_opp_construct(opp, ctx, inst,
786 : &opp_regs[inst], &opp_shift, &opp_mask);
787 0 : return &opp->base;
788 : }
789 :
790 0 : static struct dce_aux *dcn30_aux_engine_create(
791 : struct dc_context *ctx,
792 : uint32_t inst)
793 : {
794 0 : struct aux_engine_dce110 *aux_engine =
795 : kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
796 :
797 0 : if (!aux_engine)
798 : return NULL;
799 :
800 0 : dce110_aux_engine_construct(aux_engine, ctx, inst,
801 : SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
802 : &aux_engine_regs[inst],
803 : &aux_mask,
804 : &aux_shift,
805 0 : ctx->dc->caps.extended_aux_timeout_support);
806 :
807 0 : return &aux_engine->base;
808 : }
809 :
810 : #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
811 :
812 : static const struct dce_i2c_registers i2c_hw_regs[] = {
813 : i2c_inst_regs(1),
814 : i2c_inst_regs(2),
815 : i2c_inst_regs(3),
816 : i2c_inst_regs(4),
817 : i2c_inst_regs(5),
818 : i2c_inst_regs(6),
819 : };
820 :
821 : static const struct dce_i2c_shift i2c_shifts = {
822 : I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
823 : };
824 :
825 : static const struct dce_i2c_mask i2c_masks = {
826 : I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
827 : };
828 :
829 0 : static struct dce_i2c_hw *dcn30_i2c_hw_create(
830 : struct dc_context *ctx,
831 : uint32_t inst)
832 : {
833 0 : struct dce_i2c_hw *dce_i2c_hw =
834 : kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
835 :
836 0 : if (!dce_i2c_hw)
837 : return NULL;
838 :
839 0 : dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
840 : &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
841 :
842 0 : return dce_i2c_hw;
843 : }
844 :
845 0 : static struct mpc *dcn30_mpc_create(
846 : struct dc_context *ctx,
847 : int num_mpcc,
848 : int num_rmu)
849 : {
850 0 : struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
851 : GFP_KERNEL);
852 :
853 0 : if (!mpc30)
854 : return NULL;
855 :
856 0 : dcn30_mpc_construct(mpc30, ctx,
857 : &mpc_regs,
858 : &mpc_shift,
859 : &mpc_mask,
860 : num_mpcc,
861 : num_rmu);
862 :
863 0 : return &mpc30->base;
864 : }
865 :
866 0 : static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
867 : {
868 : int i;
869 :
870 0 : struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
871 : GFP_KERNEL);
872 :
873 0 : if (!hubbub3)
874 : return NULL;
875 :
876 0 : hubbub3_construct(hubbub3, ctx,
877 : &hubbub_reg,
878 : &hubbub_shift,
879 : &hubbub_mask);
880 :
881 :
882 0 : for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
883 0 : struct dcn20_vmid *vmid = &hubbub3->vmid[i];
884 :
885 0 : vmid->ctx = ctx;
886 :
887 0 : vmid->regs = &vmid_regs[i];
888 0 : vmid->shifts = &vmid_shifts;
889 0 : vmid->masks = &vmid_masks;
890 : }
891 :
892 0 : return &hubbub3->base;
893 : }
894 :
895 0 : static struct timing_generator *dcn30_timing_generator_create(
896 : struct dc_context *ctx,
897 : uint32_t instance)
898 : {
899 0 : struct optc *tgn10 =
900 : kzalloc(sizeof(struct optc), GFP_KERNEL);
901 :
902 0 : if (!tgn10)
903 : return NULL;
904 :
905 0 : tgn10->base.inst = instance;
906 0 : tgn10->base.ctx = ctx;
907 :
908 0 : tgn10->tg_regs = &optc_regs[instance];
909 0 : tgn10->tg_shift = &optc_shift;
910 0 : tgn10->tg_mask = &optc_mask;
911 :
912 0 : dcn30_timing_generator_init(tgn10);
913 :
914 0 : return &tgn10->base;
915 : }
916 :
917 : static const struct encoder_feature_support link_enc_feature = {
918 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
919 : .max_hdmi_pixel_clock = 600000,
920 : .hdmi_ycbcr420_supported = true,
921 : .dp_ycbcr420_supported = true,
922 : .fec_supported = true,
923 : .flags.bits.IS_HBR2_CAPABLE = true,
924 : .flags.bits.IS_HBR3_CAPABLE = true,
925 : .flags.bits.IS_TPS3_CAPABLE = true,
926 : .flags.bits.IS_TPS4_CAPABLE = true
927 : };
928 :
929 0 : static struct link_encoder *dcn30_link_encoder_create(
930 : struct dc_context *ctx,
931 : const struct encoder_init_data *enc_init_data)
932 : {
933 0 : struct dcn20_link_encoder *enc20 =
934 : kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
935 :
936 0 : if (!enc20)
937 : return NULL;
938 :
939 0 : dcn30_link_encoder_construct(enc20,
940 : enc_init_data,
941 : &link_enc_feature,
942 0 : &link_enc_regs[enc_init_data->transmitter],
943 0 : &link_enc_aux_regs[enc_init_data->channel - 1],
944 0 : &link_enc_hpd_regs[enc_init_data->hpd_source],
945 : &le_shift,
946 : &le_mask);
947 :
948 0 : return &enc20->enc10.base;
949 : }
950 :
951 0 : static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
952 : {
953 0 : struct dce_panel_cntl *panel_cntl =
954 : kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
955 :
956 0 : if (!panel_cntl)
957 : return NULL;
958 :
959 0 : dce_panel_cntl_construct(panel_cntl,
960 : init_data,
961 0 : &panel_cntl_regs[init_data->inst],
962 : &panel_cntl_shift,
963 : &panel_cntl_mask);
964 :
965 0 : return &panel_cntl->base;
966 : }
967 :
968 0 : static void read_dce_straps(
969 : struct dc_context *ctx,
970 : struct resource_straps *straps)
971 : {
972 0 : generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
973 : FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
974 :
975 0 : }
976 :
977 0 : static struct audio *dcn30_create_audio(
978 : struct dc_context *ctx, unsigned int inst)
979 : {
980 0 : return dce_audio_create(ctx, inst,
981 : &audio_regs[inst], &audio_shift, &audio_mask);
982 : }
983 :
984 0 : static struct vpg *dcn30_vpg_create(
985 : struct dc_context *ctx,
986 : uint32_t inst)
987 : {
988 0 : struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
989 :
990 0 : if (!vpg3)
991 : return NULL;
992 :
993 0 : vpg3_construct(vpg3, ctx, inst,
994 : &vpg_regs[inst],
995 : &vpg_shift,
996 : &vpg_mask);
997 :
998 0 : return &vpg3->base;
999 : }
1000 :
1001 0 : static struct afmt *dcn30_afmt_create(
1002 : struct dc_context *ctx,
1003 : uint32_t inst)
1004 : {
1005 0 : struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1006 :
1007 0 : if (!afmt3)
1008 : return NULL;
1009 :
1010 0 : afmt3_construct(afmt3, ctx, inst,
1011 : &afmt_regs[inst],
1012 : &afmt_shift,
1013 : &afmt_mask);
1014 :
1015 0 : return &afmt3->base;
1016 : }
1017 :
1018 0 : static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1019 : struct dc_context *ctx)
1020 : {
1021 : struct dcn10_stream_encoder *enc1;
1022 : struct vpg *vpg;
1023 : struct afmt *afmt;
1024 : int vpg_inst;
1025 : int afmt_inst;
1026 :
1027 : /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1028 0 : if (eng_id <= ENGINE_ID_DIGF) {
1029 0 : vpg_inst = eng_id;
1030 0 : afmt_inst = eng_id;
1031 : } else
1032 : return NULL;
1033 :
1034 0 : enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1035 0 : vpg = dcn30_vpg_create(ctx, vpg_inst);
1036 0 : afmt = dcn30_afmt_create(ctx, afmt_inst);
1037 :
1038 0 : if (!enc1 || !vpg || !afmt) {
1039 0 : kfree(enc1);
1040 0 : kfree(vpg);
1041 0 : kfree(afmt);
1042 0 : return NULL;
1043 : }
1044 :
1045 0 : dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1046 : eng_id, vpg, afmt,
1047 : &stream_enc_regs[eng_id],
1048 : &se_shift, &se_mask);
1049 :
1050 0 : return &enc1->base;
1051 : }
1052 :
1053 0 : static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1054 : {
1055 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1056 :
1057 0 : if (hws) {
1058 0 : hws->ctx = ctx;
1059 0 : hws->regs = &hwseq_reg;
1060 0 : hws->shifts = &hwseq_shift;
1061 0 : hws->masks = &hwseq_mask;
1062 : }
1063 0 : return hws;
1064 : }
1065 : static const struct resource_create_funcs res_create_funcs = {
1066 : .read_dce_straps = read_dce_straps,
1067 : .create_audio = dcn30_create_audio,
1068 : .create_stream_encoder = dcn30_stream_encoder_create,
1069 : .create_hwseq = dcn30_hwseq_create,
1070 : };
1071 :
1072 : static const struct resource_create_funcs res_create_maximus_funcs = {
1073 : .read_dce_straps = NULL,
1074 : .create_audio = NULL,
1075 : .create_stream_encoder = NULL,
1076 : .create_hwseq = dcn30_hwseq_create,
1077 : };
1078 :
1079 0 : static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1080 : {
1081 : unsigned int i;
1082 :
1083 0 : for (i = 0; i < pool->base.stream_enc_count; i++) {
1084 0 : if (pool->base.stream_enc[i] != NULL) {
1085 0 : if (pool->base.stream_enc[i]->vpg != NULL) {
1086 0 : kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1087 0 : pool->base.stream_enc[i]->vpg = NULL;
1088 : }
1089 0 : if (pool->base.stream_enc[i]->afmt != NULL) {
1090 0 : kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1091 0 : pool->base.stream_enc[i]->afmt = NULL;
1092 : }
1093 0 : kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1094 0 : pool->base.stream_enc[i] = NULL;
1095 : }
1096 : }
1097 :
1098 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1099 0 : if (pool->base.dscs[i] != NULL)
1100 0 : dcn20_dsc_destroy(&pool->base.dscs[i]);
1101 : }
1102 :
1103 0 : if (pool->base.mpc != NULL) {
1104 0 : kfree(TO_DCN20_MPC(pool->base.mpc));
1105 0 : pool->base.mpc = NULL;
1106 : }
1107 0 : if (pool->base.hubbub != NULL) {
1108 0 : kfree(pool->base.hubbub);
1109 0 : pool->base.hubbub = NULL;
1110 : }
1111 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1112 0 : if (pool->base.dpps[i] != NULL)
1113 0 : dcn30_dpp_destroy(&pool->base.dpps[i]);
1114 :
1115 0 : if (pool->base.ipps[i] != NULL)
1116 0 : pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1117 :
1118 0 : if (pool->base.hubps[i] != NULL) {
1119 0 : kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1120 0 : pool->base.hubps[i] = NULL;
1121 : }
1122 :
1123 0 : if (pool->base.irqs != NULL) {
1124 0 : dal_irq_service_destroy(&pool->base.irqs);
1125 : }
1126 : }
1127 :
1128 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1129 0 : if (pool->base.engines[i] != NULL)
1130 0 : dce110_engine_destroy(&pool->base.engines[i]);
1131 0 : if (pool->base.hw_i2cs[i] != NULL) {
1132 0 : kfree(pool->base.hw_i2cs[i]);
1133 0 : pool->base.hw_i2cs[i] = NULL;
1134 : }
1135 0 : if (pool->base.sw_i2cs[i] != NULL) {
1136 0 : kfree(pool->base.sw_i2cs[i]);
1137 0 : pool->base.sw_i2cs[i] = NULL;
1138 : }
1139 : }
1140 :
1141 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1142 0 : if (pool->base.opps[i] != NULL)
1143 0 : pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1144 : }
1145 :
1146 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1147 0 : if (pool->base.timing_generators[i] != NULL) {
1148 0 : kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1149 0 : pool->base.timing_generators[i] = NULL;
1150 : }
1151 : }
1152 :
1153 0 : for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1154 0 : if (pool->base.dwbc[i] != NULL) {
1155 0 : kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1156 0 : pool->base.dwbc[i] = NULL;
1157 : }
1158 0 : if (pool->base.mcif_wb[i] != NULL) {
1159 0 : kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1160 0 : pool->base.mcif_wb[i] = NULL;
1161 : }
1162 : }
1163 :
1164 0 : for (i = 0; i < pool->base.audio_count; i++) {
1165 0 : if (pool->base.audios[i])
1166 0 : dce_aud_destroy(&pool->base.audios[i]);
1167 : }
1168 :
1169 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1170 0 : if (pool->base.clock_sources[i] != NULL) {
1171 0 : dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1172 0 : pool->base.clock_sources[i] = NULL;
1173 : }
1174 : }
1175 :
1176 0 : for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1177 0 : if (pool->base.mpc_lut[i] != NULL) {
1178 0 : dc_3dlut_func_release(pool->base.mpc_lut[i]);
1179 0 : pool->base.mpc_lut[i] = NULL;
1180 : }
1181 0 : if (pool->base.mpc_shaper[i] != NULL) {
1182 0 : dc_transfer_func_release(pool->base.mpc_shaper[i]);
1183 0 : pool->base.mpc_shaper[i] = NULL;
1184 : }
1185 : }
1186 :
1187 0 : if (pool->base.dp_clock_source != NULL) {
1188 0 : dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1189 0 : pool->base.dp_clock_source = NULL;
1190 : }
1191 :
1192 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1193 0 : if (pool->base.multiple_abms[i] != NULL)
1194 0 : dce_abm_destroy(&pool->base.multiple_abms[i]);
1195 : }
1196 :
1197 0 : if (pool->base.psr != NULL)
1198 0 : dmub_psr_destroy(&pool->base.psr);
1199 :
1200 0 : if (pool->base.dccg != NULL)
1201 0 : dcn_dccg_destroy(&pool->base.dccg);
1202 :
1203 0 : if (pool->base.oem_device != NULL)
1204 0 : dal_ddc_service_destroy(&pool->base.oem_device);
1205 0 : }
1206 :
1207 0 : static struct hubp *dcn30_hubp_create(
1208 : struct dc_context *ctx,
1209 : uint32_t inst)
1210 : {
1211 0 : struct dcn20_hubp *hubp2 =
1212 : kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1213 :
1214 0 : if (!hubp2)
1215 : return NULL;
1216 :
1217 0 : if (hubp3_construct(hubp2, ctx, inst,
1218 : &hubp_regs[inst], &hubp_shift, &hubp_mask))
1219 0 : return &hubp2->base;
1220 :
1221 0 : BREAK_TO_DEBUGGER();
1222 0 : kfree(hubp2);
1223 0 : return NULL;
1224 : }
1225 :
1226 0 : static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1227 : {
1228 : int i;
1229 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
1230 :
1231 0 : for (i = 0; i < pipe_count; i++) {
1232 0 : struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1233 : GFP_KERNEL);
1234 :
1235 0 : if (!dwbc30) {
1236 0 : dm_error("DC: failed to create dwbc30!\n");
1237 : return false;
1238 : }
1239 :
1240 0 : dcn30_dwbc_construct(dwbc30, ctx,
1241 : &dwbc30_regs[i],
1242 : &dwbc30_shift,
1243 : &dwbc30_mask,
1244 : i);
1245 :
1246 0 : pool->dwbc[i] = &dwbc30->base;
1247 : }
1248 : return true;
1249 : }
1250 :
1251 0 : static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1252 : {
1253 : int i;
1254 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
1255 :
1256 0 : for (i = 0; i < pipe_count; i++) {
1257 0 : struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1258 : GFP_KERNEL);
1259 :
1260 0 : if (!mcif_wb30) {
1261 0 : dm_error("DC: failed to create mcif_wb30!\n");
1262 : return false;
1263 : }
1264 :
1265 0 : dcn30_mmhubbub_construct(mcif_wb30, ctx,
1266 : &mcif_wb30_regs[i],
1267 : &mcif_wb30_shift,
1268 : &mcif_wb30_mask,
1269 : i);
1270 :
1271 0 : pool->mcif_wb[i] = &mcif_wb30->base;
1272 : }
1273 : return true;
1274 : }
1275 :
1276 0 : static struct display_stream_compressor *dcn30_dsc_create(
1277 : struct dc_context *ctx, uint32_t inst)
1278 : {
1279 0 : struct dcn20_dsc *dsc =
1280 : kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1281 :
1282 0 : if (!dsc) {
1283 0 : BREAK_TO_DEBUGGER();
1284 0 : return NULL;
1285 : }
1286 :
1287 0 : dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1288 0 : return &dsc->base;
1289 : }
1290 :
1291 0 : enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1292 : {
1293 :
1294 0 : return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1295 : }
1296 :
1297 0 : static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1298 : {
1299 0 : struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1300 :
1301 0 : dcn30_resource_destruct(dcn30_pool);
1302 0 : kfree(dcn30_pool);
1303 0 : *pool = NULL;
1304 0 : }
1305 :
1306 0 : static struct clock_source *dcn30_clock_source_create(
1307 : struct dc_context *ctx,
1308 : struct dc_bios *bios,
1309 : enum clock_source_id id,
1310 : const struct dce110_clk_src_regs *regs,
1311 : bool dp_clk_src)
1312 : {
1313 0 : struct dce110_clk_src *clk_src =
1314 : kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1315 :
1316 0 : if (!clk_src)
1317 : return NULL;
1318 :
1319 0 : if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1320 : regs, &cs_shift, &cs_mask)) {
1321 0 : clk_src->base.dp_clk_src = dp_clk_src;
1322 0 : return &clk_src->base;
1323 : }
1324 :
1325 0 : BREAK_TO_DEBUGGER();
1326 0 : return NULL;
1327 : }
1328 :
1329 0 : int dcn30_populate_dml_pipes_from_context(
1330 : struct dc *dc, struct dc_state *context,
1331 : display_e2e_pipe_params_st *pipes,
1332 : bool fast_validate)
1333 : {
1334 : int i, pipe_cnt;
1335 0 : struct resource_context *res_ctx = &context->res_ctx;
1336 :
1337 0 : DC_FP_START();
1338 0 : dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1339 0 : DC_FP_END();
1340 :
1341 0 : for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1342 0 : if (!res_ctx->pipe_ctx[i].stream)
1343 0 : continue;
1344 :
1345 0 : pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1346 : dm_lb_16;
1347 : }
1348 :
1349 0 : return pipe_cnt;
1350 : }
1351 :
1352 0 : void dcn30_populate_dml_writeback_from_context(
1353 : struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1354 : {
1355 0 : DC_FP_START();
1356 0 : dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1357 0 : DC_FP_END();
1358 0 : }
1359 :
1360 0 : unsigned int dcn30_calc_max_scaled_time(
1361 : unsigned int time_per_pixel,
1362 : enum mmhubbub_wbif_mode mode,
1363 : unsigned int urgent_watermark)
1364 : {
1365 0 : unsigned int time_per_byte = 0;
1366 0 : unsigned int total_free_entry = 0xb40;
1367 : unsigned int buf_lh_capability;
1368 : unsigned int max_scaled_time;
1369 :
1370 0 : if (mode == PACKED_444) /* packed mode 32 bpp */
1371 0 : time_per_byte = time_per_pixel/4;
1372 0 : else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1373 0 : time_per_byte = time_per_pixel/8;
1374 :
1375 0 : if (time_per_byte == 0)
1376 0 : time_per_byte = 1;
1377 :
1378 0 : buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1379 0 : max_scaled_time = buf_lh_capability - urgent_watermark;
1380 0 : return max_scaled_time;
1381 : }
1382 :
1383 0 : void dcn30_set_mcif_arb_params(
1384 : struct dc *dc,
1385 : struct dc_state *context,
1386 : display_e2e_pipe_params_st *pipes,
1387 : int pipe_cnt)
1388 : {
1389 : enum mmhubbub_wbif_mode wbif_mode;
1390 0 : struct display_mode_lib *dml = &context->bw_ctx.dml;
1391 : struct mcif_arb_params *wb_arb_params;
1392 : int i, j, dwb_pipe;
1393 :
1394 : /* Writeback MCIF_WB arbitration parameters */
1395 0 : dwb_pipe = 0;
1396 0 : for (i = 0; i < dc->res_pool->pipe_count; i++) {
1397 :
1398 0 : if (!context->res_ctx.pipe_ctx[i].stream)
1399 0 : continue;
1400 :
1401 0 : for (j = 0; j < MAX_DWB_PIPES; j++) {
1402 0 : struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1403 :
1404 0 : if (writeback_info->wb_enabled == false)
1405 0 : continue;
1406 :
1407 : //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1408 0 : wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1409 :
1410 0 : if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1411 : writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1412 : wbif_mode = PACKED_444_FP16;
1413 : else
1414 0 : wbif_mode = PACKED_444;
1415 :
1416 0 : DC_FP_START();
1417 0 : dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1418 0 : DC_FP_END();
1419 0 : wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1420 0 : wb_arb_params->slice_lines = 32;
1421 0 : wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1422 0 : wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1423 : wbif_mode,
1424 : wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1425 :
1426 0 : dwb_pipe++;
1427 :
1428 : if (dwb_pipe >= MAX_DWB_PIPES)
1429 : return;
1430 : }
1431 : if (dwb_pipe >= MAX_DWB_PIPES)
1432 : return;
1433 : }
1434 :
1435 : }
1436 :
1437 : static struct dc_cap_funcs cap_funcs = {
1438 : .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1439 : };
1440 :
1441 0 : bool dcn30_acquire_post_bldn_3dlut(
1442 : struct resource_context *res_ctx,
1443 : const struct resource_pool *pool,
1444 : int mpcc_id,
1445 : struct dc_3dlut **lut,
1446 : struct dc_transfer_func **shaper)
1447 : {
1448 : int i;
1449 0 : bool ret = false;
1450 : union dc_3dlut_state *state;
1451 :
1452 0 : ASSERT(*lut == NULL && *shaper == NULL);
1453 0 : *lut = NULL;
1454 0 : *shaper = NULL;
1455 :
1456 0 : for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1457 0 : if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1458 0 : *lut = pool->mpc_lut[i];
1459 0 : *shaper = pool->mpc_shaper[i];
1460 0 : state = &pool->mpc_lut[i]->state;
1461 0 : res_ctx->is_mpc_3dlut_acquired[i] = true;
1462 0 : state->bits.rmu_idx_valid = 1;
1463 0 : state->bits.rmu_mux_num = i;
1464 0 : if (state->bits.rmu_mux_num == 0)
1465 0 : state->bits.mpc_rmu0_mux = mpcc_id;
1466 0 : else if (state->bits.rmu_mux_num == 1)
1467 0 : state->bits.mpc_rmu1_mux = mpcc_id;
1468 0 : else if (state->bits.rmu_mux_num == 2)
1469 0 : state->bits.mpc_rmu2_mux = mpcc_id;
1470 : ret = true;
1471 : break;
1472 : }
1473 : }
1474 0 : return ret;
1475 : }
1476 :
1477 0 : bool dcn30_release_post_bldn_3dlut(
1478 : struct resource_context *res_ctx,
1479 : const struct resource_pool *pool,
1480 : struct dc_3dlut **lut,
1481 : struct dc_transfer_func **shaper)
1482 : {
1483 : int i;
1484 0 : bool ret = false;
1485 :
1486 0 : for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1487 0 : if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1488 0 : res_ctx->is_mpc_3dlut_acquired[i] = false;
1489 0 : pool->mpc_lut[i]->state.raw = 0;
1490 0 : *lut = NULL;
1491 0 : *shaper = NULL;
1492 0 : ret = true;
1493 0 : break;
1494 : }
1495 : }
1496 0 : return ret;
1497 : }
1498 :
1499 : static bool is_soc_bounding_box_valid(struct dc *dc)
1500 : {
1501 0 : uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1502 :
1503 0 : if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1504 : return true;
1505 :
1506 : return false;
1507 : }
1508 :
1509 0 : static bool init_soc_bounding_box(struct dc *dc,
1510 : struct dcn30_resource_pool *pool)
1511 : {
1512 0 : struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1513 0 : struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1514 :
1515 : DC_LOGGER_INIT(dc->ctx->logger);
1516 :
1517 0 : if (!is_soc_bounding_box_valid(dc)) {
1518 0 : DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1519 : return false;
1520 : }
1521 :
1522 0 : loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1523 0 : loaded_ip->max_num_dpp = pool->base.pipe_count;
1524 0 : loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1525 0 : dcn20_patch_bounding_box(dc, loaded_bb);
1526 0 : DC_FP_START();
1527 0 : patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1528 0 : DC_FP_END();
1529 :
1530 : return true;
1531 : }
1532 :
1533 0 : static bool dcn30_split_stream_for_mpc_or_odm(
1534 : const struct dc *dc,
1535 : struct resource_context *res_ctx,
1536 : struct pipe_ctx *pri_pipe,
1537 : struct pipe_ctx *sec_pipe,
1538 : bool odm)
1539 : {
1540 0 : int pipe_idx = sec_pipe->pipe_idx;
1541 0 : const struct resource_pool *pool = dc->res_pool;
1542 :
1543 0 : *sec_pipe = *pri_pipe;
1544 :
1545 0 : sec_pipe->pipe_idx = pipe_idx;
1546 0 : sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1547 0 : sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1548 0 : sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1549 0 : sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1550 0 : sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1551 0 : sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1552 0 : sec_pipe->stream_res.dsc = NULL;
1553 0 : if (odm) {
1554 0 : if (pri_pipe->next_odm_pipe) {
1555 0 : ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1556 0 : sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1557 0 : sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1558 : }
1559 0 : if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1560 0 : pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1561 0 : sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1562 : }
1563 0 : if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1564 0 : pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1565 0 : sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1566 : }
1567 0 : pri_pipe->next_odm_pipe = sec_pipe;
1568 0 : sec_pipe->prev_odm_pipe = pri_pipe;
1569 :
1570 0 : if (!sec_pipe->top_pipe)
1571 0 : sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1572 : else
1573 0 : sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1574 0 : if (sec_pipe->stream->timing.flags.DSC == 1) {
1575 0 : dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1576 0 : ASSERT(sec_pipe->stream_res.dsc);
1577 0 : if (sec_pipe->stream_res.dsc == NULL)
1578 : return false;
1579 : }
1580 : } else {
1581 0 : if (pri_pipe->bottom_pipe) {
1582 0 : ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1583 0 : sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1584 0 : sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1585 : }
1586 0 : pri_pipe->bottom_pipe = sec_pipe;
1587 0 : sec_pipe->top_pipe = pri_pipe;
1588 :
1589 0 : ASSERT(pri_pipe->plane_state);
1590 : }
1591 :
1592 : return true;
1593 : }
1594 :
1595 0 : static struct pipe_ctx *dcn30_find_split_pipe(
1596 : struct dc *dc,
1597 : struct dc_state *context,
1598 : int old_index)
1599 : {
1600 0 : struct pipe_ctx *pipe = NULL;
1601 : int i;
1602 :
1603 0 : if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1604 0 : pipe = &context->res_ctx.pipe_ctx[old_index];
1605 0 : pipe->pipe_idx = old_index;
1606 : }
1607 :
1608 0 : if (!pipe)
1609 0 : for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1610 0 : if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1611 0 : && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1612 0 : if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1613 0 : pipe = &context->res_ctx.pipe_ctx[i];
1614 0 : pipe->pipe_idx = i;
1615 : break;
1616 : }
1617 : }
1618 : }
1619 :
1620 : /*
1621 : * May need to fix pipes getting tossed from 1 opp to another on flip
1622 : * Add for debugging transient underflow during topology updates:
1623 : * ASSERT(pipe);
1624 : */
1625 0 : if (!pipe)
1626 0 : for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1627 0 : if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1628 0 : pipe = &context->res_ctx.pipe_ctx[i];
1629 0 : pipe->pipe_idx = i;
1630 : break;
1631 : }
1632 : }
1633 :
1634 0 : return pipe;
1635 : }
1636 :
1637 0 : noinline bool dcn30_internal_validate_bw(
1638 : struct dc *dc,
1639 : struct dc_state *context,
1640 : display_e2e_pipe_params_st *pipes,
1641 : int *pipe_cnt_out,
1642 : int *vlevel_out,
1643 : bool fast_validate)
1644 : {
1645 0 : bool out = false;
1646 0 : bool repopulate_pipes = false;
1647 0 : int split[MAX_PIPES] = { 0 };
1648 0 : bool merge[MAX_PIPES] = { false };
1649 0 : bool newly_split[MAX_PIPES] = { false };
1650 : int pipe_cnt, i, pipe_idx, vlevel;
1651 0 : struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1652 :
1653 0 : ASSERT(pipes);
1654 0 : if (!pipes)
1655 : return false;
1656 :
1657 0 : dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1658 0 : pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1659 :
1660 0 : if (!pipe_cnt) {
1661 : out = true;
1662 : goto validate_out;
1663 : }
1664 :
1665 0 : dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1666 :
1667 0 : if (!fast_validate) {
1668 : /*
1669 : * DML favors voltage over p-state, but we're more interested in
1670 : * supporting p-state over voltage. We can't support p-state in
1671 : * prefetch mode > 0 so try capping the prefetch mode to start.
1672 : */
1673 0 : context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1674 : dm_allow_self_refresh_and_mclk_switch;
1675 0 : vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1676 : /* This may adjust vlevel and maxMpcComb */
1677 0 : if (vlevel < context->bw_ctx.dml.soc.num_states)
1678 0 : vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1679 : }
1680 0 : if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1681 0 : vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1682 : /*
1683 : * If mode is unsupported or there's still no p-state support then
1684 : * fall back to favoring voltage.
1685 : *
1686 : * We don't actually support prefetch mode 2, so require that we
1687 : * at least support prefetch mode 1.
1688 : */
1689 0 : context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1690 : dm_allow_self_refresh;
1691 :
1692 0 : vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1693 0 : if (vlevel < context->bw_ctx.dml.soc.num_states) {
1694 0 : memset(split, 0, sizeof(split));
1695 0 : memset(merge, 0, sizeof(merge));
1696 0 : vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1697 : }
1698 : }
1699 :
1700 0 : dml_log_mode_support_params(&context->bw_ctx.dml);
1701 :
1702 0 : if (vlevel == context->bw_ctx.dml.soc.num_states)
1703 : goto validate_fail;
1704 :
1705 0 : if (!dc->config.enable_windowed_mpo_odm) {
1706 0 : for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1707 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1708 0 : struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1709 :
1710 0 : if (!pipe->stream)
1711 0 : continue;
1712 :
1713 : /* We only support full screen mpo with ODM */
1714 0 : if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1715 0 : && pipe->plane_state && mpo_pipe
1716 0 : && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1717 0 : &pipe->plane_res.scl_data.recout,
1718 : sizeof(struct rect)) != 0) {
1719 0 : ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1720 : goto validate_fail;
1721 : }
1722 0 : pipe_idx++;
1723 : }
1724 : }
1725 :
1726 : /* merge pipes if necessary */
1727 0 : for (i = 0; i < dc->res_pool->pipe_count; i++) {
1728 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1729 :
1730 : /*skip pipes that don't need merging*/
1731 0 : if (!merge[i])
1732 0 : continue;
1733 :
1734 : /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1735 0 : if (pipe->prev_odm_pipe) {
1736 : /*split off odm pipe*/
1737 0 : pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1738 0 : if (pipe->next_odm_pipe)
1739 0 : pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1740 :
1741 0 : pipe->bottom_pipe = NULL;
1742 0 : pipe->next_odm_pipe = NULL;
1743 0 : pipe->plane_state = NULL;
1744 0 : pipe->stream = NULL;
1745 0 : pipe->top_pipe = NULL;
1746 0 : pipe->prev_odm_pipe = NULL;
1747 0 : if (pipe->stream_res.dsc)
1748 0 : dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1749 0 : memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1750 0 : memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1751 0 : repopulate_pipes = true;
1752 0 : } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1753 0 : struct pipe_ctx *top_pipe = pipe->top_pipe;
1754 0 : struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1755 :
1756 0 : top_pipe->bottom_pipe = bottom_pipe;
1757 0 : if (bottom_pipe)
1758 0 : bottom_pipe->top_pipe = top_pipe;
1759 :
1760 0 : pipe->top_pipe = NULL;
1761 0 : pipe->bottom_pipe = NULL;
1762 0 : pipe->plane_state = NULL;
1763 0 : pipe->stream = NULL;
1764 0 : memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1765 0 : memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1766 0 : repopulate_pipes = true;
1767 : } else
1768 0 : ASSERT(0); /* Should never try to merge master pipe */
1769 :
1770 : }
1771 :
1772 0 : for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1773 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1774 0 : struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1775 0 : struct pipe_ctx *hsplit_pipe = NULL;
1776 : bool odm;
1777 0 : int old_index = -1;
1778 :
1779 0 : if (!pipe->stream || newly_split[i])
1780 0 : continue;
1781 :
1782 0 : pipe_idx++;
1783 0 : odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1784 :
1785 0 : if (!pipe->plane_state && !odm)
1786 0 : continue;
1787 :
1788 0 : if (split[i]) {
1789 0 : if (odm) {
1790 0 : if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1791 0 : old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1792 0 : else if (old_pipe->next_odm_pipe)
1793 0 : old_index = old_pipe->next_odm_pipe->pipe_idx;
1794 : } else {
1795 0 : if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1796 0 : old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1797 0 : old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1798 0 : else if (old_pipe->bottom_pipe &&
1799 0 : old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1800 0 : old_index = old_pipe->bottom_pipe->pipe_idx;
1801 : }
1802 0 : hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1803 0 : ASSERT(hsplit_pipe);
1804 0 : if (!hsplit_pipe)
1805 : goto validate_fail;
1806 :
1807 0 : if (!dcn30_split_stream_for_mpc_or_odm(
1808 : dc, &context->res_ctx,
1809 : pipe, hsplit_pipe, odm))
1810 : goto validate_fail;
1811 :
1812 0 : newly_split[hsplit_pipe->pipe_idx] = true;
1813 0 : repopulate_pipes = true;
1814 : }
1815 0 : if (split[i] == 4) {
1816 : struct pipe_ctx *pipe_4to1;
1817 :
1818 0 : if (odm && old_pipe->next_odm_pipe)
1819 0 : old_index = old_pipe->next_odm_pipe->pipe_idx;
1820 0 : else if (!odm && old_pipe->bottom_pipe &&
1821 0 : old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1822 0 : old_index = old_pipe->bottom_pipe->pipe_idx;
1823 : else
1824 : old_index = -1;
1825 0 : pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1826 0 : ASSERT(pipe_4to1);
1827 0 : if (!pipe_4to1)
1828 : goto validate_fail;
1829 0 : if (!dcn30_split_stream_for_mpc_or_odm(
1830 : dc, &context->res_ctx,
1831 : pipe, pipe_4to1, odm))
1832 : goto validate_fail;
1833 0 : newly_split[pipe_4to1->pipe_idx] = true;
1834 :
1835 0 : if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1836 0 : && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1837 0 : old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1838 0 : else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1839 0 : old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1840 0 : old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1841 0 : old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1842 : else
1843 : old_index = -1;
1844 0 : pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1845 0 : ASSERT(pipe_4to1);
1846 0 : if (!pipe_4to1)
1847 : goto validate_fail;
1848 0 : if (!dcn30_split_stream_for_mpc_or_odm(
1849 : dc, &context->res_ctx,
1850 : hsplit_pipe, pipe_4to1, odm))
1851 : goto validate_fail;
1852 0 : newly_split[pipe_4to1->pipe_idx] = true;
1853 : }
1854 0 : if (odm)
1855 0 : dcn20_build_mapped_resource(dc, context, pipe->stream);
1856 : }
1857 :
1858 0 : for (i = 0; i < dc->res_pool->pipe_count; i++) {
1859 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1860 :
1861 0 : if (pipe->plane_state) {
1862 0 : if (!resource_build_scaling_params(pipe))
1863 : goto validate_fail;
1864 : }
1865 : }
1866 :
1867 : /* Actual dsc count per stream dsc validation*/
1868 0 : if (!dcn20_validate_dsc(dc, context)) {
1869 0 : vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1870 0 : goto validate_fail;
1871 : }
1872 :
1873 0 : if (repopulate_pipes)
1874 0 : pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1875 0 : *vlevel_out = vlevel;
1876 0 : *pipe_cnt_out = pipe_cnt;
1877 :
1878 0 : out = true;
1879 0 : goto validate_out;
1880 :
1881 : validate_fail:
1882 : out = false;
1883 :
1884 : validate_out:
1885 : return out;
1886 : }
1887 :
1888 : static int get_refresh_rate(struct dc_state *context)
1889 : {
1890 0 : int refresh_rate = 0;
1891 0 : int h_v_total = 0;
1892 0 : struct dc_crtc_timing *timing = NULL;
1893 :
1894 : if (context == NULL || context->streams[0] == NULL)
1895 : return 0;
1896 :
1897 : /* check if refresh rate at least 120hz */
1898 0 : timing = &context->streams[0]->timing;
1899 0 : if (timing == NULL)
1900 : return 0;
1901 :
1902 0 : h_v_total = timing->h_total * timing->v_total;
1903 0 : if (h_v_total == 0)
1904 : return 0;
1905 :
1906 0 : refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1907 : return refresh_rate;
1908 : }
1909 :
1910 : #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1911 : /*
1912 : * Scaling factor for v_blank stretch calculations considering timing in
1913 : * micro-seconds and pixel clock in 100hz.
1914 : * Note: the parenthesis are necessary to ensure the correct order of
1915 : * operation where V_SCALE is used.
1916 : */
1917 : #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1918 :
1919 0 : int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1920 : {
1921 0 : struct dc_crtc_timing *timing = NULL;
1922 : uint32_t sec_per_100_lines;
1923 : uint32_t max_v_blank;
1924 : uint32_t curr_v_blank;
1925 : uint32_t v_stretch_max;
1926 : uint32_t stretched_frame_pix_cnt;
1927 : uint32_t scaled_stretched_frame_pix_cnt;
1928 : uint32_t scaled_refresh_rate;
1929 :
1930 0 : if (context == NULL || context->streams[0] == NULL)
1931 : return 0;
1932 :
1933 : /* check if refresh rate at least 120hz */
1934 0 : timing = &context->streams[0]->timing;
1935 0 : if (timing == NULL)
1936 : return 0;
1937 :
1938 0 : sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1939 0 : max_v_blank = sec_per_100_lines / V_SCALE + 1;
1940 0 : curr_v_blank = timing->v_total - timing->v_addressable;
1941 0 : v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1942 0 : stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1943 0 : scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1944 0 : scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1945 :
1946 0 : return scaled_refresh_rate;
1947 : }
1948 :
1949 0 : bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1950 : {
1951 : int refresh_rate_max_stretch_100hz;
1952 : int min_refresh_100hz;
1953 :
1954 0 : if (context == NULL || context->streams[0] == NULL)
1955 : return false;
1956 :
1957 0 : refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1958 0 : min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1959 :
1960 0 : if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1961 : return false;
1962 :
1963 0 : return true;
1964 : }
1965 :
1966 0 : bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1967 : {
1968 0 : int refresh_rate = 0;
1969 0 : const int minimum_refreshrate_supported = 120;
1970 :
1971 0 : if (context == NULL || context->streams[0] == NULL)
1972 : return false;
1973 :
1974 0 : if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1975 : return false;
1976 :
1977 0 : if (dc->debug.disable_fams)
1978 : return false;
1979 :
1980 0 : if (!dc->caps.dmub_caps.mclk_sw)
1981 : return false;
1982 :
1983 0 : if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1984 : return false;
1985 :
1986 : /* more then 1 monitor connected */
1987 0 : if (context->stream_count != 1)
1988 : return false;
1989 :
1990 0 : refresh_rate = get_refresh_rate(context);
1991 0 : if (refresh_rate < minimum_refreshrate_supported)
1992 : return false;
1993 :
1994 0 : if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
1995 : return false;
1996 :
1997 : // check if freesync enabled
1998 0 : if (!context->streams[0]->allow_freesync)
1999 : return false;
2000 :
2001 0 : if (context->streams[0]->vrr_active_variable)
2002 : return false;
2003 :
2004 0 : return true;
2005 : }
2006 :
2007 : /*
2008 : * set up FPO watermarks, pstate, dram latency
2009 : */
2010 0 : void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2011 : {
2012 0 : ASSERT(dc != NULL && context != NULL);
2013 0 : if (dc == NULL || context == NULL)
2014 : return;
2015 :
2016 : /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2017 0 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2018 : }
2019 :
2020 0 : void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2021 : {
2022 0 : DC_FP_START();
2023 0 : dcn30_fpu_update_soc_for_wm_a(dc, context);
2024 0 : DC_FP_END();
2025 0 : }
2026 :
2027 0 : void dcn30_calculate_wm_and_dlg(
2028 : struct dc *dc, struct dc_state *context,
2029 : display_e2e_pipe_params_st *pipes,
2030 : int pipe_cnt,
2031 : int vlevel)
2032 : {
2033 0 : DC_FP_START();
2034 0 : dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2035 0 : DC_FP_END();
2036 0 : }
2037 :
2038 0 : bool dcn30_validate_bandwidth(struct dc *dc,
2039 : struct dc_state *context,
2040 : bool fast_validate)
2041 : {
2042 0 : bool out = false;
2043 :
2044 0 : BW_VAL_TRACE_SETUP();
2045 :
2046 0 : int vlevel = 0;
2047 0 : int pipe_cnt = 0;
2048 0 : display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2049 : DC_LOGGER_INIT(dc->ctx->logger);
2050 :
2051 0 : BW_VAL_TRACE_COUNT();
2052 :
2053 0 : DC_FP_START();
2054 0 : out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2055 0 : DC_FP_END();
2056 :
2057 0 : if (pipe_cnt == 0)
2058 : goto validate_out;
2059 :
2060 0 : if (!out)
2061 : goto validate_fail;
2062 :
2063 0 : BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2064 :
2065 0 : if (fast_validate) {
2066 0 : BW_VAL_TRACE_SKIP(fast);
2067 : goto validate_out;
2068 : }
2069 :
2070 0 : DC_FP_START();
2071 0 : dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2072 0 : DC_FP_END();
2073 :
2074 0 : BW_VAL_TRACE_END_WATERMARKS();
2075 :
2076 : goto validate_out;
2077 :
2078 : validate_fail:
2079 0 : DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2080 : dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2081 :
2082 0 : BW_VAL_TRACE_SKIP(fail);
2083 : out = false;
2084 :
2085 : validate_out:
2086 0 : kfree(pipes);
2087 :
2088 0 : BW_VAL_TRACE_FINISH();
2089 :
2090 0 : return out;
2091 : }
2092 :
2093 0 : void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2094 : {
2095 : unsigned int i, j;
2096 0 : unsigned int num_states = 0;
2097 :
2098 0 : unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2099 0 : unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2100 0 : unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2101 0 : unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2102 :
2103 0 : unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2104 0 : unsigned int num_dcfclk_sta_targets = 4;
2105 : unsigned int num_uclk_states;
2106 :
2107 : struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2108 :
2109 0 : memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2110 :
2111 0 : if (dc->ctx->dc_bios->vram_info.num_chans)
2112 0 : dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2113 :
2114 0 : DC_FP_START();
2115 0 : dcn30_fpu_update_dram_channel_width_bytes(dc);
2116 0 : DC_FP_END();
2117 :
2118 0 : if (bw_params->clk_table.entries[0].memclk_mhz) {
2119 :
2120 0 : for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2121 0 : if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2122 0 : dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2123 0 : if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2124 0 : dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2125 0 : if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2126 0 : dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2127 0 : if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2128 0 : dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2129 : }
2130 :
2131 0 : DC_FP_START();
2132 0 : dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2133 0 : DC_FP_END();
2134 :
2135 0 : if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2136 : // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2137 0 : dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2138 0 : num_dcfclk_sta_targets++;
2139 0 : } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2140 : // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2141 0 : for (i = 0; i < num_dcfclk_sta_targets; i++) {
2142 0 : if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2143 0 : dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2144 0 : break;
2145 : }
2146 : }
2147 : // Update size of array since we "removed" duplicates
2148 0 : num_dcfclk_sta_targets = i + 1;
2149 : }
2150 :
2151 0 : num_uclk_states = bw_params->clk_table.num_entries;
2152 :
2153 : // Calculate optimal dcfclk for each uclk
2154 0 : for (i = 0; i < num_uclk_states; i++) {
2155 0 : DC_FP_START();
2156 0 : dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2157 : &optimal_dcfclk_for_uclk[i], NULL);
2158 0 : DC_FP_END();
2159 0 : if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2160 0 : optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2161 : }
2162 : }
2163 :
2164 : // Calculate optimal uclk for each dcfclk sta target
2165 0 : for (i = 0; i < num_dcfclk_sta_targets; i++) {
2166 0 : for (j = 0; j < num_uclk_states; j++) {
2167 0 : if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2168 0 : optimal_uclk_for_dcfclk_sta_targets[i] =
2169 0 : bw_params->clk_table.entries[j].memclk_mhz * 16;
2170 0 : break;
2171 : }
2172 : }
2173 : }
2174 :
2175 : i = 0;
2176 : j = 0;
2177 : // create the final dcfclk and uclk table
2178 0 : while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2179 0 : if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2180 0 : dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2181 0 : dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2182 : } else {
2183 0 : if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2184 0 : dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2185 0 : dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2186 : } else {
2187 : j = num_uclk_states;
2188 : }
2189 : }
2190 : }
2191 :
2192 0 : while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2193 0 : dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2194 0 : dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2195 : }
2196 :
2197 0 : while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2198 0 : optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2199 0 : dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2200 0 : dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2201 : }
2202 :
2203 0 : dcn3_0_soc.num_states = num_states;
2204 0 : DC_FP_START();
2205 0 : dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2206 0 : DC_FP_END();
2207 : }
2208 0 : }
2209 :
2210 : static const struct resource_funcs dcn30_res_pool_funcs = {
2211 : .destroy = dcn30_destroy_resource_pool,
2212 : .link_enc_create = dcn30_link_encoder_create,
2213 : .panel_cntl_create = dcn30_panel_cntl_create,
2214 : .validate_bandwidth = dcn30_validate_bandwidth,
2215 : .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2216 : .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2217 : .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2218 : .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2219 : .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2220 : .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2221 : .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2222 : .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2223 : .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2224 : .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2225 : .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2226 : .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2227 : .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2228 : .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2229 : };
2230 :
2231 : #define CTX ctx
2232 :
2233 : #define REG(reg_name) \
2234 : (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2235 :
2236 : static uint32_t read_pipe_fuses(struct dc_context *ctx)
2237 : {
2238 0 : uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2239 : /* Support for max 6 pipes */
2240 0 : value = value & 0x3f;
2241 : return value;
2242 : }
2243 :
2244 0 : static bool dcn30_resource_construct(
2245 : uint8_t num_virtual_links,
2246 : struct dc *dc,
2247 : struct dcn30_resource_pool *pool)
2248 : {
2249 : int i;
2250 0 : struct dc_context *ctx = dc->ctx;
2251 : struct irq_service_init_data init_data;
2252 0 : struct ddc_service_init_data ddc_init_data = {0};
2253 0 : uint32_t pipe_fuses = read_pipe_fuses(ctx);
2254 0 : uint32_t num_pipes = 0;
2255 :
2256 0 : if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2257 0 : BREAK_TO_DEBUGGER();
2258 0 : dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2259 : /* fault to single pipe */
2260 0 : pipe_fuses = 0x3e;
2261 : }
2262 :
2263 0 : DC_FP_START();
2264 :
2265 0 : ctx->dc_bios->regs = &bios_regs;
2266 :
2267 0 : pool->base.res_cap = &res_cap_dcn3;
2268 :
2269 0 : pool->base.funcs = &dcn30_res_pool_funcs;
2270 :
2271 : /*************************************************
2272 : * Resource + asic cap harcoding *
2273 : *************************************************/
2274 0 : pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2275 0 : pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2276 0 : pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2277 0 : dc->caps.max_downscale_ratio = 600;
2278 0 : dc->caps.i2c_speed_in_khz = 100;
2279 0 : dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2280 0 : dc->caps.max_cursor_size = 256;
2281 0 : dc->caps.min_horizontal_blanking_period = 80;
2282 0 : dc->caps.dmdata_alloc_size = 2048;
2283 0 : dc->caps.mall_size_per_mem_channel = 8;
2284 : /* total size = mall per channel * num channels * 1024 * 1024 */
2285 0 : dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2286 0 : dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2287 :
2288 0 : dc->caps.max_slave_planes = 2;
2289 0 : dc->caps.max_slave_yuv_planes = 2;
2290 0 : dc->caps.max_slave_rgb_planes = 2;
2291 0 : dc->caps.post_blend_color_processing = true;
2292 0 : dc->caps.force_dp_tps4_for_cp2520 = true;
2293 0 : dc->caps.extended_aux_timeout_support = true;
2294 0 : dc->caps.dmcub_support = true;
2295 :
2296 : /* Color pipeline capabilities */
2297 0 : dc->caps.color.dpp.dcn_arch = 1;
2298 0 : dc->caps.color.dpp.input_lut_shared = 0;
2299 0 : dc->caps.color.dpp.icsc = 1;
2300 0 : dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2301 0 : dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2302 0 : dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2303 0 : dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2304 0 : dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2305 0 : dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2306 0 : dc->caps.color.dpp.post_csc = 1;
2307 0 : dc->caps.color.dpp.gamma_corr = 1;
2308 0 : dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2309 :
2310 0 : dc->caps.color.dpp.hw_3d_lut = 1;
2311 0 : dc->caps.color.dpp.ogam_ram = 1;
2312 : // no OGAM ROM on DCN3
2313 0 : dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2314 0 : dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2315 0 : dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2316 0 : dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2317 0 : dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2318 0 : dc->caps.color.dpp.ocsc = 0;
2319 :
2320 0 : dc->caps.color.mpc.gamut_remap = 1;
2321 0 : dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2322 0 : dc->caps.color.mpc.ogam_ram = 1;
2323 0 : dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2324 0 : dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2325 0 : dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2326 0 : dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2327 0 : dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2328 0 : dc->caps.color.mpc.ocsc = 1;
2329 :
2330 0 : dc->caps.dp_hdmi21_pcon_support = true;
2331 :
2332 : /* read VBIOS LTTPR caps */
2333 : {
2334 0 : if (ctx->dc_bios->funcs->get_lttpr_caps) {
2335 : enum bp_result bp_query_result;
2336 0 : uint8_t is_vbios_lttpr_enable = 0;
2337 :
2338 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2339 0 : dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2340 : }
2341 :
2342 0 : if (ctx->dc_bios->funcs->get_lttpr_interop) {
2343 : enum bp_result bp_query_result;
2344 0 : uint8_t is_vbios_interop_enabled = 0;
2345 :
2346 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2347 : &is_vbios_interop_enabled);
2348 0 : dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2349 : }
2350 : }
2351 :
2352 0 : if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2353 0 : dc->debug = debug_defaults_drv;
2354 0 : else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2355 0 : dc->debug = debug_defaults_diags;
2356 : } else
2357 0 : dc->debug = debug_defaults_diags;
2358 : // Init the vm_helper
2359 0 : if (dc->vm_helper)
2360 0 : vm_helper_init(dc->vm_helper, 16);
2361 :
2362 : /*************************************************
2363 : * Create resources *
2364 : *************************************************/
2365 :
2366 : /* Clock Sources for Pixel Clock*/
2367 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2368 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2369 : CLOCK_SOURCE_COMBO_PHY_PLL0,
2370 : &clk_src_regs[0], false);
2371 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2372 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2373 : CLOCK_SOURCE_COMBO_PHY_PLL1,
2374 : &clk_src_regs[1], false);
2375 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2376 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2377 : CLOCK_SOURCE_COMBO_PHY_PLL2,
2378 : &clk_src_regs[2], false);
2379 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2380 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2381 : CLOCK_SOURCE_COMBO_PHY_PLL3,
2382 : &clk_src_regs[3], false);
2383 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2384 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2385 : CLOCK_SOURCE_COMBO_PHY_PLL4,
2386 : &clk_src_regs[4], false);
2387 0 : pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2388 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2389 : CLOCK_SOURCE_COMBO_PHY_PLL5,
2390 : &clk_src_regs[5], false);
2391 :
2392 0 : pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2393 :
2394 : /* todo: not reuse phy_pll registers */
2395 0 : pool->base.dp_clock_source =
2396 0 : dcn30_clock_source_create(ctx, ctx->dc_bios,
2397 : CLOCK_SOURCE_ID_DP_DTO,
2398 : &clk_src_regs[0], true);
2399 :
2400 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
2401 0 : if (pool->base.clock_sources[i] == NULL) {
2402 0 : dm_error("DC: failed to create clock sources!\n");
2403 0 : BREAK_TO_DEBUGGER();
2404 0 : goto create_fail;
2405 : }
2406 : }
2407 :
2408 : /* DCCG */
2409 0 : pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2410 0 : if (pool->base.dccg == NULL) {
2411 0 : dm_error("DC: failed to create dccg!\n");
2412 0 : BREAK_TO_DEBUGGER();
2413 0 : goto create_fail;
2414 : }
2415 :
2416 : /* PP Lib and SMU interfaces */
2417 0 : init_soc_bounding_box(dc, pool);
2418 :
2419 0 : num_pipes = dcn3_0_ip.max_num_dpp;
2420 :
2421 0 : for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2422 0 : if (pipe_fuses & 1 << i)
2423 0 : num_pipes--;
2424 :
2425 0 : dcn3_0_ip.max_num_dpp = num_pipes;
2426 0 : dcn3_0_ip.max_num_otg = num_pipes;
2427 :
2428 0 : dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2429 :
2430 : /* IRQ */
2431 0 : init_data.ctx = dc->ctx;
2432 0 : pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2433 0 : if (!pool->base.irqs)
2434 : goto create_fail;
2435 :
2436 : /* HUBBUB */
2437 0 : pool->base.hubbub = dcn30_hubbub_create(ctx);
2438 0 : if (pool->base.hubbub == NULL) {
2439 0 : BREAK_TO_DEBUGGER();
2440 0 : dm_error("DC: failed to create hubbub!\n");
2441 0 : goto create_fail;
2442 : }
2443 :
2444 : /* HUBPs, DPPs, OPPs and TGs */
2445 0 : for (i = 0; i < pool->base.pipe_count; i++) {
2446 0 : pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2447 0 : if (pool->base.hubps[i] == NULL) {
2448 0 : BREAK_TO_DEBUGGER();
2449 0 : dm_error(
2450 : "DC: failed to create hubps!\n");
2451 0 : goto create_fail;
2452 : }
2453 :
2454 0 : pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2455 0 : if (pool->base.dpps[i] == NULL) {
2456 0 : BREAK_TO_DEBUGGER();
2457 0 : dm_error(
2458 : "DC: failed to create dpps!\n");
2459 0 : goto create_fail;
2460 : }
2461 : }
2462 :
2463 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2464 0 : pool->base.opps[i] = dcn30_opp_create(ctx, i);
2465 0 : if (pool->base.opps[i] == NULL) {
2466 0 : BREAK_TO_DEBUGGER();
2467 0 : dm_error(
2468 : "DC: failed to create output pixel processor!\n");
2469 0 : goto create_fail;
2470 : }
2471 : }
2472 :
2473 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2474 0 : pool->base.timing_generators[i] = dcn30_timing_generator_create(
2475 : ctx, i);
2476 0 : if (pool->base.timing_generators[i] == NULL) {
2477 0 : BREAK_TO_DEBUGGER();
2478 0 : dm_error("DC: failed to create tg!\n");
2479 0 : goto create_fail;
2480 : }
2481 : }
2482 0 : pool->base.timing_generator_count = i;
2483 : /* PSR */
2484 0 : pool->base.psr = dmub_psr_create(ctx);
2485 :
2486 0 : if (pool->base.psr == NULL) {
2487 0 : dm_error("DC: failed to create PSR obj!\n");
2488 0 : BREAK_TO_DEBUGGER();
2489 0 : goto create_fail;
2490 : }
2491 :
2492 : /* ABM */
2493 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2494 0 : pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2495 : &abm_regs[i],
2496 : &abm_shift,
2497 : &abm_mask);
2498 0 : if (pool->base.multiple_abms[i] == NULL) {
2499 0 : dm_error("DC: failed to create abm for pipe %d!\n", i);
2500 0 : BREAK_TO_DEBUGGER();
2501 0 : goto create_fail;
2502 : }
2503 : }
2504 : /* MPC and DSC */
2505 0 : pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2506 0 : if (pool->base.mpc == NULL) {
2507 0 : BREAK_TO_DEBUGGER();
2508 0 : dm_error("DC: failed to create mpc!\n");
2509 0 : goto create_fail;
2510 : }
2511 :
2512 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2513 0 : pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2514 0 : if (pool->base.dscs[i] == NULL) {
2515 0 : BREAK_TO_DEBUGGER();
2516 0 : dm_error("DC: failed to create display stream compressor %d!\n", i);
2517 0 : goto create_fail;
2518 : }
2519 : }
2520 :
2521 : /* DWB and MMHUBBUB */
2522 0 : if (!dcn30_dwbc_create(ctx, &pool->base)) {
2523 0 : BREAK_TO_DEBUGGER();
2524 0 : dm_error("DC: failed to create dwbc!\n");
2525 0 : goto create_fail;
2526 : }
2527 :
2528 0 : if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2529 0 : BREAK_TO_DEBUGGER();
2530 0 : dm_error("DC: failed to create mcif_wb!\n");
2531 0 : goto create_fail;
2532 : }
2533 :
2534 : /* AUX and I2C */
2535 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2536 0 : pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2537 0 : if (pool->base.engines[i] == NULL) {
2538 0 : BREAK_TO_DEBUGGER();
2539 0 : dm_error(
2540 : "DC:failed to create aux engine!!\n");
2541 0 : goto create_fail;
2542 : }
2543 0 : pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2544 0 : if (pool->base.hw_i2cs[i] == NULL) {
2545 0 : BREAK_TO_DEBUGGER();
2546 0 : dm_error(
2547 : "DC:failed to create hw i2c!!\n");
2548 0 : goto create_fail;
2549 : }
2550 0 : pool->base.sw_i2cs[i] = NULL;
2551 : }
2552 :
2553 : /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2554 0 : if (!resource_construct(num_virtual_links, dc, &pool->base,
2555 0 : (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2556 : &res_create_funcs : &res_create_maximus_funcs)))
2557 : goto create_fail;
2558 :
2559 : /* HW Sequencer and Plane caps */
2560 0 : dcn30_hw_sequencer_construct(dc);
2561 :
2562 0 : dc->caps.max_planes = pool->base.pipe_count;
2563 :
2564 0 : for (i = 0; i < dc->caps.max_planes; ++i)
2565 0 : dc->caps.planes[i] = plane_cap;
2566 :
2567 0 : dc->cap_funcs = cap_funcs;
2568 :
2569 0 : if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2570 0 : ddc_init_data.ctx = dc->ctx;
2571 0 : ddc_init_data.link = NULL;
2572 0 : ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2573 0 : ddc_init_data.id.enum_id = 0;
2574 0 : ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2575 0 : pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2576 : } else {
2577 0 : pool->base.oem_device = NULL;
2578 : }
2579 :
2580 0 : DC_FP_END();
2581 :
2582 0 : return true;
2583 :
2584 : create_fail:
2585 :
2586 0 : DC_FP_END();
2587 0 : dcn30_resource_destruct(pool);
2588 :
2589 0 : return false;
2590 : }
2591 :
2592 0 : struct resource_pool *dcn30_create_resource_pool(
2593 : const struct dc_init_data *init_data,
2594 : struct dc *dc)
2595 : {
2596 0 : struct dcn30_resource_pool *pool =
2597 : kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2598 :
2599 0 : if (!pool)
2600 : return NULL;
2601 :
2602 0 : if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2603 0 : return &pool->base;
2604 :
2605 0 : BREAK_TO_DEBUGGER();
2606 0 : kfree(pool);
2607 0 : return NULL;
2608 : }
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