Line data Source code
1 : /*
2 : * Copyright 2019-2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 :
27 : #include "dm_services.h"
28 : #include "dc.h"
29 :
30 : #include "dcn301_init.h"
31 :
32 : #include "resource.h"
33 : #include "include/irq_service_interface.h"
34 : #include "dcn30/dcn30_resource.h"
35 : #include "dcn301_resource.h"
36 :
37 : #include "dcn20/dcn20_resource.h"
38 :
39 : #include "dcn10/dcn10_ipp.h"
40 : #include "dcn301/dcn301_hubbub.h"
41 : #include "dcn30/dcn30_mpc.h"
42 : #include "dcn30/dcn30_hubp.h"
43 : #include "irq/dcn30/irq_service_dcn30.h"
44 : #include "dcn30/dcn30_dpp.h"
45 : #include "dcn30/dcn30_optc.h"
46 : #include "dcn20/dcn20_hwseq.h"
47 : #include "dcn30/dcn30_hwseq.h"
48 : #include "dce110/dce110_hw_sequencer.h"
49 : #include "dcn30/dcn30_opp.h"
50 : #include "dcn20/dcn20_dsc.h"
51 : #include "dcn30/dcn30_vpg.h"
52 : #include "dcn30/dcn30_afmt.h"
53 : #include "dce/dce_clock_source.h"
54 : #include "dce/dce_audio.h"
55 : #include "dce/dce_hwseq.h"
56 : #include "clk_mgr.h"
57 : #include "virtual/virtual_stream_encoder.h"
58 : #include "dce110/dce110_resource.h"
59 : #include "dml/display_mode_vba.h"
60 : #include "dcn301/dcn301_dccg.h"
61 : #include "dcn10/dcn10_resource.h"
62 : #include "dcn30/dcn30_dio_stream_encoder.h"
63 : #include "dcn301/dcn301_dio_link_encoder.h"
64 : #include "dcn301_panel_cntl.h"
65 :
66 : #include "vangogh_ip_offset.h"
67 :
68 : #include "dcn30/dcn30_dwb.h"
69 : #include "dcn30/dcn30_mmhubbub.h"
70 :
71 : #include "dcn/dcn_3_0_1_offset.h"
72 : #include "dcn/dcn_3_0_1_sh_mask.h"
73 :
74 : #include "nbio/nbio_7_2_0_offset.h"
75 :
76 : #include "dpcs/dpcs_3_0_0_offset.h"
77 : #include "dpcs/dpcs_3_0_0_sh_mask.h"
78 :
79 : #include "reg_helper.h"
80 : #include "dce/dmub_abm.h"
81 : #include "dce/dce_aux.h"
82 : #include "dce/dce_i2c.h"
83 :
84 : #include "dml/dcn30/dcn30_fpu.h"
85 :
86 : #include "dml/dcn30/display_mode_vba_30.h"
87 : #include "dml/dcn301/dcn301_fpu.h"
88 : #include "vm_helper.h"
89 : #include "dcn20/dcn20_vmid.h"
90 : #include "amdgpu_socbb.h"
91 :
92 : #define TO_DCN301_RES_POOL(pool)\
93 : container_of(pool, struct dcn301_resource_pool, base)
94 :
95 : #define DC_LOGGER_INIT(logger)
96 :
97 : enum dcn301_clk_src_array_id {
98 : DCN301_CLK_SRC_PLL0,
99 : DCN301_CLK_SRC_PLL1,
100 : DCN301_CLK_SRC_PLL2,
101 : DCN301_CLK_SRC_PLL3,
102 : DCN301_CLK_SRC_TOTAL
103 : };
104 :
105 : /* begin *********************
106 : * macros to expend register list macro defined in HW object header file
107 : */
108 :
109 : /* DCN */
110 : /* TODO awful hack. fixup dcn20_dwb.h */
111 : #undef BASE_INNER
112 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
113 :
114 : #define BASE(seg) BASE_INNER(seg)
115 :
116 : #define SR(reg_name)\
117 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 : mm ## reg_name
119 :
120 : #define SRI(reg_name, block, id)\
121 : .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 : mm ## block ## id ## _ ## reg_name
123 :
124 : #define SRI2(reg_name, block, id)\
125 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
126 : mm ## reg_name
127 :
128 : #define SRIR(var_name, reg_name, block, id)\
129 : .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 : mm ## block ## id ## _ ## reg_name
131 :
132 : #define SRII(reg_name, block, id)\
133 : .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 : mm ## block ## id ## _ ## reg_name
135 :
136 : #define SRII2(reg_name_pre, reg_name_post, id)\
137 : .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \
138 : ## id ## _ ## reg_name_post ## _BASE_IDX) + \
139 : mm ## reg_name_pre ## id ## _ ## reg_name_post
140 :
141 : #define SRII_MPC_RMU(reg_name, block, id)\
142 : .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 : mm ## block ## id ## _ ## reg_name
144 :
145 : #define SRII_DWB(reg_name, temp_name, block, id)\
146 : .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
147 : mm ## block ## id ## _ ## temp_name
148 :
149 : #define DCCG_SRII(reg_name, block, id)\
150 : .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 : mm ## block ## id ## _ ## reg_name
152 :
153 : #define VUPDATE_SRII(reg_name, block, id)\
154 : .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
155 : mm ## reg_name ## _ ## block ## id
156 :
157 : /* NBIO */
158 : #define NBIO_BASE_INNER(seg) \
159 : NBIO_BASE__INST0_SEG ## seg
160 :
161 : #define NBIO_BASE(seg) \
162 : NBIO_BASE_INNER(seg)
163 :
164 : #define NBIO_SR(reg_name)\
165 : .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
166 : regBIF_BX0_ ## reg_name
167 :
168 : /* MMHUB */
169 : #define MMHUB_BASE_INNER(seg) \
170 : MMHUB_BASE__INST0_SEG ## seg
171 :
172 : #define MMHUB_BASE(seg) \
173 : MMHUB_BASE_INNER(seg)
174 :
175 : #define MMHUB_SR(reg_name)\
176 : .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
177 : regMM ## reg_name
178 :
179 : /* CLOCK */
180 : #define CLK_BASE_INNER(seg) \
181 : CLK_BASE__INST0_SEG ## seg
182 :
183 : #define CLK_BASE(seg) \
184 : CLK_BASE_INNER(seg)
185 :
186 : #define CLK_SRI(reg_name, block, inst)\
187 : .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
188 : mm ## block ## _ ## inst ## _ ## reg_name
189 :
190 : static const struct bios_registers bios_regs = {
191 : NBIO_SR(BIOS_SCRATCH_3),
192 : NBIO_SR(BIOS_SCRATCH_6)
193 : };
194 :
195 : #define clk_src_regs(index, pllid)\
196 : [index] = {\
197 : CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
198 : }
199 :
200 : static const struct dce110_clk_src_regs clk_src_regs[] = {
201 : clk_src_regs(0, A),
202 : clk_src_regs(1, B),
203 : clk_src_regs(2, C),
204 : clk_src_regs(3, D)
205 : };
206 :
207 : static const struct dce110_clk_src_shift cs_shift = {
208 : CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
209 : };
210 :
211 : static const struct dce110_clk_src_mask cs_mask = {
212 : CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
213 : };
214 :
215 : #define abm_regs(id)\
216 : [id] = {\
217 : ABM_DCN301_REG_LIST(id)\
218 : }
219 :
220 : static const struct dce_abm_registers abm_regs[] = {
221 : abm_regs(0),
222 : abm_regs(1),
223 : abm_regs(2),
224 : abm_regs(3),
225 : };
226 :
227 : static const struct dce_abm_shift abm_shift = {
228 : ABM_MASK_SH_LIST_DCN30(__SHIFT)
229 : };
230 :
231 : static const struct dce_abm_mask abm_mask = {
232 : ABM_MASK_SH_LIST_DCN30(_MASK)
233 : };
234 :
235 : #define audio_regs(id)\
236 : [id] = {\
237 : AUD_COMMON_REG_LIST(id)\
238 : }
239 :
240 : static const struct dce_audio_registers audio_regs[] = {
241 : audio_regs(0),
242 : audio_regs(1),
243 : audio_regs(2),
244 : audio_regs(3),
245 : audio_regs(4),
246 : audio_regs(5),
247 : audio_regs(6)
248 : };
249 :
250 : #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
251 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
252 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
253 : AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
254 :
255 : static const struct dce_audio_shift audio_shift = {
256 : DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
257 : };
258 :
259 : static const struct dce_audio_mask audio_mask = {
260 : DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
261 : };
262 :
263 : #define vpg_regs(id)\
264 : [id] = {\
265 : VPG_DCN3_REG_LIST(id)\
266 : }
267 :
268 : static const struct dcn30_vpg_registers vpg_regs[] = {
269 : vpg_regs(0),
270 : vpg_regs(1),
271 : vpg_regs(2),
272 : vpg_regs(3),
273 : };
274 :
275 : static const struct dcn30_vpg_shift vpg_shift = {
276 : DCN3_VPG_MASK_SH_LIST(__SHIFT)
277 : };
278 :
279 : static const struct dcn30_vpg_mask vpg_mask = {
280 : DCN3_VPG_MASK_SH_LIST(_MASK)
281 : };
282 :
283 : #define afmt_regs(id)\
284 : [id] = {\
285 : AFMT_DCN3_REG_LIST(id)\
286 : }
287 :
288 : static const struct dcn30_afmt_registers afmt_regs[] = {
289 : afmt_regs(0),
290 : afmt_regs(1),
291 : afmt_regs(2),
292 : afmt_regs(3),
293 : };
294 :
295 : static const struct dcn30_afmt_shift afmt_shift = {
296 : DCN3_AFMT_MASK_SH_LIST(__SHIFT)
297 : };
298 :
299 : static const struct dcn30_afmt_mask afmt_mask = {
300 : DCN3_AFMT_MASK_SH_LIST(_MASK)
301 : };
302 :
303 : #define stream_enc_regs(id)\
304 : [id] = {\
305 : SE_DCN3_REG_LIST(id)\
306 : }
307 :
308 : static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
309 : stream_enc_regs(0),
310 : stream_enc_regs(1),
311 : stream_enc_regs(2),
312 : stream_enc_regs(3),
313 : };
314 :
315 : static const struct dcn10_stream_encoder_shift se_shift = {
316 : SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
317 : };
318 :
319 : static const struct dcn10_stream_encoder_mask se_mask = {
320 : SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
321 : };
322 :
323 :
324 : #define aux_regs(id)\
325 : [id] = {\
326 : DCN2_AUX_REG_LIST(id)\
327 : }
328 :
329 : static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
330 : aux_regs(0),
331 : aux_regs(1),
332 : aux_regs(2),
333 : aux_regs(3),
334 : };
335 :
336 : #define hpd_regs(id)\
337 : [id] = {\
338 : HPD_REG_LIST(id)\
339 : }
340 :
341 : static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
342 : hpd_regs(0),
343 : hpd_regs(1),
344 : hpd_regs(2),
345 : hpd_regs(3),
346 : };
347 :
348 :
349 : #define link_regs(id, phyid)\
350 : [id] = {\
351 : LE_DCN301_REG_LIST(id), \
352 : UNIPHY_DCN2_REG_LIST(phyid), \
353 : DPCS_DCN2_REG_LIST(id), \
354 : SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
355 : }
356 :
357 : static const struct dce110_aux_registers_shift aux_shift = {
358 : DCN_AUX_MASK_SH_LIST(__SHIFT)
359 : };
360 :
361 : static const struct dce110_aux_registers_mask aux_mask = {
362 : DCN_AUX_MASK_SH_LIST(_MASK)
363 : };
364 :
365 : static const struct dcn10_link_enc_registers link_enc_regs[] = {
366 : link_regs(0, A),
367 : link_regs(1, B),
368 : link_regs(2, C),
369 : link_regs(3, D),
370 : };
371 :
372 : static const struct dcn10_link_enc_shift le_shift = {
373 : LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
374 : DPCS_DCN2_MASK_SH_LIST(__SHIFT)
375 : };
376 :
377 : static const struct dcn10_link_enc_mask le_mask = {
378 : LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
379 : DPCS_DCN2_MASK_SH_LIST(_MASK)
380 : };
381 :
382 : #define panel_cntl_regs(id)\
383 : [id] = {\
384 : DCN301_PANEL_CNTL_REG_LIST(id),\
385 : }
386 :
387 : static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
388 : panel_cntl_regs(0),
389 : panel_cntl_regs(1),
390 : };
391 :
392 : static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
393 : DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
394 : };
395 :
396 : static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
397 : DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
398 : };
399 :
400 : #define dpp_regs(id)\
401 : [id] = {\
402 : DPP_REG_LIST_DCN30(id),\
403 : }
404 :
405 : static const struct dcn3_dpp_registers dpp_regs[] = {
406 : dpp_regs(0),
407 : dpp_regs(1),
408 : dpp_regs(2),
409 : dpp_regs(3),
410 : };
411 :
412 : static const struct dcn3_dpp_shift tf_shift = {
413 : DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
414 : };
415 :
416 : static const struct dcn3_dpp_mask tf_mask = {
417 : DPP_REG_LIST_SH_MASK_DCN30(_MASK)
418 : };
419 :
420 : #define opp_regs(id)\
421 : [id] = {\
422 : OPP_REG_LIST_DCN30(id),\
423 : }
424 :
425 : static const struct dcn20_opp_registers opp_regs[] = {
426 : opp_regs(0),
427 : opp_regs(1),
428 : opp_regs(2),
429 : opp_regs(3),
430 : };
431 :
432 : static const struct dcn20_opp_shift opp_shift = {
433 : OPP_MASK_SH_LIST_DCN20(__SHIFT)
434 : };
435 :
436 : static const struct dcn20_opp_mask opp_mask = {
437 : OPP_MASK_SH_LIST_DCN20(_MASK)
438 : };
439 :
440 : #define aux_engine_regs(id)\
441 : [id] = {\
442 : AUX_COMMON_REG_LIST0(id), \
443 : .AUXN_IMPCAL = 0, \
444 : .AUXP_IMPCAL = 0, \
445 : .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
446 : }
447 :
448 : static const struct dce110_aux_registers aux_engine_regs[] = {
449 : aux_engine_regs(0),
450 : aux_engine_regs(1),
451 : aux_engine_regs(2),
452 : aux_engine_regs(3),
453 : };
454 :
455 : #define dwbc_regs_dcn3(id)\
456 : [id] = {\
457 : DWBC_COMMON_REG_LIST_DCN30(id),\
458 : }
459 :
460 : static const struct dcn30_dwbc_registers dwbc30_regs[] = {
461 : dwbc_regs_dcn3(0),
462 : };
463 :
464 : static const struct dcn30_dwbc_shift dwbc30_shift = {
465 : DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
466 : };
467 :
468 : static const struct dcn30_dwbc_mask dwbc30_mask = {
469 : DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
470 : };
471 :
472 : #define mcif_wb_regs_dcn3(id)\
473 : [id] = {\
474 : MCIF_WB_COMMON_REG_LIST_DCN30(id),\
475 : }
476 :
477 : static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
478 : mcif_wb_regs_dcn3(0)
479 : };
480 :
481 : static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
482 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
483 : };
484 :
485 : static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
486 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
487 : };
488 :
489 : #define dsc_regsDCN20(id)\
490 : [id] = {\
491 : DSC_REG_LIST_DCN20(id)\
492 : }
493 :
494 : static const struct dcn20_dsc_registers dsc_regs[] = {
495 : dsc_regsDCN20(0),
496 : dsc_regsDCN20(1),
497 : dsc_regsDCN20(2),
498 : };
499 :
500 : static const struct dcn20_dsc_shift dsc_shift = {
501 : DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
502 : };
503 :
504 : static const struct dcn20_dsc_mask dsc_mask = {
505 : DSC_REG_LIST_SH_MASK_DCN20(_MASK)
506 : };
507 :
508 : static const struct dcn30_mpc_registers mpc_regs = {
509 : MPC_REG_LIST_DCN3_0(0),
510 : MPC_REG_LIST_DCN3_0(1),
511 : MPC_REG_LIST_DCN3_0(2),
512 : MPC_REG_LIST_DCN3_0(3),
513 : MPC_OUT_MUX_REG_LIST_DCN3_0(0),
514 : MPC_OUT_MUX_REG_LIST_DCN3_0(1),
515 : MPC_OUT_MUX_REG_LIST_DCN3_0(2),
516 : MPC_OUT_MUX_REG_LIST_DCN3_0(3),
517 : MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
518 : MPC_RMU_REG_LIST_DCN3AG(0),
519 : MPC_RMU_REG_LIST_DCN3AG(1),
520 : MPC_DWB_MUX_REG_LIST_DCN3_0(0),
521 : };
522 :
523 : static const struct dcn30_mpc_shift mpc_shift = {
524 : MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
525 : };
526 :
527 : static const struct dcn30_mpc_mask mpc_mask = {
528 : MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
529 : };
530 :
531 : #define optc_regs(id)\
532 : [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
533 :
534 :
535 : static const struct dcn_optc_registers optc_regs[] = {
536 : optc_regs(0),
537 : optc_regs(1),
538 : optc_regs(2),
539 : optc_regs(3),
540 : };
541 :
542 : static const struct dcn_optc_shift optc_shift = {
543 : OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
544 : };
545 :
546 : static const struct dcn_optc_mask optc_mask = {
547 : OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
548 : };
549 :
550 : #define hubp_regs(id)\
551 : [id] = {\
552 : HUBP_REG_LIST_DCN30(id)\
553 : }
554 :
555 : static const struct dcn_hubp2_registers hubp_regs[] = {
556 : hubp_regs(0),
557 : hubp_regs(1),
558 : hubp_regs(2),
559 : hubp_regs(3),
560 : };
561 :
562 : static const struct dcn_hubp2_shift hubp_shift = {
563 : HUBP_MASK_SH_LIST_DCN30(__SHIFT)
564 : };
565 :
566 : static const struct dcn_hubp2_mask hubp_mask = {
567 : HUBP_MASK_SH_LIST_DCN30(_MASK)
568 : };
569 :
570 : static const struct dcn_hubbub_registers hubbub_reg = {
571 : HUBBUB_REG_LIST_DCN301(0)
572 : };
573 :
574 : static const struct dcn_hubbub_shift hubbub_shift = {
575 : HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
576 : };
577 :
578 : static const struct dcn_hubbub_mask hubbub_mask = {
579 : HUBBUB_MASK_SH_LIST_DCN301(_MASK)
580 : };
581 :
582 : static const struct dccg_registers dccg_regs = {
583 : DCCG_REG_LIST_DCN301()
584 : };
585 :
586 : static const struct dccg_shift dccg_shift = {
587 : DCCG_MASK_SH_LIST_DCN301(__SHIFT)
588 : };
589 :
590 : static const struct dccg_mask dccg_mask = {
591 : DCCG_MASK_SH_LIST_DCN301(_MASK)
592 : };
593 :
594 : static const struct dce_hwseq_registers hwseq_reg = {
595 : HWSEQ_DCN301_REG_LIST()
596 : };
597 :
598 : static const struct dce_hwseq_shift hwseq_shift = {
599 : HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
600 : };
601 :
602 : static const struct dce_hwseq_mask hwseq_mask = {
603 : HWSEQ_DCN301_MASK_SH_LIST(_MASK)
604 : };
605 : #define vmid_regs(id)\
606 : [id] = {\
607 : DCN20_VMID_REG_LIST(id)\
608 : }
609 :
610 : static const struct dcn_vmid_registers vmid_regs[] = {
611 : vmid_regs(0),
612 : vmid_regs(1),
613 : vmid_regs(2),
614 : vmid_regs(3),
615 : vmid_regs(4),
616 : vmid_regs(5),
617 : vmid_regs(6),
618 : vmid_regs(7),
619 : vmid_regs(8),
620 : vmid_regs(9),
621 : vmid_regs(10),
622 : vmid_regs(11),
623 : vmid_regs(12),
624 : vmid_regs(13),
625 : vmid_regs(14),
626 : vmid_regs(15)
627 : };
628 :
629 : static const struct dcn20_vmid_shift vmid_shifts = {
630 : DCN20_VMID_MASK_SH_LIST(__SHIFT)
631 : };
632 :
633 : static const struct dcn20_vmid_mask vmid_masks = {
634 : DCN20_VMID_MASK_SH_LIST(_MASK)
635 : };
636 :
637 : static const struct resource_caps res_cap_dcn301 = {
638 : .num_timing_generator = 4,
639 : .num_opp = 4,
640 : .num_video_plane = 4,
641 : .num_audio = 4,
642 : .num_stream_encoder = 4,
643 : .num_pll = 4,
644 : .num_dwb = 1,
645 : .num_ddc = 4,
646 : .num_vmid = 16,
647 : .num_mpc_3dlut = 2,
648 : .num_dsc = 3,
649 : };
650 :
651 : static const struct dc_plane_cap plane_cap = {
652 : .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
653 : .blends_with_above = true,
654 : .blends_with_below = true,
655 : .per_pixel_alpha = true,
656 :
657 : .pixel_format_support = {
658 : .argb8888 = true,
659 : .nv12 = true,
660 : .fp16 = true,
661 : .p010 = true,
662 : .ayuv = false,
663 : },
664 :
665 : .max_upscale_factor = {
666 : .argb8888 = 16000,
667 : .nv12 = 16000,
668 : .fp16 = 16000
669 : },
670 :
671 : /* 6:1 downscaling ratio: 1000/6 = 166.666 */
672 : .max_downscale_factor = {
673 : .argb8888 = 167,
674 : .nv12 = 167,
675 : .fp16 = 167
676 : },
677 : 64,
678 : 64
679 : };
680 :
681 : static const struct dc_debug_options debug_defaults_drv = {
682 : .disable_dmcu = true,
683 : .force_abm_enable = false,
684 : .timing_trace = false,
685 : .clock_trace = true,
686 : .disable_dpp_power_gate = false,
687 : .disable_hubp_power_gate = false,
688 : .disable_clock_gate = true,
689 : .disable_pplib_clock_request = true,
690 : .disable_pplib_wm_range = true,
691 : .pipe_split_policy = MPC_SPLIT_AVOID,
692 : .force_single_disp_pipe_split = false,
693 : .disable_dcc = DCC_ENABLE,
694 : .vsr_support = true,
695 : .performance_trace = false,
696 : .max_downscale_src_width = 7680,/*upto 8K*/
697 : .scl_reset_length10 = true,
698 : .sanity_checks = false,
699 : .underflow_assert_delay_us = 0xFFFFFFFF,
700 : .dwb_fi_phase = -1, // -1 = disable
701 : .dmub_command_table = true,
702 : .use_max_lb = false,
703 : };
704 :
705 : static const struct dc_debug_options debug_defaults_diags = {
706 : .disable_dmcu = true,
707 : .force_abm_enable = false,
708 : .timing_trace = true,
709 : .clock_trace = true,
710 : .disable_dpp_power_gate = false,
711 : .disable_hubp_power_gate = false,
712 : .disable_clock_gate = true,
713 : .disable_pplib_clock_request = true,
714 : .disable_pplib_wm_range = true,
715 : .disable_stutter = true,
716 : .scl_reset_length10 = true,
717 : .dwb_fi_phase = -1, // -1 = disable
718 : .dmub_command_table = true,
719 : .use_max_lb = false,
720 : };
721 :
722 : static void dcn301_dpp_destroy(struct dpp **dpp)
723 : {
724 0 : kfree(TO_DCN20_DPP(*dpp));
725 0 : *dpp = NULL;
726 : }
727 :
728 0 : static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
729 : {
730 0 : struct dcn3_dpp *dpp =
731 : kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
732 :
733 0 : if (!dpp)
734 : return NULL;
735 :
736 0 : if (dpp3_construct(dpp, ctx, inst,
737 : &dpp_regs[inst], &tf_shift, &tf_mask))
738 0 : return &dpp->base;
739 :
740 0 : BREAK_TO_DEBUGGER();
741 0 : kfree(dpp);
742 0 : return NULL;
743 : }
744 0 : static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
745 : uint32_t inst)
746 : {
747 0 : struct dcn20_opp *opp =
748 : kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
749 :
750 0 : if (!opp) {
751 0 : BREAK_TO_DEBUGGER();
752 0 : return NULL;
753 : }
754 :
755 0 : dcn20_opp_construct(opp, ctx, inst,
756 : &opp_regs[inst], &opp_shift, &opp_mask);
757 0 : return &opp->base;
758 : }
759 :
760 0 : static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
761 : {
762 0 : struct aux_engine_dce110 *aux_engine =
763 : kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
764 :
765 0 : if (!aux_engine)
766 : return NULL;
767 :
768 0 : dce110_aux_engine_construct(aux_engine, ctx, inst,
769 : SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
770 : &aux_engine_regs[inst],
771 : &aux_mask,
772 : &aux_shift,
773 0 : ctx->dc->caps.extended_aux_timeout_support);
774 :
775 0 : return &aux_engine->base;
776 : }
777 : #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
778 :
779 : static const struct dce_i2c_registers i2c_hw_regs[] = {
780 : i2c_inst_regs(1),
781 : i2c_inst_regs(2),
782 : i2c_inst_regs(3),
783 : i2c_inst_regs(4),
784 : };
785 :
786 : static const struct dce_i2c_shift i2c_shifts = {
787 : I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
788 : };
789 :
790 : static const struct dce_i2c_mask i2c_masks = {
791 : I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
792 : };
793 :
794 0 : static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
795 : {
796 0 : struct dce_i2c_hw *dce_i2c_hw =
797 : kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
798 :
799 0 : if (!dce_i2c_hw)
800 : return NULL;
801 :
802 0 : dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
803 : &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
804 :
805 0 : return dce_i2c_hw;
806 : }
807 0 : static struct mpc *dcn301_mpc_create(
808 : struct dc_context *ctx,
809 : int num_mpcc,
810 : int num_rmu)
811 : {
812 0 : struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
813 : GFP_KERNEL);
814 :
815 0 : if (!mpc30)
816 : return NULL;
817 :
818 0 : dcn30_mpc_construct(mpc30, ctx,
819 : &mpc_regs,
820 : &mpc_shift,
821 : &mpc_mask,
822 : num_mpcc,
823 : num_rmu);
824 :
825 0 : return &mpc30->base;
826 : }
827 :
828 0 : static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
829 : {
830 : int i;
831 :
832 0 : struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
833 : GFP_KERNEL);
834 :
835 0 : if (!hubbub3)
836 : return NULL;
837 :
838 0 : hubbub301_construct(hubbub3, ctx,
839 : &hubbub_reg,
840 : &hubbub_shift,
841 : &hubbub_mask);
842 :
843 :
844 0 : for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
845 0 : struct dcn20_vmid *vmid = &hubbub3->vmid[i];
846 :
847 0 : vmid->ctx = ctx;
848 :
849 0 : vmid->regs = &vmid_regs[i];
850 0 : vmid->shifts = &vmid_shifts;
851 0 : vmid->masks = &vmid_masks;
852 : }
853 :
854 0 : hubbub3->num_vmid = res_cap_dcn301.num_vmid;
855 :
856 0 : return &hubbub3->base;
857 : }
858 :
859 0 : static struct timing_generator *dcn301_timing_generator_create(
860 : struct dc_context *ctx, uint32_t instance)
861 : {
862 0 : struct optc *tgn10 =
863 : kzalloc(sizeof(struct optc), GFP_KERNEL);
864 :
865 0 : if (!tgn10)
866 : return NULL;
867 :
868 0 : tgn10->base.inst = instance;
869 0 : tgn10->base.ctx = ctx;
870 :
871 0 : tgn10->tg_regs = &optc_regs[instance];
872 0 : tgn10->tg_shift = &optc_shift;
873 0 : tgn10->tg_mask = &optc_mask;
874 :
875 0 : dcn30_timing_generator_init(tgn10);
876 :
877 0 : return &tgn10->base;
878 : }
879 :
880 : static const struct encoder_feature_support link_enc_feature = {
881 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
882 : .max_hdmi_pixel_clock = 600000,
883 : .hdmi_ycbcr420_supported = true,
884 : .dp_ycbcr420_supported = true,
885 : .fec_supported = true,
886 : .flags.bits.IS_HBR2_CAPABLE = true,
887 : .flags.bits.IS_HBR3_CAPABLE = true,
888 : .flags.bits.IS_TPS3_CAPABLE = true,
889 : .flags.bits.IS_TPS4_CAPABLE = true
890 : };
891 :
892 0 : static struct link_encoder *dcn301_link_encoder_create(
893 : struct dc_context *ctx,
894 : const struct encoder_init_data *enc_init_data)
895 : {
896 0 : struct dcn20_link_encoder *enc20 =
897 : kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
898 :
899 0 : if (!enc20)
900 : return NULL;
901 :
902 0 : dcn301_link_encoder_construct(enc20,
903 : enc_init_data,
904 : &link_enc_feature,
905 0 : &link_enc_regs[enc_init_data->transmitter],
906 0 : &link_enc_aux_regs[enc_init_data->channel - 1],
907 0 : &link_enc_hpd_regs[enc_init_data->hpd_source],
908 : &le_shift,
909 : &le_mask);
910 :
911 0 : return &enc20->enc10.base;
912 : }
913 :
914 0 : static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
915 : {
916 0 : struct dcn301_panel_cntl *panel_cntl =
917 : kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
918 :
919 0 : if (!panel_cntl)
920 : return NULL;
921 :
922 0 : dcn301_panel_cntl_construct(panel_cntl,
923 : init_data,
924 0 : &panel_cntl_regs[init_data->inst],
925 : &panel_cntl_shift,
926 : &panel_cntl_mask);
927 :
928 0 : return &panel_cntl->base;
929 : }
930 :
931 :
932 : #define CTX ctx
933 :
934 : #define REG(reg_name) \
935 : (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
936 :
937 : static uint32_t read_pipe_fuses(struct dc_context *ctx)
938 : {
939 0 : uint32_t value = REG_READ(CC_DC_PIPE_DIS);
940 : /* RV1 support max 4 pipes */
941 0 : value = value & 0xf;
942 : return value;
943 : }
944 :
945 :
946 0 : static void read_dce_straps(
947 : struct dc_context *ctx,
948 : struct resource_straps *straps)
949 : {
950 0 : generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
951 : FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
952 :
953 0 : }
954 :
955 0 : static struct audio *dcn301_create_audio(
956 : struct dc_context *ctx, unsigned int inst)
957 : {
958 0 : return dce_audio_create(ctx, inst,
959 : &audio_regs[inst], &audio_shift, &audio_mask);
960 : }
961 :
962 0 : static struct vpg *dcn301_vpg_create(
963 : struct dc_context *ctx,
964 : uint32_t inst)
965 : {
966 0 : struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
967 :
968 0 : if (!vpg3)
969 : return NULL;
970 :
971 0 : vpg3_construct(vpg3, ctx, inst,
972 : &vpg_regs[inst],
973 : &vpg_shift,
974 : &vpg_mask);
975 :
976 0 : return &vpg3->base;
977 : }
978 :
979 0 : static struct afmt *dcn301_afmt_create(
980 : struct dc_context *ctx,
981 : uint32_t inst)
982 : {
983 0 : struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
984 :
985 0 : if (!afmt3)
986 : return NULL;
987 :
988 0 : afmt3_construct(afmt3, ctx, inst,
989 : &afmt_regs[inst],
990 : &afmt_shift,
991 : &afmt_mask);
992 :
993 0 : return &afmt3->base;
994 : }
995 :
996 0 : static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
997 : struct dc_context *ctx)
998 : {
999 : struct dcn10_stream_encoder *enc1;
1000 : struct vpg *vpg;
1001 : struct afmt *afmt;
1002 : int vpg_inst;
1003 : int afmt_inst;
1004 :
1005 : /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1006 0 : if (eng_id <= ENGINE_ID_DIGF) {
1007 0 : vpg_inst = eng_id;
1008 0 : afmt_inst = eng_id;
1009 : } else
1010 : return NULL;
1011 :
1012 0 : enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1013 0 : vpg = dcn301_vpg_create(ctx, vpg_inst);
1014 0 : afmt = dcn301_afmt_create(ctx, afmt_inst);
1015 :
1016 0 : if (!enc1 || !vpg || !afmt) {
1017 0 : kfree(enc1);
1018 0 : kfree(vpg);
1019 0 : kfree(afmt);
1020 0 : return NULL;
1021 : }
1022 :
1023 0 : dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1024 : eng_id, vpg, afmt,
1025 : &stream_enc_regs[eng_id],
1026 : &se_shift, &se_mask);
1027 :
1028 0 : return &enc1->base;
1029 : }
1030 :
1031 0 : static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1032 : {
1033 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1034 :
1035 0 : if (hws) {
1036 0 : hws->ctx = ctx;
1037 0 : hws->regs = &hwseq_reg;
1038 0 : hws->shifts = &hwseq_shift;
1039 0 : hws->masks = &hwseq_mask;
1040 : }
1041 0 : return hws;
1042 : }
1043 : static const struct resource_create_funcs res_create_funcs = {
1044 : .read_dce_straps = read_dce_straps,
1045 : .create_audio = dcn301_create_audio,
1046 : .create_stream_encoder = dcn301_stream_encoder_create,
1047 : .create_hwseq = dcn301_hwseq_create,
1048 : };
1049 :
1050 : static const struct resource_create_funcs res_create_maximus_funcs = {
1051 : .read_dce_straps = NULL,
1052 : .create_audio = NULL,
1053 : .create_stream_encoder = NULL,
1054 : .create_hwseq = dcn301_hwseq_create,
1055 : };
1056 :
1057 0 : static void dcn301_destruct(struct dcn301_resource_pool *pool)
1058 : {
1059 : unsigned int i;
1060 :
1061 0 : for (i = 0; i < pool->base.stream_enc_count; i++) {
1062 0 : if (pool->base.stream_enc[i] != NULL) {
1063 0 : if (pool->base.stream_enc[i]->vpg != NULL) {
1064 0 : kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1065 0 : pool->base.stream_enc[i]->vpg = NULL;
1066 : }
1067 0 : if (pool->base.stream_enc[i]->afmt != NULL) {
1068 0 : kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1069 0 : pool->base.stream_enc[i]->afmt = NULL;
1070 : }
1071 0 : kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1072 0 : pool->base.stream_enc[i] = NULL;
1073 : }
1074 : }
1075 :
1076 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1077 0 : if (pool->base.dscs[i] != NULL)
1078 0 : dcn20_dsc_destroy(&pool->base.dscs[i]);
1079 : }
1080 :
1081 0 : if (pool->base.mpc != NULL) {
1082 0 : kfree(TO_DCN20_MPC(pool->base.mpc));
1083 0 : pool->base.mpc = NULL;
1084 : }
1085 0 : if (pool->base.hubbub != NULL) {
1086 0 : kfree(pool->base.hubbub);
1087 0 : pool->base.hubbub = NULL;
1088 : }
1089 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1090 0 : if (pool->base.dpps[i] != NULL)
1091 0 : dcn301_dpp_destroy(&pool->base.dpps[i]);
1092 :
1093 0 : if (pool->base.ipps[i] != NULL)
1094 0 : pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1095 :
1096 0 : if (pool->base.hubps[i] != NULL) {
1097 0 : kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1098 0 : pool->base.hubps[i] = NULL;
1099 : }
1100 :
1101 0 : if (pool->base.irqs != NULL) {
1102 0 : dal_irq_service_destroy(&pool->base.irqs);
1103 : }
1104 : }
1105 :
1106 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1107 0 : if (pool->base.engines[i] != NULL)
1108 0 : dce110_engine_destroy(&pool->base.engines[i]);
1109 0 : if (pool->base.hw_i2cs[i] != NULL) {
1110 0 : kfree(pool->base.hw_i2cs[i]);
1111 0 : pool->base.hw_i2cs[i] = NULL;
1112 : }
1113 0 : if (pool->base.sw_i2cs[i] != NULL) {
1114 0 : kfree(pool->base.sw_i2cs[i]);
1115 0 : pool->base.sw_i2cs[i] = NULL;
1116 : }
1117 : }
1118 :
1119 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1120 0 : if (pool->base.opps[i] != NULL)
1121 0 : pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1122 : }
1123 :
1124 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1125 0 : if (pool->base.timing_generators[i] != NULL) {
1126 0 : kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1127 0 : pool->base.timing_generators[i] = NULL;
1128 : }
1129 : }
1130 :
1131 0 : for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1132 0 : if (pool->base.dwbc[i] != NULL) {
1133 0 : kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1134 0 : pool->base.dwbc[i] = NULL;
1135 : }
1136 0 : if (pool->base.mcif_wb[i] != NULL) {
1137 0 : kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1138 0 : pool->base.mcif_wb[i] = NULL;
1139 : }
1140 : }
1141 :
1142 0 : for (i = 0; i < pool->base.audio_count; i++) {
1143 0 : if (pool->base.audios[i])
1144 0 : dce_aud_destroy(&pool->base.audios[i]);
1145 : }
1146 :
1147 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1148 0 : if (pool->base.clock_sources[i] != NULL) {
1149 0 : dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1150 0 : pool->base.clock_sources[i] = NULL;
1151 : }
1152 : }
1153 :
1154 0 : for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1155 0 : if (pool->base.mpc_lut[i] != NULL) {
1156 0 : dc_3dlut_func_release(pool->base.mpc_lut[i]);
1157 0 : pool->base.mpc_lut[i] = NULL;
1158 : }
1159 0 : if (pool->base.mpc_shaper[i] != NULL) {
1160 0 : dc_transfer_func_release(pool->base.mpc_shaper[i]);
1161 0 : pool->base.mpc_shaper[i] = NULL;
1162 : }
1163 : }
1164 :
1165 0 : if (pool->base.dp_clock_source != NULL) {
1166 0 : dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1167 0 : pool->base.dp_clock_source = NULL;
1168 : }
1169 :
1170 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1171 0 : if (pool->base.multiple_abms[i] != NULL)
1172 0 : dce_abm_destroy(&pool->base.multiple_abms[i]);
1173 : }
1174 :
1175 0 : if (pool->base.dccg != NULL)
1176 0 : dcn_dccg_destroy(&pool->base.dccg);
1177 0 : }
1178 :
1179 0 : static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1180 : {
1181 0 : struct dcn20_hubp *hubp2 =
1182 : kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1183 :
1184 0 : if (!hubp2)
1185 : return NULL;
1186 :
1187 0 : if (hubp3_construct(hubp2, ctx, inst,
1188 : &hubp_regs[inst], &hubp_shift, &hubp_mask))
1189 0 : return &hubp2->base;
1190 :
1191 0 : BREAK_TO_DEBUGGER();
1192 0 : kfree(hubp2);
1193 0 : return NULL;
1194 : }
1195 :
1196 0 : static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1197 : {
1198 : int i;
1199 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
1200 :
1201 0 : for (i = 0; i < pipe_count; i++) {
1202 0 : struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1203 : GFP_KERNEL);
1204 :
1205 0 : if (!dwbc30) {
1206 0 : dm_error("DC: failed to create dwbc30!\n");
1207 : return false;
1208 : }
1209 :
1210 0 : dcn30_dwbc_construct(dwbc30, ctx,
1211 : &dwbc30_regs[i],
1212 : &dwbc30_shift,
1213 : &dwbc30_mask,
1214 : i);
1215 :
1216 0 : pool->dwbc[i] = &dwbc30->base;
1217 : }
1218 : return true;
1219 : }
1220 :
1221 0 : static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1222 : {
1223 : int i;
1224 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
1225 :
1226 0 : for (i = 0; i < pipe_count; i++) {
1227 0 : struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1228 : GFP_KERNEL);
1229 :
1230 0 : if (!mcif_wb30) {
1231 0 : dm_error("DC: failed to create mcif_wb30!\n");
1232 : return false;
1233 : }
1234 :
1235 0 : dcn30_mmhubbub_construct(mcif_wb30, ctx,
1236 : &mcif_wb30_regs[i],
1237 : &mcif_wb30_shift,
1238 : &mcif_wb30_mask,
1239 : i);
1240 :
1241 0 : pool->mcif_wb[i] = &mcif_wb30->base;
1242 : }
1243 : return true;
1244 : }
1245 :
1246 0 : static struct display_stream_compressor *dcn301_dsc_create(
1247 : struct dc_context *ctx, uint32_t inst)
1248 : {
1249 0 : struct dcn20_dsc *dsc =
1250 : kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1251 :
1252 0 : if (!dsc) {
1253 0 : BREAK_TO_DEBUGGER();
1254 0 : return NULL;
1255 : }
1256 :
1257 0 : dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1258 0 : return &dsc->base;
1259 : }
1260 :
1261 :
1262 0 : static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1263 : {
1264 0 : struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1265 :
1266 0 : dcn301_destruct(dcn301_pool);
1267 0 : kfree(dcn301_pool);
1268 0 : *pool = NULL;
1269 0 : }
1270 :
1271 0 : static struct clock_source *dcn301_clock_source_create(
1272 : struct dc_context *ctx,
1273 : struct dc_bios *bios,
1274 : enum clock_source_id id,
1275 : const struct dce110_clk_src_regs *regs,
1276 : bool dp_clk_src)
1277 : {
1278 0 : struct dce110_clk_src *clk_src =
1279 : kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1280 :
1281 0 : if (!clk_src)
1282 : return NULL;
1283 :
1284 0 : if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1285 : regs, &cs_shift, &cs_mask)) {
1286 0 : clk_src->base.dp_clk_src = dp_clk_src;
1287 0 : return &clk_src->base;
1288 : }
1289 :
1290 0 : BREAK_TO_DEBUGGER();
1291 0 : return NULL;
1292 : }
1293 :
1294 : static struct dc_cap_funcs cap_funcs = {
1295 : .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1296 : };
1297 :
1298 :
1299 : static bool is_soc_bounding_box_valid(struct dc *dc)
1300 : {
1301 0 : uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1302 :
1303 0 : if (ASICREV_IS_VANGOGH(hw_internal_rev))
1304 : return true;
1305 :
1306 : return false;
1307 : }
1308 :
1309 0 : static bool init_soc_bounding_box(struct dc *dc,
1310 : struct dcn301_resource_pool *pool)
1311 : {
1312 0 : struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1313 0 : struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1314 :
1315 : DC_LOGGER_INIT(dc->ctx->logger);
1316 :
1317 0 : if (!is_soc_bounding_box_valid(dc)) {
1318 0 : DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1319 : return false;
1320 : }
1321 :
1322 0 : loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1323 0 : loaded_ip->max_num_dpp = pool->base.pipe_count;
1324 0 : DC_FP_START();
1325 0 : dcn20_patch_bounding_box(dc, loaded_bb);
1326 0 : DC_FP_END();
1327 :
1328 0 : if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1329 0 : struct bp_soc_bb_info bb_info = {0};
1330 :
1331 0 : if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1332 0 : DC_FP_START();
1333 0 : dcn301_fpu_init_soc_bounding_box(bb_info);
1334 0 : DC_FP_END();
1335 : }
1336 : }
1337 :
1338 : return true;
1339 : }
1340 :
1341 :
1342 0 : static void set_wm_ranges(
1343 : struct pp_smu_funcs *pp_smu,
1344 : struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1345 : {
1346 0 : struct pp_smu_wm_range_sets ranges = {0};
1347 : int i;
1348 :
1349 : ranges.num_reader_wm_sets = 0;
1350 :
1351 0 : if (loaded_bb->num_states == 1) {
1352 : ranges.reader_wm_sets[0].wm_inst = 0;
1353 : ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1354 0 : ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1355 : ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1356 0 : ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1357 :
1358 0 : ranges.num_reader_wm_sets = 1;
1359 0 : } else if (loaded_bb->num_states > 1) {
1360 0 : for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1361 0 : ranges.reader_wm_sets[i].wm_inst = i;
1362 0 : ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1363 0 : ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1364 0 : DC_FP_START();
1365 0 : dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1366 0 : DC_FP_END();
1367 0 : ranges.num_reader_wm_sets = i + 1;
1368 : }
1369 :
1370 0 : ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1371 0 : ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1372 : }
1373 :
1374 0 : ranges.num_writer_wm_sets = 1;
1375 :
1376 0 : ranges.writer_wm_sets[0].wm_inst = 0;
1377 0 : ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1378 0 : ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1379 0 : ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1380 0 : ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1381 :
1382 : /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1383 0 : pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1384 0 : }
1385 :
1386 0 : static void dcn301_calculate_wm_and_dlg(
1387 : struct dc *dc, struct dc_state *context,
1388 : display_e2e_pipe_params_st *pipes,
1389 : int pipe_cnt,
1390 : int vlevel)
1391 : {
1392 0 : DC_FP_START();
1393 0 : dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1394 0 : DC_FP_END();
1395 0 : }
1396 :
1397 : static struct resource_funcs dcn301_res_pool_funcs = {
1398 : .destroy = dcn301_destroy_resource_pool,
1399 : .link_enc_create = dcn301_link_encoder_create,
1400 : .panel_cntl_create = dcn301_panel_cntl_create,
1401 : .validate_bandwidth = dcn30_validate_bandwidth,
1402 : .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1403 : .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1404 : .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1405 : .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1406 : .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1407 : .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1408 : .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1409 : .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1410 : .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1411 : .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1412 : .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1413 : .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1414 : .update_bw_bounding_box = dcn301_update_bw_bounding_box
1415 : };
1416 :
1417 0 : static bool dcn301_resource_construct(
1418 : uint8_t num_virtual_links,
1419 : struct dc *dc,
1420 : struct dcn301_resource_pool *pool)
1421 : {
1422 : int i, j;
1423 0 : struct dc_context *ctx = dc->ctx;
1424 : struct irq_service_init_data init_data;
1425 0 : uint32_t pipe_fuses = read_pipe_fuses(ctx);
1426 0 : uint32_t num_pipes = 0;
1427 :
1428 : DC_LOGGER_INIT(dc->ctx->logger);
1429 :
1430 0 : ctx->dc_bios->regs = &bios_regs;
1431 :
1432 0 : pool->base.res_cap = &res_cap_dcn301;
1433 :
1434 0 : pool->base.funcs = &dcn301_res_pool_funcs;
1435 :
1436 : /*************************************************
1437 : * Resource + asic cap harcoding *
1438 : *************************************************/
1439 0 : pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1440 0 : pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1441 0 : pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1442 0 : dc->caps.max_downscale_ratio = 600;
1443 0 : dc->caps.i2c_speed_in_khz = 100;
1444 0 : dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1445 0 : dc->caps.max_cursor_size = 256;
1446 0 : dc->caps.min_horizontal_blanking_period = 80;
1447 0 : dc->caps.dmdata_alloc_size = 2048;
1448 0 : dc->caps.max_slave_planes = 1;
1449 0 : dc->caps.max_slave_yuv_planes = 1;
1450 0 : dc->caps.max_slave_rgb_planes = 1;
1451 0 : dc->caps.is_apu = true;
1452 0 : dc->caps.post_blend_color_processing = true;
1453 0 : dc->caps.force_dp_tps4_for_cp2520 = true;
1454 0 : dc->caps.extended_aux_timeout_support = true;
1455 0 : dc->caps.dmcub_support = true;
1456 :
1457 : /* Color pipeline capabilities */
1458 0 : dc->caps.color.dpp.dcn_arch = 1;
1459 0 : dc->caps.color.dpp.input_lut_shared = 0;
1460 0 : dc->caps.color.dpp.icsc = 1;
1461 0 : dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1462 0 : dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1463 0 : dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1464 0 : dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1465 0 : dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1466 0 : dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1467 0 : dc->caps.color.dpp.post_csc = 1;
1468 0 : dc->caps.color.dpp.gamma_corr = 1;
1469 0 : dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1470 :
1471 0 : dc->caps.color.dpp.hw_3d_lut = 1;
1472 0 : dc->caps.color.dpp.ogam_ram = 1;
1473 : // no OGAM ROM on DCN301
1474 0 : dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1475 0 : dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1476 0 : dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1477 0 : dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1478 0 : dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1479 0 : dc->caps.color.dpp.ocsc = 0;
1480 :
1481 0 : dc->caps.color.mpc.gamut_remap = 1;
1482 0 : dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1483 0 : dc->caps.color.mpc.ogam_ram = 1;
1484 0 : dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1485 0 : dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1486 0 : dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1487 0 : dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1488 0 : dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1489 0 : dc->caps.color.mpc.ocsc = 1;
1490 :
1491 : /* read VBIOS LTTPR caps */
1492 0 : if (ctx->dc_bios->funcs->get_lttpr_caps) {
1493 : enum bp_result bp_query_result;
1494 0 : uint8_t is_vbios_lttpr_enable = 0;
1495 :
1496 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1497 0 : dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1498 : }
1499 :
1500 0 : if (ctx->dc_bios->funcs->get_lttpr_interop) {
1501 : enum bp_result bp_query_result;
1502 0 : uint8_t is_vbios_interop_enabled = 0;
1503 :
1504 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1505 0 : dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1506 : }
1507 :
1508 0 : if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1509 0 : dc->debug = debug_defaults_drv;
1510 0 : else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1511 0 : dc->debug = debug_defaults_diags;
1512 : } else
1513 0 : dc->debug = debug_defaults_diags;
1514 : // Init the vm_helper
1515 0 : if (dc->vm_helper)
1516 0 : vm_helper_init(dc->vm_helper, 16);
1517 :
1518 : /*************************************************
1519 : * Create resources *
1520 : *************************************************/
1521 :
1522 : /* Clock Sources for Pixel Clock*/
1523 0 : pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1524 0 : dcn301_clock_source_create(ctx, ctx->dc_bios,
1525 : CLOCK_SOURCE_COMBO_PHY_PLL0,
1526 : &clk_src_regs[0], false);
1527 0 : pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1528 0 : dcn301_clock_source_create(ctx, ctx->dc_bios,
1529 : CLOCK_SOURCE_COMBO_PHY_PLL1,
1530 : &clk_src_regs[1], false);
1531 0 : pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1532 0 : dcn301_clock_source_create(ctx, ctx->dc_bios,
1533 : CLOCK_SOURCE_COMBO_PHY_PLL2,
1534 : &clk_src_regs[2], false);
1535 0 : pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1536 0 : dcn301_clock_source_create(ctx, ctx->dc_bios,
1537 : CLOCK_SOURCE_COMBO_PHY_PLL3,
1538 : &clk_src_regs[3], false);
1539 :
1540 0 : pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1541 :
1542 : /* todo: not reuse phy_pll registers */
1543 0 : pool->base.dp_clock_source =
1544 0 : dcn301_clock_source_create(ctx, ctx->dc_bios,
1545 : CLOCK_SOURCE_ID_DP_DTO,
1546 : &clk_src_regs[0], true);
1547 :
1548 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1549 0 : if (pool->base.clock_sources[i] == NULL) {
1550 0 : dm_error("DC: failed to create clock sources!\n");
1551 0 : BREAK_TO_DEBUGGER();
1552 0 : goto create_fail;
1553 : }
1554 : }
1555 :
1556 : /* DCCG */
1557 0 : pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1558 0 : if (pool->base.dccg == NULL) {
1559 0 : dm_error("DC: failed to create dccg!\n");
1560 0 : BREAK_TO_DEBUGGER();
1561 0 : goto create_fail;
1562 : }
1563 :
1564 0 : init_soc_bounding_box(dc, pool);
1565 :
1566 0 : if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1567 0 : set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1568 :
1569 0 : num_pipes = dcn3_01_ip.max_num_dpp;
1570 :
1571 0 : for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1572 0 : if (pipe_fuses & 1 << i)
1573 0 : num_pipes--;
1574 0 : dcn3_01_ip.max_num_dpp = num_pipes;
1575 0 : dcn3_01_ip.max_num_otg = num_pipes;
1576 :
1577 :
1578 0 : dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1579 :
1580 : /* IRQ */
1581 0 : init_data.ctx = dc->ctx;
1582 0 : pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1583 0 : if (!pool->base.irqs)
1584 : goto create_fail;
1585 :
1586 : /* HUBBUB */
1587 0 : pool->base.hubbub = dcn301_hubbub_create(ctx);
1588 0 : if (pool->base.hubbub == NULL) {
1589 0 : BREAK_TO_DEBUGGER();
1590 0 : dm_error("DC: failed to create hubbub!\n");
1591 0 : goto create_fail;
1592 : }
1593 :
1594 : j = 0;
1595 : /* HUBPs, DPPs, OPPs and TGs */
1596 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1597 :
1598 : /* if pipe is disabled, skip instance of HW pipe,
1599 : * i.e, skip ASIC register instance
1600 : */
1601 0 : if ((pipe_fuses & (1 << i)) != 0) {
1602 0 : DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1603 0 : continue;
1604 : }
1605 :
1606 0 : pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1607 0 : if (pool->base.hubps[j] == NULL) {
1608 0 : BREAK_TO_DEBUGGER();
1609 0 : dm_error(
1610 : "DC: failed to create hubps!\n");
1611 0 : goto create_fail;
1612 : }
1613 :
1614 0 : pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1615 0 : if (pool->base.dpps[j] == NULL) {
1616 0 : BREAK_TO_DEBUGGER();
1617 0 : dm_error(
1618 : "DC: failed to create dpps!\n");
1619 0 : goto create_fail;
1620 : }
1621 :
1622 0 : pool->base.opps[j] = dcn301_opp_create(ctx, i);
1623 0 : if (pool->base.opps[j] == NULL) {
1624 0 : BREAK_TO_DEBUGGER();
1625 0 : dm_error(
1626 : "DC: failed to create output pixel processor!\n");
1627 0 : goto create_fail;
1628 : }
1629 :
1630 0 : pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1631 0 : if (pool->base.timing_generators[j] == NULL) {
1632 0 : BREAK_TO_DEBUGGER();
1633 0 : dm_error("DC: failed to create tg!\n");
1634 0 : goto create_fail;
1635 : }
1636 0 : j++;
1637 : }
1638 0 : pool->base.timing_generator_count = j;
1639 0 : pool->base.pipe_count = j;
1640 0 : pool->base.mpcc_count = j;
1641 :
1642 : /* ABM (or ABMs for NV2x) */
1643 : /* TODO: */
1644 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1645 0 : pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1646 : &abm_regs[i],
1647 : &abm_shift,
1648 : &abm_mask);
1649 0 : if (pool->base.multiple_abms[i] == NULL) {
1650 0 : dm_error("DC: failed to create abm for pipe %d!\n", i);
1651 0 : BREAK_TO_DEBUGGER();
1652 0 : goto create_fail;
1653 : }
1654 : }
1655 :
1656 : /* MPC and DSC */
1657 0 : pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1658 0 : if (pool->base.mpc == NULL) {
1659 0 : BREAK_TO_DEBUGGER();
1660 0 : dm_error("DC: failed to create mpc!\n");
1661 0 : goto create_fail;
1662 : }
1663 :
1664 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1665 0 : pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1666 0 : if (pool->base.dscs[i] == NULL) {
1667 0 : BREAK_TO_DEBUGGER();
1668 0 : dm_error("DC: failed to create display stream compressor %d!\n", i);
1669 0 : goto create_fail;
1670 : }
1671 : }
1672 :
1673 : /* DWB and MMHUBBUB */
1674 0 : if (!dcn301_dwbc_create(ctx, &pool->base)) {
1675 0 : BREAK_TO_DEBUGGER();
1676 0 : dm_error("DC: failed to create dwbc!\n");
1677 0 : goto create_fail;
1678 : }
1679 :
1680 0 : if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1681 0 : BREAK_TO_DEBUGGER();
1682 0 : dm_error("DC: failed to create mcif_wb!\n");
1683 0 : goto create_fail;
1684 : }
1685 :
1686 : /* AUX and I2C */
1687 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1688 0 : pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1689 0 : if (pool->base.engines[i] == NULL) {
1690 0 : BREAK_TO_DEBUGGER();
1691 0 : dm_error(
1692 : "DC:failed to create aux engine!!\n");
1693 0 : goto create_fail;
1694 : }
1695 0 : pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1696 0 : if (pool->base.hw_i2cs[i] == NULL) {
1697 0 : BREAK_TO_DEBUGGER();
1698 0 : dm_error(
1699 : "DC:failed to create hw i2c!!\n");
1700 0 : goto create_fail;
1701 : }
1702 0 : pool->base.sw_i2cs[i] = NULL;
1703 : }
1704 :
1705 : /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1706 0 : if (!resource_construct(num_virtual_links, dc, &pool->base,
1707 0 : (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1708 : &res_create_funcs : &res_create_maximus_funcs)))
1709 : goto create_fail;
1710 :
1711 : /* HW Sequencer and Plane caps */
1712 0 : dcn301_hw_sequencer_construct(dc);
1713 :
1714 0 : dc->caps.max_planes = pool->base.pipe_count;
1715 :
1716 0 : for (i = 0; i < dc->caps.max_planes; ++i)
1717 0 : dc->caps.planes[i] = plane_cap;
1718 :
1719 0 : dc->cap_funcs = cap_funcs;
1720 :
1721 0 : return true;
1722 :
1723 : create_fail:
1724 :
1725 0 : dcn301_destruct(pool);
1726 :
1727 0 : return false;
1728 : }
1729 :
1730 0 : struct resource_pool *dcn301_create_resource_pool(
1731 : const struct dc_init_data *init_data,
1732 : struct dc *dc)
1733 : {
1734 0 : struct dcn301_resource_pool *pool =
1735 : kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1736 :
1737 0 : if (!pool)
1738 : return NULL;
1739 :
1740 0 : if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1741 0 : return &pool->base;
1742 :
1743 0 : BREAK_TO_DEBUGGER();
1744 0 : kfree(pool);
1745 0 : return NULL;
1746 : }
|
