Line data Source code
1 : /*
2 : * Copyright 2020 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "dcn302_init.h"
27 : #include "dcn302_resource.h"
28 : #include "dcn302_dccg.h"
29 : #include "irq/dcn302/irq_service_dcn302.h"
30 :
31 : #include "dcn30/dcn30_dio_link_encoder.h"
32 : #include "dcn30/dcn30_dio_stream_encoder.h"
33 : #include "dcn30/dcn30_dwb.h"
34 : #include "dcn30/dcn30_dpp.h"
35 : #include "dcn30/dcn30_hubbub.h"
36 : #include "dcn30/dcn30_hubp.h"
37 : #include "dcn30/dcn30_mmhubbub.h"
38 : #include "dcn30/dcn30_mpc.h"
39 : #include "dcn30/dcn30_opp.h"
40 : #include "dcn30/dcn30_optc.h"
41 : #include "dcn30/dcn30_resource.h"
42 :
43 : #include "dcn20/dcn20_dsc.h"
44 : #include "dcn20/dcn20_resource.h"
45 :
46 : #include "dml/dcn30/dcn30_fpu.h"
47 :
48 : #include "dcn10/dcn10_resource.h"
49 :
50 : #include "dce/dce_abm.h"
51 : #include "dce/dce_audio.h"
52 : #include "dce/dce_aux.h"
53 : #include "dce/dce_clock_source.h"
54 : #include "dce/dce_hwseq.h"
55 : #include "dce/dce_i2c_hw.h"
56 : #include "dce/dce_panel_cntl.h"
57 : #include "dce/dmub_abm.h"
58 : #include "dce/dmub_psr.h"
59 : #include "clk_mgr.h"
60 :
61 : #include "hw_sequencer_private.h"
62 : #include "reg_helper.h"
63 : #include "resource.h"
64 : #include "vm_helper.h"
65 :
66 : #include "dml/dcn302/dcn302_fpu.h"
67 :
68 : #include "dimgrey_cavefish_ip_offset.h"
69 : #include "dcn/dcn_3_0_2_offset.h"
70 : #include "dcn/dcn_3_0_2_sh_mask.h"
71 : #include "dpcs/dpcs_3_0_0_offset.h"
72 : #include "dpcs/dpcs_3_0_0_sh_mask.h"
73 : #include "nbio/nbio_7_4_offset.h"
74 : #include "amdgpu_socbb.h"
75 :
76 : #define DC_LOGGER_INIT(logger)
77 :
78 : static const struct dc_debug_options debug_defaults_drv = {
79 : .disable_dmcu = true,
80 : .force_abm_enable = false,
81 : .timing_trace = false,
82 : .clock_trace = true,
83 : .disable_pplib_clock_request = true,
84 : .pipe_split_policy = MPC_SPLIT_DYNAMIC,
85 : .force_single_disp_pipe_split = false,
86 : .disable_dcc = DCC_ENABLE,
87 : .vsr_support = true,
88 : .performance_trace = false,
89 : .max_downscale_src_width = 7680,/*upto 8K*/
90 : .disable_pplib_wm_range = false,
91 : .scl_reset_length10 = true,
92 : .sanity_checks = false,
93 : .underflow_assert_delay_us = 0xFFFFFFFF,
94 : .dwb_fi_phase = -1, // -1 = disable,
95 : .dmub_command_table = true,
96 : .use_max_lb = true
97 : };
98 :
99 : static const struct dc_debug_options debug_defaults_diags = {
100 : .disable_dmcu = true,
101 : .force_abm_enable = false,
102 : .timing_trace = true,
103 : .clock_trace = true,
104 : .disable_dpp_power_gate = true,
105 : .disable_hubp_power_gate = true,
106 : .disable_clock_gate = true,
107 : .disable_pplib_clock_request = true,
108 : .disable_pplib_wm_range = true,
109 : .disable_stutter = false,
110 : .scl_reset_length10 = true,
111 : .dwb_fi_phase = -1, // -1 = disable
112 : .dmub_command_table = true,
113 : .enable_tri_buf = true,
114 : .disable_psr = true,
115 : .use_max_lb = true
116 : };
117 :
118 : enum dcn302_clk_src_array_id {
119 : DCN302_CLK_SRC_PLL0,
120 : DCN302_CLK_SRC_PLL1,
121 : DCN302_CLK_SRC_PLL2,
122 : DCN302_CLK_SRC_PLL3,
123 : DCN302_CLK_SRC_PLL4,
124 : DCN302_CLK_SRC_TOTAL
125 : };
126 :
127 : static const struct resource_caps res_cap_dcn302 = {
128 : .num_timing_generator = 5,
129 : .num_opp = 5,
130 : .num_video_plane = 5,
131 : .num_audio = 5,
132 : .num_stream_encoder = 5,
133 : .num_dwb = 1,
134 : .num_ddc = 5,
135 : .num_vmid = 16,
136 : .num_mpc_3dlut = 2,
137 : .num_dsc = 5,
138 : };
139 :
140 : static const struct dc_plane_cap plane_cap = {
141 : .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
142 : .blends_with_above = true,
143 : .blends_with_below = true,
144 : .per_pixel_alpha = true,
145 : .pixel_format_support = {
146 : .argb8888 = true,
147 : .nv12 = true,
148 : .fp16 = true,
149 : .p010 = true,
150 : .ayuv = false,
151 : },
152 : .max_upscale_factor = {
153 : .argb8888 = 16000,
154 : .nv12 = 16000,
155 : .fp16 = 16000
156 : },
157 : /* 6:1 downscaling ratio: 1000/6 = 166.666 */
158 : .max_downscale_factor = {
159 : .argb8888 = 167,
160 : .nv12 = 167,
161 : .fp16 = 167
162 : },
163 : 16,
164 : 16
165 : };
166 :
167 : /* NBIO */
168 : #define NBIO_BASE_INNER(seg) \
169 : NBIO_BASE__INST0_SEG ## seg
170 :
171 : #define NBIO_BASE(seg) \
172 : NBIO_BASE_INNER(seg)
173 :
174 : #define NBIO_SR(reg_name)\
175 : .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
176 : mm ## reg_name
177 :
178 : /* DCN */
179 : #undef BASE_INNER
180 : #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
181 :
182 : #define BASE(seg) BASE_INNER(seg)
183 :
184 : #define SR(reg_name)\
185 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
186 :
187 : #define SF(reg_name, field_name, post_fix)\
188 : .field_name = reg_name ## __ ## field_name ## post_fix
189 :
190 : #define SRI(reg_name, block, id)\
191 : .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
192 :
193 : #define SRI2(reg_name, block, id)\
194 : .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
195 :
196 : #define SRII(reg_name, block, id)\
197 : .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
198 : mm ## block ## id ## _ ## reg_name
199 :
200 : #define DCCG_SRII(reg_name, block, id)\
201 : .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
202 : mm ## block ## id ## _ ## reg_name
203 :
204 : #define VUPDATE_SRII(reg_name, block, id)\
205 : .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
206 : mm ## reg_name ## _ ## block ## id
207 :
208 : #define SRII_DWB(reg_name, temp_name, block, id)\
209 : .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
210 : mm ## block ## id ## _ ## temp_name
211 :
212 : #define SRII_MPC_RMU(reg_name, block, id)\
213 : .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
214 : mm ## block ## id ## _ ## reg_name
215 :
216 : static const struct dcn_hubbub_registers hubbub_reg = {
217 : HUBBUB_REG_LIST_DCN30(0)
218 : };
219 :
220 : static const struct dcn_hubbub_shift hubbub_shift = {
221 : HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
222 : };
223 :
224 : static const struct dcn_hubbub_mask hubbub_mask = {
225 : HUBBUB_MASK_SH_LIST_DCN30(_MASK)
226 : };
227 :
228 : #define vmid_regs(id)\
229 : [id] = { DCN20_VMID_REG_LIST(id) }
230 :
231 : static const struct dcn_vmid_registers vmid_regs[] = {
232 : vmid_regs(0),
233 : vmid_regs(1),
234 : vmid_regs(2),
235 : vmid_regs(3),
236 : vmid_regs(4),
237 : vmid_regs(5),
238 : vmid_regs(6),
239 : vmid_regs(7),
240 : vmid_regs(8),
241 : vmid_regs(9),
242 : vmid_regs(10),
243 : vmid_regs(11),
244 : vmid_regs(12),
245 : vmid_regs(13),
246 : vmid_regs(14),
247 : vmid_regs(15)
248 : };
249 :
250 : static const struct dcn20_vmid_shift vmid_shifts = {
251 : DCN20_VMID_MASK_SH_LIST(__SHIFT)
252 : };
253 :
254 : static const struct dcn20_vmid_mask vmid_masks = {
255 : DCN20_VMID_MASK_SH_LIST(_MASK)
256 : };
257 :
258 0 : static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
259 : {
260 : int i;
261 :
262 0 : struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
263 :
264 0 : if (!hubbub3)
265 : return NULL;
266 :
267 0 : hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
268 :
269 0 : for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
270 0 : struct dcn20_vmid *vmid = &hubbub3->vmid[i];
271 :
272 0 : vmid->ctx = ctx;
273 :
274 0 : vmid->regs = &vmid_regs[i];
275 0 : vmid->shifts = &vmid_shifts;
276 0 : vmid->masks = &vmid_masks;
277 : }
278 :
279 0 : return &hubbub3->base;
280 : }
281 :
282 : #define vpg_regs(id)\
283 : [id] = { VPG_DCN3_REG_LIST(id) }
284 :
285 : static const struct dcn30_vpg_registers vpg_regs[] = {
286 : vpg_regs(0),
287 : vpg_regs(1),
288 : vpg_regs(2),
289 : vpg_regs(3),
290 : vpg_regs(4),
291 : vpg_regs(5)
292 : };
293 :
294 : static const struct dcn30_vpg_shift vpg_shift = {
295 : DCN3_VPG_MASK_SH_LIST(__SHIFT)
296 : };
297 :
298 : static const struct dcn30_vpg_mask vpg_mask = {
299 : DCN3_VPG_MASK_SH_LIST(_MASK)
300 : };
301 :
302 0 : static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
303 : {
304 0 : struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
305 :
306 0 : if (!vpg3)
307 : return NULL;
308 :
309 0 : vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
310 :
311 0 : return &vpg3->base;
312 : }
313 :
314 : #define afmt_regs(id)\
315 : [id] = { AFMT_DCN3_REG_LIST(id) }
316 :
317 : static const struct dcn30_afmt_registers afmt_regs[] = {
318 : afmt_regs(0),
319 : afmt_regs(1),
320 : afmt_regs(2),
321 : afmt_regs(3),
322 : afmt_regs(4),
323 : afmt_regs(5)
324 : };
325 :
326 : static const struct dcn30_afmt_shift afmt_shift = {
327 : DCN3_AFMT_MASK_SH_LIST(__SHIFT)
328 : };
329 :
330 : static const struct dcn30_afmt_mask afmt_mask = {
331 : DCN3_AFMT_MASK_SH_LIST(_MASK)
332 : };
333 :
334 0 : static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
335 : {
336 0 : struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
337 :
338 0 : if (!afmt3)
339 : return NULL;
340 :
341 0 : afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
342 :
343 0 : return &afmt3->base;
344 : }
345 :
346 : #define audio_regs(id)\
347 : [id] = { AUD_COMMON_REG_LIST(id) }
348 :
349 : static const struct dce_audio_registers audio_regs[] = {
350 : audio_regs(0),
351 : audio_regs(1),
352 : audio_regs(2),
353 : audio_regs(3),
354 : audio_regs(4),
355 : audio_regs(5),
356 : audio_regs(6)
357 : };
358 :
359 : #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
360 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
361 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
362 : AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
363 :
364 : static const struct dce_audio_shift audio_shift = {
365 : DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
366 : };
367 :
368 : static const struct dce_audio_mask audio_mask = {
369 : DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
370 : };
371 :
372 0 : static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
373 : {
374 0 : return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
375 : }
376 :
377 : #define stream_enc_regs(id)\
378 : [id] = { SE_DCN3_REG_LIST(id) }
379 :
380 : static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
381 : stream_enc_regs(0),
382 : stream_enc_regs(1),
383 : stream_enc_regs(2),
384 : stream_enc_regs(3),
385 : stream_enc_regs(4)
386 : };
387 :
388 : static const struct dcn10_stream_encoder_shift se_shift = {
389 : SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
390 : };
391 :
392 : static const struct dcn10_stream_encoder_mask se_mask = {
393 : SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
394 : };
395 :
396 0 : static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
397 : {
398 : struct dcn10_stream_encoder *enc1;
399 : struct vpg *vpg;
400 : struct afmt *afmt;
401 : int vpg_inst;
402 : int afmt_inst;
403 :
404 : /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
405 0 : if (eng_id <= ENGINE_ID_DIGE) {
406 0 : vpg_inst = eng_id;
407 0 : afmt_inst = eng_id;
408 : } else
409 : return NULL;
410 :
411 0 : enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
412 0 : vpg = dcn302_vpg_create(ctx, vpg_inst);
413 0 : afmt = dcn302_afmt_create(ctx, afmt_inst);
414 :
415 0 : if (!enc1 || !vpg || !afmt) {
416 0 : kfree(enc1);
417 0 : kfree(vpg);
418 0 : kfree(afmt);
419 0 : return NULL;
420 : }
421 :
422 0 : dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
423 : &se_shift, &se_mask);
424 :
425 0 : return &enc1->base;
426 : }
427 :
428 : #define clk_src_regs(index, pllid)\
429 : [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
430 :
431 : static const struct dce110_clk_src_regs clk_src_regs[] = {
432 : clk_src_regs(0, A),
433 : clk_src_regs(1, B),
434 : clk_src_regs(2, C),
435 : clk_src_regs(3, D),
436 : clk_src_regs(4, E)
437 : };
438 :
439 : static const struct dce110_clk_src_shift cs_shift = {
440 : CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
441 : };
442 :
443 : static const struct dce110_clk_src_mask cs_mask = {
444 : CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
445 : };
446 :
447 0 : static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
448 : enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
449 : {
450 0 : struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
451 :
452 0 : if (!clk_src)
453 : return NULL;
454 :
455 0 : if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
456 0 : clk_src->base.dp_clk_src = dp_clk_src;
457 0 : return &clk_src->base;
458 : }
459 :
460 0 : BREAK_TO_DEBUGGER();
461 0 : return NULL;
462 : }
463 :
464 : static const struct dce_hwseq_registers hwseq_reg = {
465 : HWSEQ_DCN302_REG_LIST()
466 : };
467 :
468 : static const struct dce_hwseq_shift hwseq_shift = {
469 : HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
470 : };
471 :
472 : static const struct dce_hwseq_mask hwseq_mask = {
473 : HWSEQ_DCN302_MASK_SH_LIST(_MASK)
474 : };
475 :
476 0 : static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
477 : {
478 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
479 :
480 0 : if (hws) {
481 0 : hws->ctx = ctx;
482 0 : hws->regs = &hwseq_reg;
483 0 : hws->shifts = &hwseq_shift;
484 0 : hws->masks = &hwseq_mask;
485 : }
486 0 : return hws;
487 : }
488 :
489 : #define hubp_regs(id)\
490 : [id] = { HUBP_REG_LIST_DCN30(id) }
491 :
492 : static const struct dcn_hubp2_registers hubp_regs[] = {
493 : hubp_regs(0),
494 : hubp_regs(1),
495 : hubp_regs(2),
496 : hubp_regs(3),
497 : hubp_regs(4)
498 : };
499 :
500 : static const struct dcn_hubp2_shift hubp_shift = {
501 : HUBP_MASK_SH_LIST_DCN30(__SHIFT)
502 : };
503 :
504 : static const struct dcn_hubp2_mask hubp_mask = {
505 : HUBP_MASK_SH_LIST_DCN30(_MASK)
506 : };
507 :
508 0 : static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
509 : {
510 0 : struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
511 :
512 0 : if (!hubp2)
513 : return NULL;
514 :
515 0 : if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
516 0 : return &hubp2->base;
517 :
518 0 : BREAK_TO_DEBUGGER();
519 0 : kfree(hubp2);
520 0 : return NULL;
521 : }
522 :
523 : #define dpp_regs(id)\
524 : [id] = { DPP_REG_LIST_DCN30(id) }
525 :
526 : static const struct dcn3_dpp_registers dpp_regs[] = {
527 : dpp_regs(0),
528 : dpp_regs(1),
529 : dpp_regs(2),
530 : dpp_regs(3),
531 : dpp_regs(4)
532 : };
533 :
534 : static const struct dcn3_dpp_shift tf_shift = {
535 : DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
536 : };
537 :
538 : static const struct dcn3_dpp_mask tf_mask = {
539 : DPP_REG_LIST_SH_MASK_DCN30(_MASK)
540 : };
541 :
542 0 : static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
543 : {
544 0 : struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
545 :
546 0 : if (!dpp)
547 : return NULL;
548 :
549 0 : if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
550 0 : return &dpp->base;
551 :
552 0 : BREAK_TO_DEBUGGER();
553 0 : kfree(dpp);
554 0 : return NULL;
555 : }
556 :
557 : #define opp_regs(id)\
558 : [id] = { OPP_REG_LIST_DCN30(id) }
559 :
560 : static const struct dcn20_opp_registers opp_regs[] = {
561 : opp_regs(0),
562 : opp_regs(1),
563 : opp_regs(2),
564 : opp_regs(3),
565 : opp_regs(4)
566 : };
567 :
568 : static const struct dcn20_opp_shift opp_shift = {
569 : OPP_MASK_SH_LIST_DCN20(__SHIFT)
570 : };
571 :
572 : static const struct dcn20_opp_mask opp_mask = {
573 : OPP_MASK_SH_LIST_DCN20(_MASK)
574 : };
575 :
576 0 : static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
577 : {
578 0 : struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
579 :
580 0 : if (!opp) {
581 0 : BREAK_TO_DEBUGGER();
582 0 : return NULL;
583 : }
584 :
585 0 : dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
586 0 : return &opp->base;
587 : }
588 :
589 : #define optc_regs(id)\
590 : [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
591 :
592 : static const struct dcn_optc_registers optc_regs[] = {
593 : optc_regs(0),
594 : optc_regs(1),
595 : optc_regs(2),
596 : optc_regs(3),
597 : optc_regs(4)
598 : };
599 :
600 : static const struct dcn_optc_shift optc_shift = {
601 : OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
602 : };
603 :
604 : static const struct dcn_optc_mask optc_mask = {
605 : OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
606 : };
607 :
608 0 : static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
609 : {
610 0 : struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
611 :
612 0 : if (!tgn10)
613 : return NULL;
614 :
615 0 : tgn10->base.inst = instance;
616 0 : tgn10->base.ctx = ctx;
617 :
618 0 : tgn10->tg_regs = &optc_regs[instance];
619 0 : tgn10->tg_shift = &optc_shift;
620 0 : tgn10->tg_mask = &optc_mask;
621 :
622 0 : dcn30_timing_generator_init(tgn10);
623 :
624 0 : return &tgn10->base;
625 : }
626 :
627 : static const struct dcn30_mpc_registers mpc_regs = {
628 : MPC_REG_LIST_DCN3_0(0),
629 : MPC_REG_LIST_DCN3_0(1),
630 : MPC_REG_LIST_DCN3_0(2),
631 : MPC_REG_LIST_DCN3_0(3),
632 : MPC_REG_LIST_DCN3_0(4),
633 : MPC_OUT_MUX_REG_LIST_DCN3_0(0),
634 : MPC_OUT_MUX_REG_LIST_DCN3_0(1),
635 : MPC_OUT_MUX_REG_LIST_DCN3_0(2),
636 : MPC_OUT_MUX_REG_LIST_DCN3_0(3),
637 : MPC_OUT_MUX_REG_LIST_DCN3_0(4),
638 : MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
639 : MPC_RMU_REG_LIST_DCN3AG(0),
640 : MPC_RMU_REG_LIST_DCN3AG(1),
641 : MPC_RMU_REG_LIST_DCN3AG(2),
642 : MPC_DWB_MUX_REG_LIST_DCN3_0(0),
643 : };
644 :
645 : static const struct dcn30_mpc_shift mpc_shift = {
646 : MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
647 : };
648 :
649 : static const struct dcn30_mpc_mask mpc_mask = {
650 : MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
651 : };
652 :
653 0 : static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
654 : {
655 0 : struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
656 :
657 0 : if (!mpc30)
658 : return NULL;
659 :
660 0 : dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
661 :
662 0 : return &mpc30->base;
663 : }
664 :
665 : #define dsc_regsDCN20(id)\
666 : [id] = { DSC_REG_LIST_DCN20(id) }
667 :
668 : static const struct dcn20_dsc_registers dsc_regs[] = {
669 : dsc_regsDCN20(0),
670 : dsc_regsDCN20(1),
671 : dsc_regsDCN20(2),
672 : dsc_regsDCN20(3),
673 : dsc_regsDCN20(4)
674 : };
675 :
676 : static const struct dcn20_dsc_shift dsc_shift = {
677 : DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
678 : };
679 :
680 : static const struct dcn20_dsc_mask dsc_mask = {
681 : DSC_REG_LIST_SH_MASK_DCN20(_MASK)
682 : };
683 :
684 0 : static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
685 : {
686 0 : struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
687 :
688 0 : if (!dsc) {
689 0 : BREAK_TO_DEBUGGER();
690 0 : return NULL;
691 : }
692 :
693 0 : dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
694 0 : return &dsc->base;
695 : }
696 :
697 : #define dwbc_regs_dcn3(id)\
698 : [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
699 :
700 : static const struct dcn30_dwbc_registers dwbc30_regs[] = {
701 : dwbc_regs_dcn3(0)
702 : };
703 :
704 : static const struct dcn30_dwbc_shift dwbc30_shift = {
705 : DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
706 : };
707 :
708 : static const struct dcn30_dwbc_mask dwbc30_mask = {
709 : DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
710 : };
711 :
712 0 : static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
713 : {
714 : int i;
715 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
716 :
717 0 : for (i = 0; i < pipe_count; i++) {
718 0 : struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
719 :
720 0 : if (!dwbc30) {
721 0 : dm_error("DC: failed to create dwbc30!\n");
722 : return false;
723 : }
724 :
725 0 : dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
726 :
727 0 : pool->dwbc[i] = &dwbc30->base;
728 : }
729 : return true;
730 : }
731 :
732 : #define mcif_wb_regs_dcn3(id)\
733 : [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
734 :
735 : static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
736 : mcif_wb_regs_dcn3(0)
737 : };
738 :
739 : static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
740 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
741 : };
742 :
743 : static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
744 : MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
745 : };
746 :
747 0 : static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
748 : {
749 : int i;
750 0 : uint32_t pipe_count = pool->res_cap->num_dwb;
751 :
752 0 : for (i = 0; i < pipe_count; i++) {
753 0 : struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
754 :
755 0 : if (!mcif_wb30) {
756 0 : dm_error("DC: failed to create mcif_wb30!\n");
757 : return false;
758 : }
759 :
760 0 : dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
761 :
762 0 : pool->mcif_wb[i] = &mcif_wb30->base;
763 : }
764 : return true;
765 : }
766 :
767 : #define aux_engine_regs(id)\
768 : [id] = {\
769 : AUX_COMMON_REG_LIST0(id), \
770 : .AUXN_IMPCAL = 0, \
771 : .AUXP_IMPCAL = 0, \
772 : .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
773 : }
774 :
775 : static const struct dce110_aux_registers aux_engine_regs[] = {
776 : aux_engine_regs(0),
777 : aux_engine_regs(1),
778 : aux_engine_regs(2),
779 : aux_engine_regs(3),
780 : aux_engine_regs(4)
781 : };
782 :
783 : static const struct dce110_aux_registers_shift aux_shift = {
784 : DCN_AUX_MASK_SH_LIST(__SHIFT)
785 : };
786 :
787 : static const struct dce110_aux_registers_mask aux_mask = {
788 : DCN_AUX_MASK_SH_LIST(_MASK)
789 : };
790 :
791 0 : static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
792 : {
793 0 : struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
794 :
795 0 : if (!aux_engine)
796 : return NULL;
797 :
798 0 : dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
799 0 : &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
800 :
801 0 : return &aux_engine->base;
802 : }
803 :
804 : #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
805 :
806 : static const struct dce_i2c_registers i2c_hw_regs[] = {
807 : i2c_inst_regs(1),
808 : i2c_inst_regs(2),
809 : i2c_inst_regs(3),
810 : i2c_inst_regs(4),
811 : i2c_inst_regs(5)
812 : };
813 :
814 : static const struct dce_i2c_shift i2c_shifts = {
815 : I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
816 : };
817 :
818 : static const struct dce_i2c_mask i2c_masks = {
819 : I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
820 : };
821 :
822 0 : static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
823 : {
824 0 : struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
825 :
826 0 : if (!dce_i2c_hw)
827 : return NULL;
828 :
829 0 : dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
830 :
831 0 : return dce_i2c_hw;
832 : }
833 :
834 : static const struct encoder_feature_support link_enc_feature = {
835 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
836 : .max_hdmi_pixel_clock = 600000,
837 : .hdmi_ycbcr420_supported = true,
838 : .dp_ycbcr420_supported = true,
839 : .fec_supported = true,
840 : .flags.bits.IS_HBR2_CAPABLE = true,
841 : .flags.bits.IS_HBR3_CAPABLE = true,
842 : .flags.bits.IS_TPS3_CAPABLE = true,
843 : .flags.bits.IS_TPS4_CAPABLE = true
844 : };
845 :
846 : #define link_regs(id, phyid)\
847 : [id] = {\
848 : LE_DCN3_REG_LIST(id), \
849 : UNIPHY_DCN2_REG_LIST(phyid), \
850 : DPCS_DCN2_REG_LIST(id), \
851 : SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
852 : }
853 :
854 : static const struct dcn10_link_enc_registers link_enc_regs[] = {
855 : link_regs(0, A),
856 : link_regs(1, B),
857 : link_regs(2, C),
858 : link_regs(3, D),
859 : link_regs(4, E)
860 : };
861 :
862 : static const struct dcn10_link_enc_shift le_shift = {
863 : LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
864 : DPCS_DCN2_MASK_SH_LIST(__SHIFT)
865 : };
866 :
867 : static const struct dcn10_link_enc_mask le_mask = {
868 : LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
869 : DPCS_DCN2_MASK_SH_LIST(_MASK)
870 : };
871 :
872 : #define aux_regs(id)\
873 : [id] = { DCN2_AUX_REG_LIST(id) }
874 :
875 : static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
876 : aux_regs(0),
877 : aux_regs(1),
878 : aux_regs(2),
879 : aux_regs(3),
880 : aux_regs(4)
881 : };
882 :
883 : #define hpd_regs(id)\
884 : [id] = { HPD_REG_LIST(id) }
885 :
886 : static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
887 : hpd_regs(0),
888 : hpd_regs(1),
889 : hpd_regs(2),
890 : hpd_regs(3),
891 : hpd_regs(4)
892 : };
893 :
894 0 : static struct link_encoder *dcn302_link_encoder_create(
895 : struct dc_context *ctx,
896 : const struct encoder_init_data *enc_init_data)
897 : {
898 0 : struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
899 :
900 0 : if (!enc20)
901 : return NULL;
902 :
903 0 : dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
904 0 : &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
905 0 : &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
906 :
907 0 : return &enc20->enc10.base;
908 : }
909 :
910 : static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
911 : { DCN_PANEL_CNTL_REG_LIST() }
912 : };
913 :
914 : static const struct dce_panel_cntl_shift panel_cntl_shift = {
915 : DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
916 : };
917 :
918 : static const struct dce_panel_cntl_mask panel_cntl_mask = {
919 : DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
920 : };
921 :
922 0 : static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
923 : {
924 0 : struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
925 :
926 0 : if (!panel_cntl)
927 : return NULL;
928 :
929 0 : dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
930 : &panel_cntl_shift, &panel_cntl_mask);
931 :
932 0 : return &panel_cntl->base;
933 : }
934 :
935 0 : static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
936 : {
937 0 : generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
938 : FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
939 0 : }
940 :
941 : static const struct resource_create_funcs res_create_funcs = {
942 : .read_dce_straps = read_dce_straps,
943 : .create_audio = dcn302_create_audio,
944 : .create_stream_encoder = dcn302_stream_encoder_create,
945 : .create_hwseq = dcn302_hwseq_create,
946 : };
947 :
948 : static const struct resource_create_funcs res_create_maximus_funcs = {
949 : .read_dce_straps = NULL,
950 : .create_audio = NULL,
951 : .create_stream_encoder = NULL,
952 : .create_hwseq = dcn302_hwseq_create,
953 : };
954 :
955 : static bool is_soc_bounding_box_valid(struct dc *dc)
956 : {
957 0 : uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
958 :
959 0 : if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
960 : return true;
961 :
962 : return false;
963 : }
964 :
965 0 : static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
966 : {
967 0 : struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
968 0 : struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
969 :
970 : DC_LOGGER_INIT(dc->ctx->logger);
971 :
972 0 : if (!is_soc_bounding_box_valid(dc)) {
973 0 : DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
974 : return false;
975 : }
976 :
977 0 : loaded_ip->max_num_otg = pool->pipe_count;
978 0 : loaded_ip->max_num_dpp = pool->pipe_count;
979 0 : loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
980 0 : DC_FP_START();
981 0 : dcn20_patch_bounding_box(dc, loaded_bb);
982 0 : DC_FP_END();
983 :
984 0 : if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
985 0 : struct bp_soc_bb_info bb_info = { 0 };
986 :
987 0 : if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
988 : dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
989 :
990 0 : DC_FP_START();
991 0 : dcn302_fpu_init_soc_bounding_box(bb_info);
992 0 : DC_FP_END();
993 : }
994 : }
995 :
996 : return true;
997 : }
998 :
999 0 : static void dcn302_resource_destruct(struct resource_pool *pool)
1000 : {
1001 : unsigned int i;
1002 :
1003 0 : for (i = 0; i < pool->stream_enc_count; i++) {
1004 0 : if (pool->stream_enc[i] != NULL) {
1005 0 : if (pool->stream_enc[i]->vpg != NULL) {
1006 0 : kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1007 0 : pool->stream_enc[i]->vpg = NULL;
1008 : }
1009 0 : if (pool->stream_enc[i]->afmt != NULL) {
1010 0 : kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1011 0 : pool->stream_enc[i]->afmt = NULL;
1012 : }
1013 0 : kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1014 0 : pool->stream_enc[i] = NULL;
1015 : }
1016 : }
1017 :
1018 0 : for (i = 0; i < pool->res_cap->num_dsc; i++) {
1019 0 : if (pool->dscs[i] != NULL)
1020 0 : dcn20_dsc_destroy(&pool->dscs[i]);
1021 : }
1022 :
1023 0 : if (pool->mpc != NULL) {
1024 0 : kfree(TO_DCN20_MPC(pool->mpc));
1025 0 : pool->mpc = NULL;
1026 : }
1027 :
1028 0 : if (pool->hubbub != NULL) {
1029 0 : kfree(pool->hubbub);
1030 0 : pool->hubbub = NULL;
1031 : }
1032 :
1033 0 : for (i = 0; i < pool->pipe_count; i++) {
1034 0 : if (pool->dpps[i] != NULL) {
1035 0 : kfree(TO_DCN20_DPP(pool->dpps[i]));
1036 0 : pool->dpps[i] = NULL;
1037 : }
1038 :
1039 0 : if (pool->hubps[i] != NULL) {
1040 0 : kfree(TO_DCN20_HUBP(pool->hubps[i]));
1041 0 : pool->hubps[i] = NULL;
1042 : }
1043 :
1044 0 : if (pool->irqs != NULL)
1045 0 : dal_irq_service_destroy(&pool->irqs);
1046 : }
1047 :
1048 0 : for (i = 0; i < pool->res_cap->num_ddc; i++) {
1049 0 : if (pool->engines[i] != NULL)
1050 0 : dce110_engine_destroy(&pool->engines[i]);
1051 0 : if (pool->hw_i2cs[i] != NULL) {
1052 0 : kfree(pool->hw_i2cs[i]);
1053 0 : pool->hw_i2cs[i] = NULL;
1054 : }
1055 0 : if (pool->sw_i2cs[i] != NULL) {
1056 0 : kfree(pool->sw_i2cs[i]);
1057 0 : pool->sw_i2cs[i] = NULL;
1058 : }
1059 : }
1060 :
1061 0 : for (i = 0; i < pool->res_cap->num_opp; i++) {
1062 0 : if (pool->opps[i] != NULL)
1063 0 : pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1064 : }
1065 :
1066 0 : for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1067 0 : if (pool->timing_generators[i] != NULL) {
1068 0 : kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1069 0 : pool->timing_generators[i] = NULL;
1070 : }
1071 : }
1072 :
1073 0 : for (i = 0; i < pool->res_cap->num_dwb; i++) {
1074 0 : if (pool->dwbc[i] != NULL) {
1075 0 : kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1076 0 : pool->dwbc[i] = NULL;
1077 : }
1078 0 : if (pool->mcif_wb[i] != NULL) {
1079 0 : kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1080 0 : pool->mcif_wb[i] = NULL;
1081 : }
1082 : }
1083 :
1084 0 : for (i = 0; i < pool->audio_count; i++) {
1085 0 : if (pool->audios[i])
1086 0 : dce_aud_destroy(&pool->audios[i]);
1087 : }
1088 :
1089 0 : for (i = 0; i < pool->clk_src_count; i++) {
1090 0 : if (pool->clock_sources[i] != NULL)
1091 0 : dcn20_clock_source_destroy(&pool->clock_sources[i]);
1092 : }
1093 :
1094 0 : if (pool->dp_clock_source != NULL)
1095 0 : dcn20_clock_source_destroy(&pool->dp_clock_source);
1096 :
1097 0 : for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1098 0 : if (pool->mpc_lut[i] != NULL) {
1099 0 : dc_3dlut_func_release(pool->mpc_lut[i]);
1100 0 : pool->mpc_lut[i] = NULL;
1101 : }
1102 0 : if (pool->mpc_shaper[i] != NULL) {
1103 0 : dc_transfer_func_release(pool->mpc_shaper[i]);
1104 0 : pool->mpc_shaper[i] = NULL;
1105 : }
1106 : }
1107 :
1108 0 : for (i = 0; i < pool->pipe_count; i++) {
1109 0 : if (pool->multiple_abms[i] != NULL)
1110 0 : dce_abm_destroy(&pool->multiple_abms[i]);
1111 : }
1112 :
1113 0 : if (pool->psr != NULL)
1114 0 : dmub_psr_destroy(&pool->psr);
1115 :
1116 0 : if (pool->dccg != NULL)
1117 0 : dcn_dccg_destroy(&pool->dccg);
1118 0 : }
1119 :
1120 0 : static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1121 : {
1122 0 : dcn302_resource_destruct(*pool);
1123 0 : kfree(*pool);
1124 0 : *pool = NULL;
1125 0 : }
1126 :
1127 0 : void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1128 : {
1129 0 : DC_FP_START();
1130 0 : dcn302_fpu_update_bw_bounding_box(dc, bw_params);
1131 0 : DC_FP_END();
1132 0 : }
1133 :
1134 : static struct resource_funcs dcn302_res_pool_funcs = {
1135 : .destroy = dcn302_destroy_resource_pool,
1136 : .link_enc_create = dcn302_link_encoder_create,
1137 : .panel_cntl_create = dcn302_panel_cntl_create,
1138 : .validate_bandwidth = dcn30_validate_bandwidth,
1139 : .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1140 : .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1141 : .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1142 : .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1143 : .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1144 : .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1145 : .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1146 : .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1147 : .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1148 : .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1149 : .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1150 : .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1151 : .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1152 : .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1153 : };
1154 :
1155 : static struct dc_cap_funcs cap_funcs = {
1156 : .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1157 : };
1158 :
1159 : static const struct bios_registers bios_regs = {
1160 : NBIO_SR(BIOS_SCRATCH_3),
1161 : NBIO_SR(BIOS_SCRATCH_6)
1162 : };
1163 :
1164 : static const struct dccg_registers dccg_regs = {
1165 : DCCG_REG_LIST_DCN3_02()
1166 : };
1167 :
1168 : static const struct dccg_shift dccg_shift = {
1169 : DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1170 : };
1171 :
1172 : static const struct dccg_mask dccg_mask = {
1173 : DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1174 : };
1175 :
1176 : #define abm_regs(id)\
1177 : [id] = { ABM_DCN302_REG_LIST(id) }
1178 :
1179 : static const struct dce_abm_registers abm_regs[] = {
1180 : abm_regs(0),
1181 : abm_regs(1),
1182 : abm_regs(2),
1183 : abm_regs(3),
1184 : abm_regs(4)
1185 : };
1186 :
1187 : static const struct dce_abm_shift abm_shift = {
1188 : ABM_MASK_SH_LIST_DCN30(__SHIFT)
1189 : };
1190 :
1191 : static const struct dce_abm_mask abm_mask = {
1192 : ABM_MASK_SH_LIST_DCN30(_MASK)
1193 : };
1194 :
1195 0 : static bool dcn302_resource_construct(
1196 : uint8_t num_virtual_links,
1197 : struct dc *dc,
1198 : struct resource_pool *pool)
1199 : {
1200 : int i;
1201 0 : struct dc_context *ctx = dc->ctx;
1202 : struct irq_service_init_data init_data;
1203 :
1204 0 : ctx->dc_bios->regs = &bios_regs;
1205 :
1206 0 : pool->res_cap = &res_cap_dcn302;
1207 :
1208 0 : pool->funcs = &dcn302_res_pool_funcs;
1209 :
1210 : /*************************************************
1211 : * Resource + asic cap harcoding *
1212 : *************************************************/
1213 0 : pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1214 0 : pool->pipe_count = pool->res_cap->num_timing_generator;
1215 0 : pool->mpcc_count = pool->res_cap->num_timing_generator;
1216 0 : dc->caps.max_downscale_ratio = 600;
1217 0 : dc->caps.i2c_speed_in_khz = 100;
1218 0 : dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1219 0 : dc->caps.max_cursor_size = 256;
1220 0 : dc->caps.min_horizontal_blanking_period = 80;
1221 0 : dc->caps.dmdata_alloc_size = 2048;
1222 0 : dc->caps.mall_size_per_mem_channel = 4;
1223 : /* total size = mall per channel * num channels * 1024 * 1024 */
1224 0 : dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1225 0 : dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1226 0 : dc->caps.max_slave_planes = 2;
1227 0 : dc->caps.max_slave_yuv_planes = 2;
1228 0 : dc->caps.max_slave_rgb_planes = 2;
1229 0 : dc->caps.post_blend_color_processing = true;
1230 0 : dc->caps.force_dp_tps4_for_cp2520 = true;
1231 0 : dc->caps.extended_aux_timeout_support = true;
1232 0 : dc->caps.dmcub_support = true;
1233 :
1234 : /* Color pipeline capabilities */
1235 0 : dc->caps.color.dpp.dcn_arch = 1;
1236 0 : dc->caps.color.dpp.input_lut_shared = 0;
1237 0 : dc->caps.color.dpp.icsc = 1;
1238 0 : dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1239 0 : dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1240 0 : dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1241 0 : dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1242 0 : dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1243 0 : dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1244 0 : dc->caps.color.dpp.post_csc = 1;
1245 0 : dc->caps.color.dpp.gamma_corr = 1;
1246 0 : dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1247 :
1248 0 : dc->caps.color.dpp.hw_3d_lut = 1;
1249 0 : dc->caps.color.dpp.ogam_ram = 1;
1250 : // no OGAM ROM on DCN3
1251 0 : dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1252 0 : dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1253 0 : dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1254 0 : dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1255 0 : dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1256 0 : dc->caps.color.dpp.ocsc = 0;
1257 :
1258 0 : dc->caps.color.mpc.gamut_remap = 1;
1259 0 : dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1260 0 : dc->caps.color.mpc.ogam_ram = 1;
1261 0 : dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1262 0 : dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1263 0 : dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1264 0 : dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1265 0 : dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1266 0 : dc->caps.color.mpc.ocsc = 1;
1267 :
1268 : /* read VBIOS LTTPR caps */
1269 0 : if (ctx->dc_bios->funcs->get_lttpr_caps) {
1270 : enum bp_result bp_query_result;
1271 0 : uint8_t is_vbios_lttpr_enable = 0;
1272 :
1273 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1274 0 : dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1275 : }
1276 :
1277 0 : if (ctx->dc_bios->funcs->get_lttpr_interop) {
1278 : enum bp_result bp_query_result;
1279 0 : uint8_t is_vbios_interop_enabled = 0;
1280 :
1281 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
1282 : &is_vbios_interop_enabled);
1283 0 : dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1284 : }
1285 :
1286 0 : if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1287 0 : dc->debug = debug_defaults_drv;
1288 : else
1289 0 : dc->debug = debug_defaults_diags;
1290 :
1291 : // Init the vm_helper
1292 0 : if (dc->vm_helper)
1293 0 : vm_helper_init(dc->vm_helper, 16);
1294 :
1295 : /*************************************************
1296 : * Create resources *
1297 : *************************************************/
1298 :
1299 : /* Clock Sources for Pixel Clock*/
1300 0 : pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1301 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1302 : CLOCK_SOURCE_COMBO_PHY_PLL0,
1303 : &clk_src_regs[0], false);
1304 0 : pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1305 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1306 : CLOCK_SOURCE_COMBO_PHY_PLL1,
1307 : &clk_src_regs[1], false);
1308 0 : pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1309 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1310 : CLOCK_SOURCE_COMBO_PHY_PLL2,
1311 : &clk_src_regs[2], false);
1312 0 : pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1313 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1314 : CLOCK_SOURCE_COMBO_PHY_PLL3,
1315 : &clk_src_regs[3], false);
1316 0 : pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1317 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1318 : CLOCK_SOURCE_COMBO_PHY_PLL4,
1319 : &clk_src_regs[4], false);
1320 :
1321 0 : pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1322 :
1323 : /* todo: not reuse phy_pll registers */
1324 0 : pool->dp_clock_source =
1325 0 : dcn302_clock_source_create(ctx, ctx->dc_bios,
1326 : CLOCK_SOURCE_ID_DP_DTO,
1327 : &clk_src_regs[0], true);
1328 :
1329 0 : for (i = 0; i < pool->clk_src_count; i++) {
1330 0 : if (pool->clock_sources[i] == NULL) {
1331 0 : dm_error("DC: failed to create clock sources!\n");
1332 0 : BREAK_TO_DEBUGGER();
1333 0 : goto create_fail;
1334 : }
1335 : }
1336 :
1337 : /* DCCG */
1338 0 : pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1339 0 : if (pool->dccg == NULL) {
1340 0 : dm_error("DC: failed to create dccg!\n");
1341 0 : BREAK_TO_DEBUGGER();
1342 0 : goto create_fail;
1343 : }
1344 :
1345 : /* PP Lib and SMU interfaces */
1346 0 : init_soc_bounding_box(dc, pool);
1347 :
1348 : /* DML */
1349 0 : dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1350 :
1351 : /* IRQ */
1352 0 : init_data.ctx = dc->ctx;
1353 0 : pool->irqs = dal_irq_service_dcn302_create(&init_data);
1354 0 : if (!pool->irqs)
1355 : goto create_fail;
1356 :
1357 : /* HUBBUB */
1358 0 : pool->hubbub = dcn302_hubbub_create(ctx);
1359 0 : if (pool->hubbub == NULL) {
1360 0 : BREAK_TO_DEBUGGER();
1361 0 : dm_error("DC: failed to create hubbub!\n");
1362 0 : goto create_fail;
1363 : }
1364 :
1365 : /* HUBPs, DPPs, OPPs and TGs */
1366 0 : for (i = 0; i < pool->pipe_count; i++) {
1367 0 : pool->hubps[i] = dcn302_hubp_create(ctx, i);
1368 0 : if (pool->hubps[i] == NULL) {
1369 0 : BREAK_TO_DEBUGGER();
1370 0 : dm_error("DC: failed to create hubps!\n");
1371 0 : goto create_fail;
1372 : }
1373 :
1374 0 : pool->dpps[i] = dcn302_dpp_create(ctx, i);
1375 0 : if (pool->dpps[i] == NULL) {
1376 0 : BREAK_TO_DEBUGGER();
1377 0 : dm_error("DC: failed to create dpps!\n");
1378 0 : goto create_fail;
1379 : }
1380 : }
1381 :
1382 0 : for (i = 0; i < pool->res_cap->num_opp; i++) {
1383 0 : pool->opps[i] = dcn302_opp_create(ctx, i);
1384 0 : if (pool->opps[i] == NULL) {
1385 0 : BREAK_TO_DEBUGGER();
1386 0 : dm_error("DC: failed to create output pixel processor!\n");
1387 0 : goto create_fail;
1388 : }
1389 : }
1390 :
1391 0 : for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1392 0 : pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1393 0 : if (pool->timing_generators[i] == NULL) {
1394 0 : BREAK_TO_DEBUGGER();
1395 0 : dm_error("DC: failed to create tg!\n");
1396 0 : goto create_fail;
1397 : }
1398 : }
1399 0 : pool->timing_generator_count = i;
1400 :
1401 : /* PSR */
1402 0 : pool->psr = dmub_psr_create(ctx);
1403 0 : if (pool->psr == NULL) {
1404 0 : dm_error("DC: failed to create psr!\n");
1405 0 : BREAK_TO_DEBUGGER();
1406 0 : goto create_fail;
1407 : }
1408 :
1409 : /* ABMs */
1410 0 : for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1411 0 : pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1412 0 : if (pool->multiple_abms[i] == NULL) {
1413 0 : dm_error("DC: failed to create abm for pipe %d!\n", i);
1414 0 : BREAK_TO_DEBUGGER();
1415 0 : goto create_fail;
1416 : }
1417 : }
1418 :
1419 : /* MPC and DSC */
1420 0 : pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1421 0 : if (pool->mpc == NULL) {
1422 0 : BREAK_TO_DEBUGGER();
1423 0 : dm_error("DC: failed to create mpc!\n");
1424 0 : goto create_fail;
1425 : }
1426 :
1427 0 : for (i = 0; i < pool->res_cap->num_dsc; i++) {
1428 0 : pool->dscs[i] = dcn302_dsc_create(ctx, i);
1429 0 : if (pool->dscs[i] == NULL) {
1430 0 : BREAK_TO_DEBUGGER();
1431 0 : dm_error("DC: failed to create display stream compressor %d!\n", i);
1432 0 : goto create_fail;
1433 : }
1434 : }
1435 :
1436 : /* DWB and MMHUBBUB */
1437 0 : if (!dcn302_dwbc_create(ctx, pool)) {
1438 0 : BREAK_TO_DEBUGGER();
1439 0 : dm_error("DC: failed to create dwbc!\n");
1440 0 : goto create_fail;
1441 : }
1442 :
1443 0 : if (!dcn302_mmhubbub_create(ctx, pool)) {
1444 0 : BREAK_TO_DEBUGGER();
1445 0 : dm_error("DC: failed to create mcif_wb!\n");
1446 0 : goto create_fail;
1447 : }
1448 :
1449 : /* AUX and I2C */
1450 0 : for (i = 0; i < pool->res_cap->num_ddc; i++) {
1451 0 : pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1452 0 : if (pool->engines[i] == NULL) {
1453 0 : BREAK_TO_DEBUGGER();
1454 0 : dm_error("DC:failed to create aux engine!!\n");
1455 0 : goto create_fail;
1456 : }
1457 0 : pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1458 0 : if (pool->hw_i2cs[i] == NULL) {
1459 0 : BREAK_TO_DEBUGGER();
1460 0 : dm_error("DC:failed to create hw i2c!!\n");
1461 0 : goto create_fail;
1462 : }
1463 0 : pool->sw_i2cs[i] = NULL;
1464 : }
1465 :
1466 : /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1467 0 : if (!resource_construct(num_virtual_links, dc, pool,
1468 0 : (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1469 : &res_create_funcs : &res_create_maximus_funcs)))
1470 : goto create_fail;
1471 :
1472 : /* HW Sequencer and Plane caps */
1473 0 : dcn302_hw_sequencer_construct(dc);
1474 :
1475 0 : dc->caps.max_planes = pool->pipe_count;
1476 :
1477 0 : for (i = 0; i < dc->caps.max_planes; ++i)
1478 0 : dc->caps.planes[i] = plane_cap;
1479 :
1480 0 : dc->cap_funcs = cap_funcs;
1481 :
1482 0 : return true;
1483 :
1484 : create_fail:
1485 :
1486 0 : dcn302_resource_destruct(pool);
1487 :
1488 0 : return false;
1489 : }
1490 :
1491 0 : struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1492 : {
1493 0 : struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1494 :
1495 0 : if (!pool)
1496 : return NULL;
1497 :
1498 0 : if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1499 : return pool;
1500 :
1501 0 : BREAK_TO_DEBUGGER();
1502 0 : kfree(pool);
1503 0 : return NULL;
1504 : }
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