Line data Source code
1 : // SPDX-License-Identifier: MIT
2 : /*
3 : * Copyright 2022 Advanced Micro Devices, Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: AMD
24 : *
25 : */
26 :
27 :
28 : #include "dc_bios_types.h"
29 : #include "dcn30/dcn30_dio_stream_encoder.h"
30 : #include "dcn314_dio_stream_encoder.h"
31 : #include "reg_helper.h"
32 : #include "hw_shared.h"
33 : #include "inc/link_dpcd.h"
34 : #include "dpcd_defs.h"
35 :
36 : #define DC_LOGGER \
37 : enc1->base.ctx->logger
38 :
39 : #define REG(reg)\
40 : (enc1->regs->reg)
41 :
42 : #undef FN
43 : #define FN(reg_name, field_name) \
44 : enc1->se_shift->field_name, enc1->se_mask->field_name
45 :
46 : #define VBI_LINE_0 0
47 : #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
48 :
49 : #define CTX \
50 : enc1->base.ctx
51 :
52 :
53 0 : static void enc314_enable_fifo(struct stream_encoder *enc)
54 : {
55 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
56 :
57 : /* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */
58 0 : REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);
59 0 : REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1, DIG_FIFO_READ_START_LEVEL, 0x7);
60 0 : REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
61 0 : REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
62 0 : REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
63 0 : REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
64 0 : }
65 :
66 0 : static void enc314_disable_fifo(struct stream_encoder *enc)
67 : {
68 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
69 :
70 0 : REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,
71 : DIG_FIFO_READ_START_LEVEL, 0);
72 0 : }
73 :
74 0 : static void enc314_dp_set_odm_combine(
75 : struct stream_encoder *enc,
76 : bool odm_combine)
77 : {
78 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
79 :
80 0 : REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine);
81 0 : }
82 :
83 : /* setup stream encoder in dvi mode */
84 0 : void enc314_stream_encoder_dvi_set_stream_attribute(
85 : struct stream_encoder *enc,
86 : struct dc_crtc_timing *crtc_timing,
87 : bool is_dual_link)
88 : {
89 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
90 :
91 0 : if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
92 0 : struct bp_encoder_control cntl = {0};
93 :
94 0 : cntl.action = ENCODER_CONTROL_SETUP;
95 0 : cntl.engine_id = enc1->base.id;
96 0 : cntl.signal = is_dual_link ?
97 0 : SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
98 : cntl.enable_dp_audio = false;
99 0 : cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
100 0 : cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
101 :
102 0 : if (enc1->base.bp->funcs->encoder_control(
103 : enc1->base.bp, &cntl) != BP_RESULT_OK)
104 0 : return;
105 :
106 : } else {
107 :
108 : //Set pattern for clock channel, default vlue 0x63 does not work
109 0 : REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
110 :
111 : //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
112 :
113 : //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
114 :
115 0 : enc314_enable_fifo(enc);
116 : }
117 :
118 0 : ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
119 0 : ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
120 0 : enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
121 : }
122 :
123 : /* setup stream encoder in hdmi mode */
124 0 : static void enc314_stream_encoder_hdmi_set_stream_attribute(
125 : struct stream_encoder *enc,
126 : struct dc_crtc_timing *crtc_timing,
127 : int actual_pix_clk_khz,
128 : bool enable_audio)
129 : {
130 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
131 :
132 0 : if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
133 0 : struct bp_encoder_control cntl = {0};
134 :
135 0 : cntl.action = ENCODER_CONTROL_SETUP;
136 0 : cntl.engine_id = enc1->base.id;
137 0 : cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
138 0 : cntl.enable_dp_audio = enable_audio;
139 0 : cntl.pixel_clock = actual_pix_clk_khz;
140 0 : cntl.lanes_number = LANE_COUNT_FOUR;
141 :
142 0 : if (enc1->base.bp->funcs->encoder_control(
143 : enc1->base.bp, &cntl) != BP_RESULT_OK)
144 0 : return;
145 :
146 : } else {
147 :
148 : //Set pattern for clock channel, default vlue 0x63 does not work
149 0 : REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
150 :
151 : //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
152 :
153 : //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
154 :
155 0 : enc314_enable_fifo(enc);
156 : }
157 :
158 : /* Configure pixel encoding */
159 0 : enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
160 :
161 : /* setup HDMI engine */
162 0 : REG_UPDATE_6(HDMI_CONTROL,
163 : HDMI_PACKET_GEN_VERSION, 1,
164 : HDMI_KEEPOUT_MODE, 1,
165 : HDMI_DEEP_COLOR_ENABLE, 0,
166 : HDMI_DATA_SCRAMBLE_EN, 0,
167 : HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
168 : HDMI_CLOCK_CHANNEL_RATE, 0);
169 :
170 : /* Configure color depth */
171 0 : switch (crtc_timing->display_color_depth) {
172 : case COLOR_DEPTH_888:
173 0 : REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
174 0 : break;
175 : case COLOR_DEPTH_101010:
176 0 : if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
177 0 : REG_UPDATE_2(HDMI_CONTROL,
178 : HDMI_DEEP_COLOR_DEPTH, 1,
179 : HDMI_DEEP_COLOR_ENABLE, 0);
180 : } else {
181 0 : REG_UPDATE_2(HDMI_CONTROL,
182 : HDMI_DEEP_COLOR_DEPTH, 1,
183 : HDMI_DEEP_COLOR_ENABLE, 1);
184 : }
185 : break;
186 : case COLOR_DEPTH_121212:
187 0 : if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
188 0 : REG_UPDATE_2(HDMI_CONTROL,
189 : HDMI_DEEP_COLOR_DEPTH, 2,
190 : HDMI_DEEP_COLOR_ENABLE, 0);
191 : } else {
192 0 : REG_UPDATE_2(HDMI_CONTROL,
193 : HDMI_DEEP_COLOR_DEPTH, 2,
194 : HDMI_DEEP_COLOR_ENABLE, 1);
195 : }
196 : break;
197 : case COLOR_DEPTH_161616:
198 0 : REG_UPDATE_2(HDMI_CONTROL,
199 : HDMI_DEEP_COLOR_DEPTH, 3,
200 : HDMI_DEEP_COLOR_ENABLE, 1);
201 0 : break;
202 : default:
203 : break;
204 : }
205 :
206 0 : if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
207 : /* enable HDMI data scrambler
208 : * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
209 : * Clock channel frequency is 1/4 of character rate.
210 : */
211 0 : REG_UPDATE_2(HDMI_CONTROL,
212 : HDMI_DATA_SCRAMBLE_EN, 1,
213 : HDMI_CLOCK_CHANNEL_RATE, 1);
214 0 : } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
215 :
216 : /* TODO: New feature for DCE11, still need to implement */
217 :
218 : /* enable HDMI data scrambler
219 : * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
220 : * Clock channel frequency is the same
221 : * as character rate
222 : */
223 0 : REG_UPDATE_2(HDMI_CONTROL,
224 : HDMI_DATA_SCRAMBLE_EN, 1,
225 : HDMI_CLOCK_CHANNEL_RATE, 0);
226 : }
227 :
228 :
229 : /* Enable transmission of General Control packet on every frame */
230 0 : REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
231 : HDMI_GC_CONT, 1,
232 : HDMI_GC_SEND, 1,
233 : HDMI_NULL_SEND, 1);
234 :
235 : /* Disable Audio Content Protection packet transmission */
236 0 : REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
237 :
238 : /* following belongs to audio */
239 : /* Enable Audio InfoFrame packet transmission. */
240 0 : REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
241 :
242 : /* update double-buffered AUDIO_INFO registers immediately */
243 0 : ASSERT(enc->afmt);
244 0 : enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
245 :
246 : /* Select line number on which to send Audio InfoFrame packets */
247 0 : REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
248 : VBI_LINE_0 + 2);
249 :
250 : /* set HDMI GC AVMUTE */
251 0 : REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
252 : }
253 :
254 :
255 :
256 : static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
257 : {
258 0 : bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
259 :
260 0 : two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
261 0 : && !timing->dsc_cfg.ycbcr422_simple);
262 : return two_pix;
263 : }
264 :
265 0 : static void enc314_stream_encoder_dp_unblank(
266 : struct dc_link *link,
267 : struct stream_encoder *enc,
268 : const struct encoder_unblank_param *param)
269 : {
270 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
271 :
272 0 : if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
273 0 : uint32_t n_vid = 0x8000;
274 : uint32_t m_vid;
275 0 : uint32_t n_multiply = 0;
276 0 : uint64_t m_vid_l = n_vid;
277 :
278 : /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
279 0 : if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) {
280 : /*this logic should be the same in get_pixel_clock_parameters() */
281 0 : n_multiply = 1;
282 : }
283 : /* M / N = Fstream / Flink
284 : * m_vid / n_vid = pixel rate / link rate
285 : */
286 :
287 0 : m_vid_l *= param->timing.pix_clk_100hz / 10;
288 0 : m_vid_l = div_u64(m_vid_l,
289 : param->link_settings.link_rate
290 : * LINK_RATE_REF_FREQ_IN_KHZ);
291 :
292 0 : m_vid = (uint32_t) m_vid_l;
293 :
294 : /* enable auto measurement */
295 :
296 0 : REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
297 :
298 : /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
299 : * therefore program initial value for Mvid and Nvid
300 : */
301 :
302 0 : REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
303 :
304 0 : REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
305 :
306 0 : REG_UPDATE_2(DP_VID_TIMING,
307 : DP_VID_M_N_GEN_EN, 1,
308 : DP_VID_N_MUL, n_multiply);
309 : }
310 :
311 : /* make sure stream is disabled before resetting steer fifo */
312 0 : REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);
313 0 : REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 0, 10, 5000);
314 :
315 : /* DIG_START is removed from the register spec */
316 :
317 : /* switch DP encoder to CRTC data, but reset it the fifo first. It may happen
318 : * that it overflows during mode transition, and sometimes doesn't recover.
319 : */
320 0 : REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
321 0 : REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);
322 0 : udelay(10);
323 :
324 0 : REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
325 :
326 : /* DIG Resync FIFO now needs to be explicitly enabled. */
327 0 : enc314_enable_fifo(enc);
328 :
329 : /* wait 100us for DIG/DP logic to prime
330 : * (i.e. a few video lines)
331 : */
332 0 : udelay(100);
333 :
334 : /* the hardware would start sending video at the start of the next DP
335 : * frame (i.e. rising edge of the vblank).
336 : * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
337 : * register has no effect on enable transition! HW always guarantees
338 : * VID_STREAM enable at start of next frame, and this is not
339 : * programmable
340 : */
341 :
342 0 : REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
343 :
344 0 : dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
345 0 : }
346 :
347 : /* Set DSC-related configuration.
348 : * dsc_mode: 0 disables DSC, other values enable DSC in specified format
349 : * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32
350 : * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN32
351 : */
352 0 : static void enc314_dp_set_dsc_config(struct stream_encoder *enc,
353 : enum optc_dsc_mode dsc_mode,
354 : uint32_t dsc_bytes_per_pixel,
355 : uint32_t dsc_slice_width)
356 : {
357 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
358 :
359 0 : REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);
360 0 : }
361 :
362 : /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
363 : * into a dcn_dsc_state struct.
364 : */
365 0 : static void enc314_read_state(struct stream_encoder *enc, struct enc_state *s)
366 : {
367 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
368 :
369 : //if dsc is enabled, continue to read
370 0 : REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
371 0 : if (s->dsc_mode) {
372 0 : REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
373 :
374 0 : REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
375 0 : REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
376 :
377 0 : REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
378 0 : REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
379 : }
380 0 : }
381 :
382 0 : static void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container)
383 : {
384 0 : struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
385 :
386 : // The naming of this field is confusing, what it means is the output mode of otg, which
387 : // is the input mode of the dig
388 0 : REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);
389 0 : }
390 :
391 :
392 : static const struct stream_encoder_funcs dcn314_str_enc_funcs = {
393 : .dp_set_odm_combine =
394 : enc314_dp_set_odm_combine,
395 : .dp_set_stream_attribute =
396 : enc2_stream_encoder_dp_set_stream_attribute,
397 : .hdmi_set_stream_attribute =
398 : enc314_stream_encoder_hdmi_set_stream_attribute,
399 : .dvi_set_stream_attribute =
400 : enc314_stream_encoder_dvi_set_stream_attribute,
401 : .set_throttled_vcp_size =
402 : enc1_stream_encoder_set_throttled_vcp_size,
403 : .update_hdmi_info_packets =
404 : enc3_stream_encoder_update_hdmi_info_packets,
405 : .stop_hdmi_info_packets =
406 : enc3_stream_encoder_stop_hdmi_info_packets,
407 : .update_dp_info_packets =
408 : enc3_stream_encoder_update_dp_info_packets,
409 : .stop_dp_info_packets =
410 : enc1_stream_encoder_stop_dp_info_packets,
411 : .dp_blank =
412 : enc1_stream_encoder_dp_blank,
413 : .dp_unblank =
414 : enc314_stream_encoder_dp_unblank,
415 : .audio_mute_control = enc3_audio_mute_control,
416 :
417 : .dp_audio_setup = enc3_se_dp_audio_setup,
418 : .dp_audio_enable = enc3_se_dp_audio_enable,
419 : .dp_audio_disable = enc1_se_dp_audio_disable,
420 :
421 : .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
422 : .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
423 : .setup_stereo_sync = enc1_setup_stereo_sync,
424 : .set_avmute = enc1_stream_encoder_set_avmute,
425 : .dig_connect_to_otg = enc1_dig_connect_to_otg,
426 : .dig_source_otg = enc1_dig_source_otg,
427 :
428 : .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
429 :
430 : .enc_read_state = enc314_read_state,
431 : .dp_set_dsc_config = enc314_dp_set_dsc_config,
432 : .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
433 : .set_dynamic_metadata = enc2_set_dynamic_metadata,
434 : .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
435 :
436 : .enable_fifo = enc314_enable_fifo,
437 : .disable_fifo = enc314_disable_fifo,
438 : .set_input_mode = enc314_set_dig_input_mode,
439 : };
440 :
441 0 : void dcn314_dio_stream_encoder_construct(
442 : struct dcn10_stream_encoder *enc1,
443 : struct dc_context *ctx,
444 : struct dc_bios *bp,
445 : enum engine_id eng_id,
446 : struct vpg *vpg,
447 : struct afmt *afmt,
448 : const struct dcn10_stream_enc_registers *regs,
449 : const struct dcn10_stream_encoder_shift *se_shift,
450 : const struct dcn10_stream_encoder_mask *se_mask)
451 : {
452 0 : enc1->base.funcs = &dcn314_str_enc_funcs;
453 0 : enc1->base.ctx = ctx;
454 0 : enc1->base.id = eng_id;
455 0 : enc1->base.bp = bp;
456 0 : enc1->base.vpg = vpg;
457 0 : enc1->base.afmt = afmt;
458 0 : enc1->regs = regs;
459 0 : enc1->se_shift = se_shift;
460 0 : enc1->se_mask = se_mask;
461 0 : enc1->base.stream_enc_inst = vpg->inst;
462 0 : }
463 :
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