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1 : /*
2 : * Copyright 2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include "reg_helper.h"
27 : #include "core_types.h"
28 : #include "dcn32_dccg.h"
29 :
30 : #define TO_DCN_DCCG(dccg)\
31 : container_of(dccg, struct dcn_dccg, base)
32 :
33 : #define REG(reg) \
34 : (dccg_dcn->regs->reg)
35 :
36 : #undef FN
37 : #define FN(reg_name, field_name) \
38 : dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
39 :
40 : #define CTX \
41 : dccg_dcn->base.ctx
42 : #define DC_LOGGER \
43 : dccg->ctx->logger
44 :
45 0 : static void dccg32_set_pixel_rate_div(
46 : struct dccg *dccg,
47 : uint32_t otg_inst,
48 : enum pixel_rate_div k1,
49 : enum pixel_rate_div k2)
50 : {
51 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
52 :
53 0 : switch (otg_inst) {
54 : case 0:
55 0 : REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
56 : OTG0_PIXEL_RATE_DIVK1, k1,
57 : OTG0_PIXEL_RATE_DIVK2, k2);
58 0 : break;
59 : case 1:
60 0 : REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
61 : OTG1_PIXEL_RATE_DIVK1, k1,
62 : OTG1_PIXEL_RATE_DIVK2, k2);
63 0 : break;
64 : case 2:
65 0 : REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
66 : OTG2_PIXEL_RATE_DIVK1, k1,
67 : OTG2_PIXEL_RATE_DIVK2, k2);
68 0 : break;
69 : case 3:
70 0 : REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
71 : OTG3_PIXEL_RATE_DIVK1, k1,
72 : OTG3_PIXEL_RATE_DIVK2, k2);
73 0 : break;
74 : default:
75 0 : BREAK_TO_DEBUGGER();
76 0 : return;
77 : }
78 : }
79 :
80 0 : static void dccg32_set_dtbclk_p_src(
81 : struct dccg *dccg,
82 : enum streamclk_source src,
83 : uint32_t otg_inst)
84 : {
85 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
86 :
87 0 : uint32_t p_src_sel = 0; /* selects dprefclk */
88 0 : if (src == DTBCLK0)
89 0 : p_src_sel = 2; /* selects dtbclk0 */
90 :
91 0 : switch (otg_inst) {
92 : case 0:
93 0 : if (src == REFCLK)
94 0 : REG_UPDATE(DTBCLK_P_CNTL,
95 : DTBCLK_P0_EN, 0);
96 : else
97 0 : REG_UPDATE_2(DTBCLK_P_CNTL,
98 : DTBCLK_P0_SRC_SEL, p_src_sel,
99 : DTBCLK_P0_EN, 1);
100 : break;
101 : case 1:
102 0 : if (src == REFCLK)
103 0 : REG_UPDATE(DTBCLK_P_CNTL,
104 : DTBCLK_P1_EN, 0);
105 : else
106 0 : REG_UPDATE_2(DTBCLK_P_CNTL,
107 : DTBCLK_P1_SRC_SEL, p_src_sel,
108 : DTBCLK_P1_EN, 1);
109 : break;
110 : case 2:
111 0 : if (src == REFCLK)
112 0 : REG_UPDATE(DTBCLK_P_CNTL,
113 : DTBCLK_P2_EN, 0);
114 : else
115 0 : REG_UPDATE_2(DTBCLK_P_CNTL,
116 : DTBCLK_P2_SRC_SEL, p_src_sel,
117 : DTBCLK_P2_EN, 1);
118 : break;
119 : case 3:
120 0 : if (src == REFCLK)
121 0 : REG_UPDATE(DTBCLK_P_CNTL,
122 : DTBCLK_P3_EN, 0);
123 : else
124 0 : REG_UPDATE_2(DTBCLK_P_CNTL,
125 : DTBCLK_P3_SRC_SEL, p_src_sel,
126 : DTBCLK_P3_EN, 1);
127 : break;
128 : default:
129 0 : BREAK_TO_DEBUGGER();
130 0 : return;
131 : }
132 :
133 : }
134 :
135 : /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
136 0 : void dccg32_set_dtbclk_dto(
137 : struct dccg *dccg,
138 : const struct dtbclk_dto_params *params)
139 : {
140 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
141 : /* DTO Output Rate / Pixel Rate = 1/4 */
142 0 : int req_dtbclk_khz = params->pixclk_khz / 4;
143 :
144 0 : if (params->ref_dtbclk_khz && req_dtbclk_khz) {
145 : uint32_t modulo, phase;
146 :
147 : // phase / modulo = dtbclk / dtbclk ref
148 0 : modulo = params->ref_dtbclk_khz * 1000;
149 0 : phase = req_dtbclk_khz * 1000;
150 :
151 0 : REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
152 0 : REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
153 :
154 0 : REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
155 : DTBCLK_DTO_ENABLE[params->otg_inst], 1);
156 :
157 0 : REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst],
158 : DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1,
159 : 1, 100);
160 :
161 : /* program OTG_PIXEL_RATE_DIV for DIVK1 and DIVK2 fields */
162 0 : dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);
163 :
164 : /* The recommended programming sequence to enable DTBCLK DTO to generate
165 : * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
166 : * be set only after DTO is enabled
167 : */
168 0 : REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
169 : PIPE_DTO_SRC_SEL[params->otg_inst], 2);
170 : } else {
171 0 : REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
172 : DTBCLK_DTO_ENABLE[params->otg_inst], 0,
173 : PIPE_DTO_SRC_SEL[params->otg_inst], 1);
174 0 : if (params->is_hdmi)
175 0 : REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
176 : PIPE_DTO_SRC_SEL[params->otg_inst], 0);
177 :
178 0 : REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
179 0 : REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
180 : }
181 0 : }
182 :
183 0 : static void dccg32_set_valid_pixel_rate(
184 : struct dccg *dccg,
185 : int ref_dtbclk_khz,
186 : int otg_inst,
187 : int pixclk_khz)
188 : {
189 0 : struct dtbclk_dto_params dto_params = {0};
190 :
191 0 : dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
192 0 : dto_params.otg_inst = otg_inst;
193 0 : dto_params.pixclk_khz = pixclk_khz;
194 0 : dto_params.is_hdmi = true;
195 :
196 0 : dccg32_set_dtbclk_dto(dccg, &dto_params);
197 0 : }
198 :
199 0 : static void dccg32_get_dccg_ref_freq(struct dccg *dccg,
200 : unsigned int xtalin_freq_inKhz,
201 : unsigned int *dccg_ref_freq_inKhz)
202 : {
203 : /*
204 : * Assume refclk is sourced from xtalin
205 : * expect 100MHz
206 : */
207 0 : *dccg_ref_freq_inKhz = xtalin_freq_inKhz;
208 0 : return;
209 : }
210 :
211 0 : void dccg32_set_dpstreamclk(
212 : struct dccg *dccg,
213 : enum streamclk_source src,
214 : int otg_inst,
215 : int dp_hpo_inst)
216 : {
217 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
218 :
219 : /* set the dtbclk_p source */
220 0 : dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
221 :
222 : /* enabled to select one of the DTBCLKs for pipe */
223 0 : switch (otg_inst)
224 : {
225 : case 0:
226 0 : REG_UPDATE_2(DPSTREAMCLK_CNTL,
227 : DPSTREAMCLK0_EN,
228 : (src == REFCLK) ? 0 : 1, DPSTREAMCLK0_SRC_SEL, otg_inst);
229 0 : break;
230 : case 1:
231 0 : REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN,
232 : (src == REFCLK) ? 0 : 1, DPSTREAMCLK1_SRC_SEL, otg_inst);
233 0 : break;
234 : case 2:
235 0 : REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN,
236 : (src == REFCLK) ? 0 : 1, DPSTREAMCLK2_SRC_SEL, otg_inst);
237 0 : break;
238 : case 3:
239 0 : REG_UPDATE_2(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN,
240 : (src == REFCLK) ? 0 : 1, DPSTREAMCLK3_SRC_SEL, otg_inst);
241 0 : break;
242 : default:
243 0 : BREAK_TO_DEBUGGER();
244 0 : return;
245 : }
246 : }
247 :
248 0 : void dccg32_otg_add_pixel(struct dccg *dccg,
249 : uint32_t otg_inst)
250 : {
251 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
252 :
253 0 : REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
254 : OTG_ADD_PIXEL[otg_inst], 1);
255 0 : }
256 :
257 0 : void dccg32_otg_drop_pixel(struct dccg *dccg,
258 : uint32_t otg_inst)
259 : {
260 0 : struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
261 :
262 0 : REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
263 : OTG_DROP_PIXEL[otg_inst], 1);
264 0 : }
265 :
266 : static const struct dccg_funcs dccg32_funcs = {
267 : .update_dpp_dto = dccg2_update_dpp_dto,
268 : .get_dccg_ref_freq = dccg32_get_dccg_ref_freq,
269 : .dccg_init = dccg31_init,
270 : .set_dpstreamclk = dccg32_set_dpstreamclk,
271 : .enable_symclk32_se = dccg31_enable_symclk32_se,
272 : .disable_symclk32_se = dccg31_disable_symclk32_se,
273 : .enable_symclk32_le = dccg31_enable_symclk32_le,
274 : .disable_symclk32_le = dccg31_disable_symclk32_le,
275 : .set_physymclk = dccg31_set_physymclk,
276 : .set_dtbclk_dto = dccg32_set_dtbclk_dto,
277 : .set_valid_pixel_rate = dccg32_set_valid_pixel_rate,
278 : .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
279 : .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
280 : .otg_add_pixel = dccg32_otg_add_pixel,
281 : .otg_drop_pixel = dccg32_otg_drop_pixel,
282 : .set_pixel_rate_div = dccg32_set_pixel_rate_div,
283 : };
284 :
285 0 : struct dccg *dccg32_create(
286 : struct dc_context *ctx,
287 : const struct dccg_registers *regs,
288 : const struct dccg_shift *dccg_shift,
289 : const struct dccg_mask *dccg_mask)
290 : {
291 0 : struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
292 : struct dccg *base;
293 :
294 0 : if (dccg_dcn == NULL) {
295 0 : BREAK_TO_DEBUGGER();
296 0 : return NULL;
297 : }
298 :
299 0 : base = &dccg_dcn->base;
300 0 : base->ctx = ctx;
301 0 : base->funcs = &dccg32_funcs;
302 :
303 0 : dccg_dcn->regs = regs;
304 0 : dccg_dcn->dccg_shift = dccg_shift;
305 0 : dccg_dcn->dccg_mask = dccg_mask;
306 :
307 0 : return &dccg_dcn->base;
308 : }
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