Line data Source code
1 : /*
2 : * Copyright 2021 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 :
27 : #include "reg_helper.h"
28 :
29 : #include "core_types.h"
30 : #include "link_encoder.h"
31 : #include "dcn31/dcn31_dio_link_encoder.h"
32 : #include "dcn32_dio_link_encoder.h"
33 : #include "stream_encoder.h"
34 : #include "i2caux_interface.h"
35 : #include "dc_bios_types.h"
36 : #include "link_enc_cfg.h"
37 :
38 : #include "gpio_service_interface.h"
39 :
40 : #ifndef MIN
41 : #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
42 : #endif
43 :
44 : #define CTX \
45 : enc10->base.ctx
46 : #define DC_LOGGER \
47 : enc10->base.ctx->logger
48 :
49 : #define REG(reg)\
50 : (enc10->link_regs->reg)
51 :
52 : #undef FN
53 : #define FN(reg_name, field_name) \
54 : enc10->link_shift->field_name, enc10->link_mask->field_name
55 :
56 : #define AUX_REG(reg)\
57 : (enc10->aux_regs->reg)
58 :
59 : #define AUX_REG_READ(reg_name) \
60 : dm_read_reg(CTX, AUX_REG(reg_name))
61 :
62 : #define AUX_REG_WRITE(reg_name, val) \
63 : dm_write_reg(CTX, AUX_REG(reg_name), val)
64 :
65 :
66 0 : void enc32_hw_init(struct link_encoder *enc)
67 : {
68 0 : struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
69 :
70 : /*
71 : 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
72 : 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
73 : 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
74 : 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
75 : 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
76 : 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
77 : 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
78 : 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
79 : */
80 :
81 : /*
82 : AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
83 : AUX_RX_START_WINDOW = 1 [6:4]
84 : AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
85 : AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1
86 : AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
87 : AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0
88 : AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1
89 : AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1
90 : AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3
91 : AUX_RX_DETECTION_THRESHOLD [30:28] = 1
92 : */
93 0 : AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
94 :
95 0 : AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
96 :
97 : //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
98 : // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
99 : // 27MHz -> 0xd
100 : // 100MHz -> 0x32
101 : // 48MHz -> 0x18
102 :
103 : // Set TMDS_CTL0 to 1. This is a legacy setting.
104 0 : REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
105 :
106 0 : dcn10_aux_initialize(enc10);
107 0 : }
108 :
109 :
110 0 : void dcn32_link_encoder_enable_dp_output(
111 : struct link_encoder *enc,
112 : const struct dc_link_settings *link_settings,
113 : enum clock_source_id clock_source)
114 : {
115 0 : if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
116 0 : dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source);
117 0 : return;
118 : }
119 : }
120 :
121 0 : bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc)
122 : {
123 0 : struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
124 0 : uint32_t dp_alt_mode_disable = 0;
125 0 : bool is_usb_c_alt_mode = false;
126 :
127 0 : if (enc->features.flags.bits.DP_IS_USB_C) {
128 : /* if value == 1 alt mode is disabled, otherwise it is enabled */
129 0 : REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
130 0 : is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
131 : }
132 :
133 0 : return is_usb_c_alt_mode;
134 : }
135 :
136 0 : void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
137 : struct dc_link_settings *link_settings)
138 : {
139 0 : struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
140 0 : uint32_t is_in_usb_c_dp4_mode = 0;
141 :
142 0 : dcn10_link_encoder_get_max_link_cap(enc, link_settings);
143 :
144 : /* in usb c dp2 mode, max lane count is 2 */
145 0 : if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
146 0 : REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
147 0 : if (!is_in_usb_c_dp4_mode)
148 0 : link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
149 : }
150 :
151 0 : }
152 :
153 0 : void enc32_set_dig_output_mode(struct link_encoder *enc, uint8_t pix_per_container)
154 : {
155 0 : struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
156 0 : REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container);
157 0 : }
158 :
159 : static const struct link_encoder_funcs dcn32_link_enc_funcs = {
160 : .read_state = link_enc2_read_state,
161 : .validate_output_with_stream =
162 : dcn30_link_encoder_validate_output_with_stream,
163 : .hw_init = enc32_hw_init,
164 : .setup = dcn10_link_encoder_setup,
165 : .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
166 : .enable_dp_output = dcn32_link_encoder_enable_dp_output,
167 : .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
168 : .disable_output = dcn10_link_encoder_disable_output,
169 : .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
170 : .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
171 : .update_mst_stream_allocation_table =
172 : dcn10_link_encoder_update_mst_stream_allocation_table,
173 : .psr_program_dp_dphy_fast_training =
174 : dcn10_psr_program_dp_dphy_fast_training,
175 : .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
176 : .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
177 : .enable_hpd = dcn10_link_encoder_enable_hpd,
178 : .disable_hpd = dcn10_link_encoder_disable_hpd,
179 : .is_dig_enabled = dcn10_is_dig_enabled,
180 : .destroy = dcn10_link_encoder_destroy,
181 : .fec_set_enable = enc2_fec_set_enable,
182 : .fec_set_ready = enc2_fec_set_ready,
183 : .fec_is_active = enc2_fec_is_active,
184 : .get_dig_frontend = dcn10_get_dig_frontend,
185 : .get_dig_mode = dcn10_get_dig_mode,
186 : .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
187 : .get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
188 : .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
189 : .set_dig_output_mode = enc32_set_dig_output_mode,
190 : };
191 :
192 0 : void dcn32_link_encoder_construct(
193 : struct dcn20_link_encoder *enc20,
194 : const struct encoder_init_data *init_data,
195 : const struct encoder_feature_support *enc_features,
196 : const struct dcn10_link_enc_registers *link_regs,
197 : const struct dcn10_link_enc_aux_registers *aux_regs,
198 : const struct dcn10_link_enc_hpd_registers *hpd_regs,
199 : const struct dcn10_link_enc_shift *link_shift,
200 : const struct dcn10_link_enc_mask *link_mask)
201 : {
202 0 : struct bp_connector_speed_cap_info bp_cap_info = {0};
203 0 : const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
204 0 : enum bp_result result = BP_RESULT_OK;
205 0 : struct dcn10_link_encoder *enc10 = &enc20->enc10;
206 :
207 0 : enc10->base.funcs = &dcn32_link_enc_funcs;
208 0 : enc10->base.ctx = init_data->ctx;
209 0 : enc10->base.id = init_data->encoder;
210 :
211 0 : enc10->base.hpd_source = init_data->hpd_source;
212 0 : enc10->base.connector = init_data->connector;
213 :
214 0 : if (enc10->base.connector.id == CONNECTOR_ID_USBC)
215 0 : enc10->base.features.flags.bits.DP_IS_USB_C = 1;
216 :
217 0 : enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
218 :
219 0 : enc10->base.features = *enc_features;
220 :
221 0 : enc10->base.transmitter = init_data->transmitter;
222 :
223 : /* set the flag to indicate whether driver poll the I2C data pin
224 : * while doing the DP sink detect
225 : */
226 :
227 : /* if (dal_adapter_service_is_feature_supported(as,
228 : FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
229 : enc10->base.features.flags.bits.
230 : DP_SINK_DETECT_POLL_DATA_PIN = true;*/
231 :
232 0 : enc10->base.output_signals =
233 : SIGNAL_TYPE_DVI_SINGLE_LINK |
234 : SIGNAL_TYPE_DVI_DUAL_LINK |
235 : SIGNAL_TYPE_LVDS |
236 : SIGNAL_TYPE_DISPLAY_PORT |
237 : SIGNAL_TYPE_DISPLAY_PORT_MST |
238 : SIGNAL_TYPE_EDP |
239 : SIGNAL_TYPE_HDMI_TYPE_A;
240 :
241 0 : enc10->link_regs = link_regs;
242 0 : enc10->aux_regs = aux_regs;
243 0 : enc10->hpd_regs = hpd_regs;
244 0 : enc10->link_shift = link_shift;
245 0 : enc10->link_mask = link_mask;
246 :
247 0 : switch (enc10->base.transmitter) {
248 : case TRANSMITTER_UNIPHY_A:
249 0 : enc10->base.preferred_engine = ENGINE_ID_DIGA;
250 0 : break;
251 : case TRANSMITTER_UNIPHY_B:
252 0 : enc10->base.preferred_engine = ENGINE_ID_DIGB;
253 0 : break;
254 : case TRANSMITTER_UNIPHY_C:
255 0 : enc10->base.preferred_engine = ENGINE_ID_DIGC;
256 0 : break;
257 : case TRANSMITTER_UNIPHY_D:
258 0 : enc10->base.preferred_engine = ENGINE_ID_DIGD;
259 0 : break;
260 : case TRANSMITTER_UNIPHY_E:
261 0 : enc10->base.preferred_engine = ENGINE_ID_DIGE;
262 0 : break;
263 : default:
264 0 : ASSERT_CRITICAL(false);
265 0 : enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
266 : }
267 :
268 : /* default to one to mirror Windows behavior */
269 0 : enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
270 :
271 0 : if (bp_funcs->get_connector_speed_cap_info)
272 0 : result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
273 : enc10->base.connector, &bp_cap_info);
274 :
275 : /* Override features with DCE-specific values */
276 0 : if (result == BP_RESULT_OK) {
277 0 : enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
278 0 : bp_cap_info.DP_HBR2_EN;
279 0 : enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
280 0 : bp_cap_info.DP_HBR3_EN;
281 0 : enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
282 0 : enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
283 0 : enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
284 0 : enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
285 0 : enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
286 : } else {
287 0 : DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
288 : __func__,
289 : result);
290 : }
291 0 : if (enc10->base.ctx->dc->debug.hdmi20_disable) {
292 0 : enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
293 : }
294 0 : }
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