Line data Source code
1 : // SPDX-License-Identifier: MIT
2 : /*
3 : * Copyright 2019 Advanced Micro Devices, Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: AMD
24 : *
25 : */
26 :
27 : #include "dm_services.h"
28 : #include "dc.h"
29 :
30 : #include "dcn32/dcn32_init.h"
31 :
32 : #include "resource.h"
33 : #include "include/irq_service_interface.h"
34 : #include "dcn32/dcn32_resource.h"
35 : #include "dcn321_resource.h"
36 :
37 : #include "dcn20/dcn20_resource.h"
38 : #include "dcn30/dcn30_resource.h"
39 :
40 : #include "dml/dcn321/dcn321_fpu.h"
41 :
42 : #include "dcn10/dcn10_ipp.h"
43 : #include "dcn30/dcn30_hubbub.h"
44 : #include "dcn31/dcn31_hubbub.h"
45 : #include "dcn32/dcn32_hubbub.h"
46 : #include "dcn32/dcn32_mpc.h"
47 : #include "dcn32/dcn32_hubp.h"
48 : #include "irq/dcn32/irq_service_dcn32.h"
49 : #include "dcn32/dcn32_dpp.h"
50 : #include "dcn32/dcn32_optc.h"
51 : #include "dcn20/dcn20_hwseq.h"
52 : #include "dcn30/dcn30_hwseq.h"
53 : #include "dce110/dce110_hw_sequencer.h"
54 : #include "dcn30/dcn30_opp.h"
55 : #include "dcn20/dcn20_dsc.h"
56 : #include "dcn30/dcn30_vpg.h"
57 : #include "dcn30/dcn30_afmt.h"
58 : #include "dcn30/dcn30_dio_stream_encoder.h"
59 : #include "dcn32/dcn32_dio_stream_encoder.h"
60 : #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61 : #include "dcn31/dcn31_hpo_dp_link_encoder.h"
62 : #include "dcn32/dcn32_hpo_dp_link_encoder.h"
63 : #include "dc_link_dp.h"
64 : #include "dcn31/dcn31_apg.h"
65 : #include "dcn31/dcn31_dio_link_encoder.h"
66 : #include "dcn32/dcn32_dio_link_encoder.h"
67 : #include "dcn321_dio_link_encoder.h"
68 : #include "dce/dce_clock_source.h"
69 : #include "dce/dce_audio.h"
70 : #include "dce/dce_hwseq.h"
71 : #include "clk_mgr.h"
72 : #include "virtual/virtual_stream_encoder.h"
73 : #include "dml/display_mode_vba.h"
74 : #include "dcn32/dcn32_dccg.h"
75 : #include "dcn10/dcn10_resource.h"
76 : #include "dc_link_ddc.h"
77 : #include "dcn31/dcn31_panel_cntl.h"
78 :
79 : #include "dcn30/dcn30_dwb.h"
80 : #include "dcn32/dcn32_mmhubbub.h"
81 :
82 : #include "dcn/dcn_3_2_1_offset.h"
83 : #include "dcn/dcn_3_2_1_sh_mask.h"
84 : #include "nbio/nbio_4_3_0_offset.h"
85 :
86 : #include "reg_helper.h"
87 : #include "dce/dmub_abm.h"
88 : #include "dce/dmub_psr.h"
89 : #include "dce/dce_aux.h"
90 : #include "dce/dce_i2c.h"
91 :
92 : #include "dml/dcn30/display_mode_vba_30.h"
93 : #include "vm_helper.h"
94 : #include "dcn20/dcn20_vmid.h"
95 :
96 : #define DCN_BASE__INST0_SEG1 0x000000C0
97 : #define DCN_BASE__INST0_SEG2 0x000034C0
98 : #define DCN_BASE__INST0_SEG3 0x00009000
99 : #define NBIO_BASE__INST0_SEG1 0x00000014
100 :
101 : #define MAX_INSTANCE 8
102 : #define MAX_SEGMENT 6
103 :
104 : struct IP_BASE_INSTANCE {
105 : unsigned int segment[MAX_SEGMENT];
106 : };
107 :
108 : struct IP_BASE {
109 : struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
110 : };
111 :
112 : static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
113 : { { 0, 0, 0, 0, 0, 0 } },
114 : { { 0, 0, 0, 0, 0, 0 } },
115 : { { 0, 0, 0, 0, 0, 0 } },
116 : { { 0, 0, 0, 0, 0, 0 } },
117 : { { 0, 0, 0, 0, 0, 0 } },
118 : { { 0, 0, 0, 0, 0, 0 } },
119 : { { 0, 0, 0, 0, 0, 0 } } } };
120 :
121 : #define DC_LOGGER_INIT(logger)
122 : #define fixed16_to_double(x) (((double)x) / ((double) (1 << 16)))
123 : #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
124 :
125 : enum dcn321_clk_src_array_id {
126 : DCN321_CLK_SRC_PLL0,
127 : DCN321_CLK_SRC_PLL1,
128 : DCN321_CLK_SRC_PLL2,
129 : DCN321_CLK_SRC_PLL3,
130 : DCN321_CLK_SRC_PLL4,
131 : DCN321_CLK_SRC_TOTAL
132 : };
133 :
134 : /* begin *********************
135 : * macros to expend register list macro defined in HW object header file
136 : */
137 :
138 : /* DCN */
139 : /* TODO awful hack. fixup dcn20_dwb.h */
140 : #undef BASE_INNER
141 : #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
142 :
143 : #define BASE(seg) BASE_INNER(seg)
144 :
145 : #define SR(reg_name)\
146 : REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 : reg ## reg_name
148 : #define SR_ARR(reg_name, id)\
149 : REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 : reg ## reg_name
151 : #define SR_ARR_INIT(reg_name, id, value)\
152 : REG_STRUCT[id].reg_name = value
153 :
154 : #define SRI(reg_name, block, id)\
155 : REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
156 : reg ## block ## id ## _ ## reg_name
157 :
158 : #define SRI_ARR(reg_name, block, id)\
159 : REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
160 : reg ## block ## id ## _ ## reg_name
161 :
162 : #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
163 : REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 : reg ## block ## id ## _ ## reg_name
165 :
166 : #define SRI2(reg_name, block, id)\
167 : .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
168 : reg ## reg_name
169 : #define SRI2_ARR(reg_name, block, id)\
170 : REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
171 : reg ## reg_name
172 :
173 : #define SRIR(var_name, reg_name, block, id)\
174 : .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 : reg ## block ## id ## _ ## reg_name
176 :
177 : #define SRII(reg_name, block, id)\
178 : REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
179 : reg ## block ## id ## _ ## reg_name
180 :
181 : #define SRII_ARR_2(reg_name, block, id, inst)\
182 : REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 : reg ## block ## id ## _ ## reg_name
184 :
185 : #define SRII_MPC_RMU(reg_name, block, id)\
186 : .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
187 : reg ## block ## id ## _ ## reg_name
188 :
189 : #define SRII_DWB(reg_name, temp_name, block, id)\
190 : REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
191 : reg ## block ## id ## _ ## temp_name
192 :
193 : #define DCCG_SRII(reg_name, block, id)\
194 : REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
195 : reg ## block ## id ## _ ## reg_name
196 :
197 : #define VUPDATE_SRII(reg_name, block, id)\
198 : REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
199 : reg ## reg_name ## _ ## block ## id
200 :
201 : /* NBIO */
202 : #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
203 :
204 : #define NBIO_BASE(seg) \
205 : NBIO_BASE_INNER(seg)
206 :
207 : #define NBIO_SR(reg_name)\
208 : REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
209 : regBIF_BX0_ ## reg_name
210 : #define NBIO_SR_ARR(reg_name, id)\
211 : REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
212 : regBIF_BX0_ ## reg_name
213 :
214 : #define CTX ctx
215 : #define REG(reg_name) \
216 : (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
217 :
218 : static struct bios_registers bios_regs;
219 :
220 : #define bios_regs_init() \
221 : ( \
222 : NBIO_SR(BIOS_SCRATCH_3),\
223 : NBIO_SR(BIOS_SCRATCH_6)\
224 : )
225 :
226 : #define clk_src_regs_init(index, pllid)\
227 : CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
228 :
229 : static struct dce110_clk_src_regs clk_src_regs[5];
230 :
231 : static const struct dce110_clk_src_shift cs_shift = {
232 : CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
233 : };
234 :
235 : static const struct dce110_clk_src_mask cs_mask = {
236 : CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
237 : };
238 :
239 : #define abm_regs_init(id)\
240 : ABM_DCN32_REG_LIST_RI(id)
241 :
242 : static struct dce_abm_registers abm_regs[4];
243 :
244 : static const struct dce_abm_shift abm_shift = {
245 : ABM_MASK_SH_LIST_DCN32(__SHIFT)
246 : };
247 :
248 : static const struct dce_abm_mask abm_mask = {
249 : ABM_MASK_SH_LIST_DCN32(_MASK)
250 : };
251 :
252 : #define audio_regs_init(id)\
253 : AUD_COMMON_REG_LIST_RI(id)
254 :
255 : static struct dce_audio_registers audio_regs[5];
256 :
257 : #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
258 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
259 : SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
260 : AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
261 :
262 : static const struct dce_audio_shift audio_shift = {
263 : DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
264 : };
265 :
266 : static const struct dce_audio_mask audio_mask = {
267 : DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
268 : };
269 :
270 : #define vpg_regs_init(id)\
271 : VPG_DCN3_REG_LIST_RI(id)
272 :
273 : static struct dcn30_vpg_registers vpg_regs[10];
274 :
275 : static const struct dcn30_vpg_shift vpg_shift = {
276 : DCN3_VPG_MASK_SH_LIST(__SHIFT)
277 : };
278 :
279 : static const struct dcn30_vpg_mask vpg_mask = {
280 : DCN3_VPG_MASK_SH_LIST(_MASK)
281 : };
282 :
283 : #define afmt_regs_init(id)\
284 : AFMT_DCN3_REG_LIST_RI(id)
285 :
286 : static struct dcn30_afmt_registers afmt_regs[6];
287 :
288 : static const struct dcn30_afmt_shift afmt_shift = {
289 : DCN3_AFMT_MASK_SH_LIST(__SHIFT)
290 : };
291 :
292 : static const struct dcn30_afmt_mask afmt_mask = {
293 : DCN3_AFMT_MASK_SH_LIST(_MASK)
294 : };
295 :
296 : #define apg_regs_init(id)\
297 : APG_DCN31_REG_LIST_RI(id)
298 :
299 : static struct dcn31_apg_registers apg_regs[4];
300 :
301 : static const struct dcn31_apg_shift apg_shift = {
302 : DCN31_APG_MASK_SH_LIST(__SHIFT)
303 : };
304 :
305 : static const struct dcn31_apg_mask apg_mask = {
306 : DCN31_APG_MASK_SH_LIST(_MASK)
307 : };
308 :
309 : #define stream_enc_regs_init(id)\
310 : SE_DCN32_REG_LIST_RI(id)
311 :
312 : static struct dcn10_stream_enc_registers stream_enc_regs[5];
313 :
314 : static const struct dcn10_stream_encoder_shift se_shift = {
315 : SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
316 : };
317 :
318 : static const struct dcn10_stream_encoder_mask se_mask = {
319 : SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
320 : };
321 :
322 :
323 : #define aux_regs_init(id)\
324 : DCN2_AUX_REG_LIST_RI(id)
325 :
326 : static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
327 :
328 : #define hpd_regs_init(id)\
329 : HPD_REG_LIST_RI(id)
330 :
331 : static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
332 :
333 : #define link_regs_init(id, phyid)\
334 : ( \
335 : LE_DCN31_REG_LIST_RI(id), \
336 : UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
337 : )
338 : /*DPCS_DCN31_REG_LIST(id),*/ \
339 :
340 : static struct dcn10_link_enc_registers link_enc_regs[5];
341 :
342 : static const struct dcn10_link_enc_shift le_shift = {
343 : LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
344 : // DPCS_DCN31_MASK_SH_LIST(__SHIFT)
345 : };
346 :
347 : static const struct dcn10_link_enc_mask le_mask = {
348 : LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
349 : // DPCS_DCN31_MASK_SH_LIST(_MASK)
350 : };
351 :
352 : #define hpo_dp_stream_encoder_reg_init(id)\
353 : DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
354 :
355 : static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
356 :
357 : static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
358 : DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
359 : };
360 :
361 : static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
362 : DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
363 : };
364 :
365 :
366 : #define hpo_dp_link_encoder_reg_init(id)\
367 : DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
368 : /*DCN3_1_RDPCSTX_REG_LIST(0),*/
369 : /*DCN3_1_RDPCSTX_REG_LIST(1),*/
370 : /*DCN3_1_RDPCSTX_REG_LIST(2),*/
371 : /*DCN3_1_RDPCSTX_REG_LIST(3),*/
372 :
373 : static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
374 :
375 : static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
376 : DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
377 : };
378 :
379 : static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
380 : DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
381 : };
382 :
383 : #define dpp_regs_init(id)\
384 : DPP_REG_LIST_DCN30_COMMON_RI(id)
385 :
386 : static struct dcn3_dpp_registers dpp_regs[4];
387 :
388 : static const struct dcn3_dpp_shift tf_shift = {
389 : DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
390 : };
391 :
392 : static const struct dcn3_dpp_mask tf_mask = {
393 : DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
394 : };
395 :
396 :
397 : #define opp_regs_init(id)\
398 : OPP_REG_LIST_DCN30_RI(id)
399 :
400 : static struct dcn20_opp_registers opp_regs[4];
401 :
402 : static const struct dcn20_opp_shift opp_shift = {
403 : OPP_MASK_SH_LIST_DCN20(__SHIFT)
404 : };
405 :
406 : static const struct dcn20_opp_mask opp_mask = {
407 : OPP_MASK_SH_LIST_DCN20(_MASK)
408 : };
409 :
410 : #define aux_engine_regs_init(id) \
411 : ( \
412 : AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
413 : SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
414 : SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
415 : SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
416 : )
417 :
418 : static struct dce110_aux_registers aux_engine_regs[5];
419 :
420 : static const struct dce110_aux_registers_shift aux_shift = {
421 : DCN_AUX_MASK_SH_LIST(__SHIFT)
422 : };
423 :
424 : static const struct dce110_aux_registers_mask aux_mask = {
425 : DCN_AUX_MASK_SH_LIST(_MASK)
426 : };
427 :
428 : #define dwbc_regs_dcn3_init(id)\
429 : DWBC_COMMON_REG_LIST_DCN30_RI(id)
430 :
431 : static struct dcn30_dwbc_registers dwbc30_regs[1];
432 :
433 : static const struct dcn30_dwbc_shift dwbc30_shift = {
434 : DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
435 : };
436 :
437 : static const struct dcn30_dwbc_mask dwbc30_mask = {
438 : DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
439 : };
440 :
441 : #define mcif_wb_regs_dcn3_init(id)\
442 : MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
443 :
444 : static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
445 :
446 : static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
447 : MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
448 : };
449 :
450 : static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
451 : MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
452 : };
453 :
454 : #define dsc_regsDCN20_init(id)\
455 : DSC_REG_LIST_DCN20_RI(id)
456 :
457 : static struct dcn20_dsc_registers dsc_regs[4];
458 :
459 : static const struct dcn20_dsc_shift dsc_shift = {
460 : DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
461 : };
462 :
463 : static const struct dcn20_dsc_mask dsc_mask = {
464 : DSC_REG_LIST_SH_MASK_DCN20(_MASK)
465 : };
466 :
467 : static struct dcn30_mpc_registers mpc_regs;
468 : #define dcn_mpc_regs_init()\
469 : ( \
470 : MPC_REG_LIST_DCN3_0_RI(0),\
471 : MPC_REG_LIST_DCN3_0_RI(1),\
472 : MPC_REG_LIST_DCN3_0_RI(2),\
473 : MPC_REG_LIST_DCN3_0_RI(3),\
474 : MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
475 : MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
476 : MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
477 : MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
478 : MPC_MCM_REG_LIST_DCN32_RI(0),\
479 : MPC_MCM_REG_LIST_DCN32_RI(1),\
480 : MPC_MCM_REG_LIST_DCN32_RI(2),\
481 : MPC_MCM_REG_LIST_DCN32_RI(3),\
482 : MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)\
483 : )
484 :
485 : static const struct dcn30_mpc_shift mpc_shift = {
486 : MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
487 : };
488 :
489 : static const struct dcn30_mpc_mask mpc_mask = {
490 : MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
491 : };
492 :
493 : #define optc_regs_init(id)\
494 : OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
495 :
496 : static struct dcn_optc_registers optc_regs[4];
497 :
498 : static const struct dcn_optc_shift optc_shift = {
499 : OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
500 : };
501 :
502 : static const struct dcn_optc_mask optc_mask = {
503 : OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
504 : };
505 :
506 : #define hubp_regs_init(id) \
507 : HUBP_REG_LIST_DCN32_RI(id)
508 :
509 : static struct dcn_hubp2_registers hubp_regs[4];
510 :
511 : static const struct dcn_hubp2_shift hubp_shift = {
512 : HUBP_MASK_SH_LIST_DCN32(__SHIFT)
513 : };
514 :
515 : static const struct dcn_hubp2_mask hubp_mask = {
516 : HUBP_MASK_SH_LIST_DCN32(_MASK)
517 : };
518 :
519 : static struct dcn_hubbub_registers hubbub_reg;
520 : #define hubbub_reg_init()\
521 : HUBBUB_REG_LIST_DCN32_RI(0)
522 :
523 : static const struct dcn_hubbub_shift hubbub_shift = {
524 : HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
525 : };
526 :
527 : static const struct dcn_hubbub_mask hubbub_mask = {
528 : HUBBUB_MASK_SH_LIST_DCN32(_MASK)
529 : };
530 :
531 : static struct dccg_registers dccg_regs;
532 :
533 : #define dccg_regs_init()\
534 : DCCG_REG_LIST_DCN32_RI()
535 :
536 : static const struct dccg_shift dccg_shift = {
537 : DCCG_MASK_SH_LIST_DCN32(__SHIFT)
538 : };
539 :
540 : static const struct dccg_mask dccg_mask = {
541 : DCCG_MASK_SH_LIST_DCN32(_MASK)
542 : };
543 :
544 :
545 : #define SRII2(reg_name_pre, reg_name_post, id)\
546 : .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
547 : ## id ## _ ## reg_name_post ## _BASE_IDX) + \
548 : reg ## reg_name_pre ## id ## _ ## reg_name_post
549 :
550 :
551 : #define HWSEQ_DCN32_REG_LIST()\
552 : SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
553 : SR(DIO_MEM_PWR_CTRL), \
554 : SR(ODM_MEM_PWR_CTRL3), \
555 : SR(MMHUBBUB_MEM_PWR_CNTL), \
556 : SR(DCCG_GATE_DISABLE_CNTL), \
557 : SR(DCCG_GATE_DISABLE_CNTL2), \
558 : SR(DCFCLK_CNTL),\
559 : SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
560 : SRII(PIXEL_RATE_CNTL, OTG, 0), \
561 : SRII(PIXEL_RATE_CNTL, OTG, 1),\
562 : SRII(PIXEL_RATE_CNTL, OTG, 2),\
563 : SRII(PIXEL_RATE_CNTL, OTG, 3),\
564 : SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
565 : SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
566 : SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
567 : SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
568 : SR(MICROSECOND_TIME_BASE_DIV), \
569 : SR(MILLISECOND_TIME_BASE_DIV), \
570 : SR(DISPCLK_FREQ_CHANGE_CNTL), \
571 : SR(RBBMIF_TIMEOUT_DIS), \
572 : SR(RBBMIF_TIMEOUT_DIS_2), \
573 : SR(DCHUBBUB_CRC_CTRL), \
574 : SR(DPP_TOP0_DPP_CRC_CTRL), \
575 : SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
576 : SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
577 : SR(MPC_CRC_CTRL), \
578 : SR(MPC_CRC_RESULT_GB), \
579 : SR(MPC_CRC_RESULT_C), \
580 : SR(MPC_CRC_RESULT_AR), \
581 : SR(DOMAIN0_PG_CONFIG), \
582 : SR(DOMAIN1_PG_CONFIG), \
583 : SR(DOMAIN2_PG_CONFIG), \
584 : SR(DOMAIN3_PG_CONFIG), \
585 : SR(DOMAIN16_PG_CONFIG), \
586 : SR(DOMAIN17_PG_CONFIG), \
587 : SR(DOMAIN18_PG_CONFIG), \
588 : SR(DOMAIN19_PG_CONFIG), \
589 : SR(DOMAIN0_PG_STATUS), \
590 : SR(DOMAIN1_PG_STATUS), \
591 : SR(DOMAIN2_PG_STATUS), \
592 : SR(DOMAIN3_PG_STATUS), \
593 : SR(DOMAIN16_PG_STATUS), \
594 : SR(DOMAIN17_PG_STATUS), \
595 : SR(DOMAIN18_PG_STATUS), \
596 : SR(DOMAIN19_PG_STATUS), \
597 : SR(D1VGA_CONTROL), \
598 : SR(D2VGA_CONTROL), \
599 : SR(D3VGA_CONTROL), \
600 : SR(D4VGA_CONTROL), \
601 : SR(D5VGA_CONTROL), \
602 : SR(D6VGA_CONTROL), \
603 : SR(DC_IP_REQUEST_CNTL), \
604 : SR(AZALIA_AUDIO_DTO), \
605 : SR(AZALIA_CONTROLLER_CLOCK_GATING)
606 :
607 : static struct dce_hwseq_registers hwseq_reg;
608 :
609 : #define hwseq_reg_init()\
610 : HWSEQ_DCN32_REG_LIST()
611 :
612 : #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
613 : HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
614 : HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
615 : HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
616 : HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
617 : HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
618 : HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
619 : HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
620 : HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
621 : HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
622 : HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
623 : HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
624 : HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
625 : HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
626 : HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
627 : HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
628 : HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
629 : HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
630 : HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
631 : HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
632 : HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
633 : HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
634 : HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
635 : HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
636 : HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
637 : HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
638 : HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
639 : HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
640 : HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
641 : HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
642 : HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
643 : HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
644 : HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
645 :
646 : static const struct dce_hwseq_shift hwseq_shift = {
647 : HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
648 : };
649 :
650 : static const struct dce_hwseq_mask hwseq_mask = {
651 : HWSEQ_DCN32_MASK_SH_LIST(_MASK)
652 : };
653 : #define vmid_regs_init(id)\
654 : DCN20_VMID_REG_LIST_RI(id)
655 :
656 : static struct dcn_vmid_registers vmid_regs[16];
657 :
658 : static const struct dcn20_vmid_shift vmid_shifts = {
659 : DCN20_VMID_MASK_SH_LIST(__SHIFT)
660 : };
661 :
662 : static const struct dcn20_vmid_mask vmid_masks = {
663 : DCN20_VMID_MASK_SH_LIST(_MASK)
664 : };
665 :
666 : static const struct resource_caps res_cap_dcn321 = {
667 : .num_timing_generator = 4,
668 : .num_opp = 4,
669 : .num_video_plane = 4,
670 : .num_audio = 5,
671 : .num_stream_encoder = 5,
672 : .num_hpo_dp_stream_encoder = 4,
673 : .num_hpo_dp_link_encoder = 2,
674 : .num_pll = 5,
675 : .num_dwb = 1,
676 : .num_ddc = 5,
677 : .num_vmid = 16,
678 : .num_mpc_3dlut = 4,
679 : .num_dsc = 4,
680 : };
681 :
682 : static const struct dc_plane_cap plane_cap = {
683 : .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
684 : .blends_with_above = true,
685 : .blends_with_below = true,
686 : .per_pixel_alpha = true,
687 :
688 : .pixel_format_support = {
689 : .argb8888 = true,
690 : .nv12 = true,
691 : .fp16 = true,
692 : .p010 = true,
693 : .ayuv = false,
694 : },
695 :
696 : .max_upscale_factor = {
697 : .argb8888 = 16000,
698 : .nv12 = 16000,
699 : .fp16 = 16000
700 : },
701 :
702 : // 6:1 downscaling ratio: 1000/6 = 166.666
703 : .max_downscale_factor = {
704 : .argb8888 = 167,
705 : .nv12 = 167,
706 : .fp16 = 167
707 : },
708 : 64,
709 : 64
710 : };
711 :
712 : static const struct dc_debug_options debug_defaults_drv = {
713 : .disable_dmcu = true,
714 : .force_abm_enable = false,
715 : .timing_trace = false,
716 : .clock_trace = true,
717 : .disable_pplib_clock_request = false,
718 : .pipe_split_policy = MPC_SPLIT_AVOID,
719 : .force_single_disp_pipe_split = false,
720 : .disable_dcc = DCC_ENABLE,
721 : .vsr_support = true,
722 : .performance_trace = false,
723 : .max_downscale_src_width = 7680,/*upto 8K*/
724 : .disable_pplib_wm_range = false,
725 : .scl_reset_length10 = true,
726 : .sanity_checks = false,
727 : .underflow_assert_delay_us = 0xFFFFFFFF,
728 : .dwb_fi_phase = -1, // -1 = disable,
729 : .dmub_command_table = true,
730 : .enable_mem_low_power = {
731 : .bits = {
732 : .vga = false,
733 : .i2c = false,
734 : .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
735 : .dscl = false,
736 : .cm = false,
737 : .mpc = false,
738 : .optc = true,
739 : }
740 : },
741 : .use_max_lb = true,
742 : .force_disable_subvp = false,
743 : .exit_idle_opt_for_cursor_updates = true,
744 : .enable_single_display_2to1_odm_policy = true,
745 : .enable_dp_dig_pixel_rate_div_policy = 1,
746 : };
747 :
748 : static const struct dc_debug_options debug_defaults_diags = {
749 : .disable_dmcu = true,
750 : .force_abm_enable = false,
751 : .timing_trace = true,
752 : .clock_trace = true,
753 : .disable_dpp_power_gate = true,
754 : .disable_hubp_power_gate = true,
755 : .disable_dsc_power_gate = true,
756 : .disable_clock_gate = true,
757 : .disable_pplib_clock_request = true,
758 : .disable_pplib_wm_range = true,
759 : .disable_stutter = false,
760 : .scl_reset_length10 = true,
761 : .dwb_fi_phase = -1, // -1 = disable
762 : .dmub_command_table = true,
763 : .enable_tri_buf = true,
764 : .use_max_lb = true,
765 : .force_disable_subvp = true
766 : };
767 :
768 :
769 0 : static struct dce_aux *dcn321_aux_engine_create(
770 : struct dc_context *ctx,
771 : uint32_t inst)
772 : {
773 0 : struct aux_engine_dce110 *aux_engine =
774 : kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
775 :
776 0 : if (!aux_engine)
777 : return NULL;
778 :
779 : #undef REG_STRUCT
780 : #define REG_STRUCT aux_engine_regs
781 0 : aux_engine_regs_init(0),
782 0 : aux_engine_regs_init(1),
783 0 : aux_engine_regs_init(2),
784 0 : aux_engine_regs_init(3),
785 0 : aux_engine_regs_init(4);
786 :
787 0 : dce110_aux_engine_construct(aux_engine, ctx, inst,
788 : SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
789 0 : &aux_engine_regs[inst],
790 : &aux_mask,
791 : &aux_shift,
792 0 : ctx->dc->caps.extended_aux_timeout_support);
793 :
794 0 : return &aux_engine->base;
795 : }
796 : #define i2c_inst_regs_init(id)\
797 : I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
798 :
799 : static struct dce_i2c_registers i2c_hw_regs[6];
800 :
801 : static const struct dce_i2c_shift i2c_shifts = {
802 : I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
803 : };
804 :
805 : static const struct dce_i2c_mask i2c_masks = {
806 : I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
807 : };
808 :
809 0 : static struct dce_i2c_hw *dcn321_i2c_hw_create(
810 : struct dc_context *ctx,
811 : uint32_t inst)
812 : {
813 0 : struct dce_i2c_hw *dce_i2c_hw =
814 : kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
815 :
816 0 : if (!dce_i2c_hw)
817 : return NULL;
818 :
819 : #undef REG_STRUCT
820 : #define REG_STRUCT i2c_hw_regs
821 0 : i2c_inst_regs_init(1),
822 0 : i2c_inst_regs_init(2),
823 0 : i2c_inst_regs_init(3),
824 0 : i2c_inst_regs_init(4),
825 0 : i2c_inst_regs_init(5);
826 :
827 0 : dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
828 0 : &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
829 :
830 0 : return dce_i2c_hw;
831 : }
832 :
833 0 : static struct clock_source *dcn321_clock_source_create(
834 : struct dc_context *ctx,
835 : struct dc_bios *bios,
836 : enum clock_source_id id,
837 : const struct dce110_clk_src_regs *regs,
838 : bool dp_clk_src)
839 : {
840 0 : struct dce110_clk_src *clk_src =
841 : kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
842 :
843 0 : if (!clk_src)
844 : return NULL;
845 :
846 0 : if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
847 : regs, &cs_shift, &cs_mask)) {
848 0 : clk_src->base.dp_clk_src = dp_clk_src;
849 0 : return &clk_src->base;
850 : }
851 :
852 0 : BREAK_TO_DEBUGGER();
853 0 : return NULL;
854 : }
855 :
856 0 : static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx)
857 : {
858 : int i;
859 :
860 0 : struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
861 : GFP_KERNEL);
862 :
863 0 : if (!hubbub2)
864 : return NULL;
865 :
866 : #undef REG_STRUCT
867 : #define REG_STRUCT hubbub_reg
868 0 : hubbub_reg_init();
869 :
870 : #undef REG_STRUCT
871 : #define REG_STRUCT vmid_regs
872 0 : vmid_regs_init(0),
873 0 : vmid_regs_init(1),
874 0 : vmid_regs_init(2),
875 0 : vmid_regs_init(3),
876 0 : vmid_regs_init(4),
877 0 : vmid_regs_init(5),
878 0 : vmid_regs_init(6),
879 0 : vmid_regs_init(7),
880 0 : vmid_regs_init(8),
881 0 : vmid_regs_init(9),
882 0 : vmid_regs_init(10),
883 0 : vmid_regs_init(11),
884 0 : vmid_regs_init(12),
885 0 : vmid_regs_init(13),
886 0 : vmid_regs_init(14),
887 0 : vmid_regs_init(15);
888 :
889 0 : hubbub32_construct(hubbub2, ctx,
890 : &hubbub_reg,
891 : &hubbub_shift,
892 : &hubbub_mask,
893 0 : ctx->dc->dml.ip.det_buffer_size_kbytes,
894 0 : ctx->dc->dml.ip.pixel_chunk_size_kbytes,
895 0 : ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
896 :
897 :
898 0 : for (i = 0; i < res_cap_dcn321.num_vmid; i++) {
899 0 : struct dcn20_vmid *vmid = &hubbub2->vmid[i];
900 :
901 0 : vmid->ctx = ctx;
902 :
903 0 : vmid->regs = &vmid_regs[i];
904 0 : vmid->shifts = &vmid_shifts;
905 0 : vmid->masks = &vmid_masks;
906 : }
907 :
908 0 : return &hubbub2->base;
909 : }
910 :
911 0 : static struct hubp *dcn321_hubp_create(
912 : struct dc_context *ctx,
913 : uint32_t inst)
914 : {
915 0 : struct dcn20_hubp *hubp2 =
916 : kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
917 :
918 0 : if (!hubp2)
919 : return NULL;
920 :
921 : #undef REG_STRUCT
922 : #define REG_STRUCT hubp_regs
923 0 : hubp_regs_init(0),
924 0 : hubp_regs_init(1),
925 0 : hubp_regs_init(2),
926 0 : hubp_regs_init(3);
927 :
928 0 : if (hubp32_construct(hubp2, ctx, inst,
929 0 : &hubp_regs[inst], &hubp_shift, &hubp_mask))
930 0 : return &hubp2->base;
931 :
932 0 : BREAK_TO_DEBUGGER();
933 0 : kfree(hubp2);
934 0 : return NULL;
935 : }
936 :
937 : static void dcn321_dpp_destroy(struct dpp **dpp)
938 : {
939 0 : kfree(TO_DCN30_DPP(*dpp));
940 0 : *dpp = NULL;
941 : }
942 :
943 0 : static struct dpp *dcn321_dpp_create(
944 : struct dc_context *ctx,
945 : uint32_t inst)
946 : {
947 0 : struct dcn3_dpp *dpp3 =
948 : kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
949 :
950 0 : if (!dpp3)
951 : return NULL;
952 :
953 : #undef REG_STRUCT
954 : #define REG_STRUCT dpp_regs
955 0 : dpp_regs_init(0),
956 0 : dpp_regs_init(1),
957 0 : dpp_regs_init(2),
958 0 : dpp_regs_init(3);
959 :
960 0 : if (dpp32_construct(dpp3, ctx, inst,
961 0 : &dpp_regs[inst], &tf_shift, &tf_mask))
962 0 : return &dpp3->base;
963 :
964 0 : BREAK_TO_DEBUGGER();
965 0 : kfree(dpp3);
966 0 : return NULL;
967 : }
968 :
969 0 : static struct mpc *dcn321_mpc_create(
970 : struct dc_context *ctx,
971 : int num_mpcc,
972 : int num_rmu)
973 : {
974 0 : struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
975 : GFP_KERNEL);
976 :
977 0 : if (!mpc30)
978 : return NULL;
979 :
980 : #undef REG_STRUCT
981 : #define REG_STRUCT mpc_regs
982 0 : dcn_mpc_regs_init();
983 :
984 0 : dcn32_mpc_construct(mpc30, ctx,
985 : &mpc_regs,
986 : &mpc_shift,
987 : &mpc_mask,
988 : num_mpcc,
989 : num_rmu);
990 :
991 0 : return &mpc30->base;
992 : }
993 :
994 0 : static struct output_pixel_processor *dcn321_opp_create(
995 : struct dc_context *ctx, uint32_t inst)
996 : {
997 0 : struct dcn20_opp *opp2 =
998 : kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
999 :
1000 0 : if (!opp2) {
1001 0 : BREAK_TO_DEBUGGER();
1002 0 : return NULL;
1003 : }
1004 :
1005 : #undef REG_STRUCT
1006 : #define REG_STRUCT opp_regs
1007 0 : opp_regs_init(0),
1008 0 : opp_regs_init(1),
1009 0 : opp_regs_init(2),
1010 0 : opp_regs_init(3);
1011 :
1012 0 : dcn20_opp_construct(opp2, ctx, inst,
1013 0 : &opp_regs[inst], &opp_shift, &opp_mask);
1014 0 : return &opp2->base;
1015 : }
1016 :
1017 :
1018 0 : static struct timing_generator *dcn321_timing_generator_create(
1019 : struct dc_context *ctx,
1020 : uint32_t instance)
1021 : {
1022 0 : struct optc *tgn10 =
1023 : kzalloc(sizeof(struct optc), GFP_KERNEL);
1024 :
1025 0 : if (!tgn10)
1026 : return NULL;
1027 :
1028 : #undef REG_STRUCT
1029 : #define REG_STRUCT optc_regs
1030 0 : optc_regs_init(0),
1031 0 : optc_regs_init(1),
1032 0 : optc_regs_init(2),
1033 0 : optc_regs_init(3);
1034 :
1035 0 : tgn10->base.inst = instance;
1036 0 : tgn10->base.ctx = ctx;
1037 :
1038 0 : tgn10->tg_regs = &optc_regs[instance];
1039 0 : tgn10->tg_shift = &optc_shift;
1040 0 : tgn10->tg_mask = &optc_mask;
1041 :
1042 0 : dcn32_timing_generator_init(tgn10);
1043 :
1044 0 : return &tgn10->base;
1045 : }
1046 :
1047 : static const struct encoder_feature_support link_enc_feature = {
1048 : .max_hdmi_deep_color = COLOR_DEPTH_121212,
1049 : .max_hdmi_pixel_clock = 600000,
1050 : .hdmi_ycbcr420_supported = true,
1051 : .dp_ycbcr420_supported = true,
1052 : .fec_supported = true,
1053 : .flags.bits.IS_HBR2_CAPABLE = true,
1054 : .flags.bits.IS_HBR3_CAPABLE = true,
1055 : .flags.bits.IS_TPS3_CAPABLE = true,
1056 : .flags.bits.IS_TPS4_CAPABLE = true
1057 : };
1058 :
1059 0 : static struct link_encoder *dcn321_link_encoder_create(
1060 : struct dc_context *ctx,
1061 : const struct encoder_init_data *enc_init_data)
1062 : {
1063 0 : struct dcn20_link_encoder *enc20 =
1064 : kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1065 :
1066 0 : if (!enc20)
1067 : return NULL;
1068 :
1069 : #undef REG_STRUCT
1070 : #define REG_STRUCT link_enc_aux_regs
1071 0 : aux_regs_init(0),
1072 0 : aux_regs_init(1),
1073 0 : aux_regs_init(2),
1074 0 : aux_regs_init(3),
1075 0 : aux_regs_init(4);
1076 :
1077 : #undef REG_STRUCT
1078 : #define REG_STRUCT link_enc_hpd_regs
1079 0 : hpd_regs_init(0),
1080 0 : hpd_regs_init(1),
1081 0 : hpd_regs_init(2),
1082 0 : hpd_regs_init(3),
1083 0 : hpd_regs_init(4);
1084 :
1085 : #undef REG_STRUCT
1086 : #define REG_STRUCT link_enc_regs
1087 0 : link_regs_init(0, A),
1088 0 : link_regs_init(1, B),
1089 0 : link_regs_init(2, C),
1090 0 : link_regs_init(3, D),
1091 0 : link_regs_init(4, E);
1092 :
1093 0 : dcn321_link_encoder_construct(enc20,
1094 : enc_init_data,
1095 : &link_enc_feature,
1096 0 : &link_enc_regs[enc_init_data->transmitter],
1097 0 : &link_enc_aux_regs[enc_init_data->channel - 1],
1098 0 : &link_enc_hpd_regs[enc_init_data->hpd_source],
1099 : &le_shift,
1100 : &le_mask);
1101 :
1102 0 : return &enc20->enc10.base;
1103 : }
1104 :
1105 0 : static void read_dce_straps(
1106 : struct dc_context *ctx,
1107 : struct resource_straps *straps)
1108 : {
1109 0 : generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1110 : FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1111 :
1112 0 : }
1113 :
1114 0 : static struct audio *dcn321_create_audio(
1115 : struct dc_context *ctx, unsigned int inst)
1116 : {
1117 :
1118 : #undef REG_STRUCT
1119 : #define REG_STRUCT audio_regs
1120 0 : audio_regs_init(0),
1121 0 : audio_regs_init(1),
1122 0 : audio_regs_init(2),
1123 0 : audio_regs_init(3),
1124 0 : audio_regs_init(4);
1125 :
1126 0 : return dce_audio_create(ctx, inst,
1127 0 : &audio_regs[inst], &audio_shift, &audio_mask);
1128 : }
1129 :
1130 0 : static struct vpg *dcn321_vpg_create(
1131 : struct dc_context *ctx,
1132 : uint32_t inst)
1133 : {
1134 0 : struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1135 :
1136 0 : if (!vpg3)
1137 : return NULL;
1138 :
1139 : #undef REG_STRUCT
1140 : #define REG_STRUCT vpg_regs
1141 0 : vpg_regs_init(0),
1142 0 : vpg_regs_init(1),
1143 0 : vpg_regs_init(2),
1144 0 : vpg_regs_init(3),
1145 0 : vpg_regs_init(4),
1146 0 : vpg_regs_init(5),
1147 0 : vpg_regs_init(6),
1148 0 : vpg_regs_init(7),
1149 0 : vpg_regs_init(8),
1150 0 : vpg_regs_init(9);
1151 :
1152 0 : vpg3_construct(vpg3, ctx, inst,
1153 0 : &vpg_regs[inst],
1154 : &vpg_shift,
1155 : &vpg_mask);
1156 :
1157 0 : return &vpg3->base;
1158 : }
1159 :
1160 0 : static struct afmt *dcn321_afmt_create(
1161 : struct dc_context *ctx,
1162 : uint32_t inst)
1163 : {
1164 0 : struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1165 :
1166 0 : if (!afmt3)
1167 : return NULL;
1168 :
1169 : #undef REG_STRUCT
1170 : #define REG_STRUCT afmt_regs
1171 0 : afmt_regs_init(0),
1172 0 : afmt_regs_init(1),
1173 0 : afmt_regs_init(2),
1174 0 : afmt_regs_init(3),
1175 0 : afmt_regs_init(4),
1176 0 : afmt_regs_init(5);
1177 :
1178 0 : afmt3_construct(afmt3, ctx, inst,
1179 0 : &afmt_regs[inst],
1180 : &afmt_shift,
1181 : &afmt_mask);
1182 :
1183 0 : return &afmt3->base;
1184 : }
1185 :
1186 0 : static struct apg *dcn321_apg_create(
1187 : struct dc_context *ctx,
1188 : uint32_t inst)
1189 : {
1190 0 : struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1191 :
1192 0 : if (!apg31)
1193 : return NULL;
1194 :
1195 : #undef REG_STRUCT
1196 : #define REG_STRUCT apg_regs
1197 0 : apg_regs_init(0),
1198 0 : apg_regs_init(1),
1199 0 : apg_regs_init(2),
1200 0 : apg_regs_init(3);
1201 :
1202 0 : apg31_construct(apg31, ctx, inst,
1203 0 : &apg_regs[inst],
1204 : &apg_shift,
1205 : &apg_mask);
1206 :
1207 0 : return &apg31->base;
1208 : }
1209 :
1210 0 : static struct stream_encoder *dcn321_stream_encoder_create(
1211 : enum engine_id eng_id,
1212 : struct dc_context *ctx)
1213 : {
1214 : struct dcn10_stream_encoder *enc1;
1215 : struct vpg *vpg;
1216 : struct afmt *afmt;
1217 : int vpg_inst;
1218 : int afmt_inst;
1219 :
1220 : /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1221 0 : if (eng_id <= ENGINE_ID_DIGF) {
1222 0 : vpg_inst = eng_id;
1223 0 : afmt_inst = eng_id;
1224 : } else
1225 : return NULL;
1226 :
1227 0 : enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1228 0 : vpg = dcn321_vpg_create(ctx, vpg_inst);
1229 0 : afmt = dcn321_afmt_create(ctx, afmt_inst);
1230 :
1231 0 : if (!enc1 || !vpg || !afmt) {
1232 0 : kfree(enc1);
1233 0 : kfree(vpg);
1234 0 : kfree(afmt);
1235 0 : return NULL;
1236 : }
1237 :
1238 : #undef REG_STRUCT
1239 : #define REG_STRUCT stream_enc_regs
1240 0 : stream_enc_regs_init(0),
1241 0 : stream_enc_regs_init(1),
1242 0 : stream_enc_regs_init(2),
1243 0 : stream_enc_regs_init(3),
1244 0 : stream_enc_regs_init(4);
1245 :
1246 0 : dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1247 : eng_id, vpg, afmt,
1248 0 : &stream_enc_regs[eng_id],
1249 : &se_shift, &se_mask);
1250 :
1251 0 : return &enc1->base;
1252 : }
1253 :
1254 0 : static struct hpo_dp_stream_encoder *dcn321_hpo_dp_stream_encoder_create(
1255 : enum engine_id eng_id,
1256 : struct dc_context *ctx)
1257 : {
1258 : struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1259 : struct vpg *vpg;
1260 : struct apg *apg;
1261 : uint32_t hpo_dp_inst;
1262 : uint32_t vpg_inst;
1263 : uint32_t apg_inst;
1264 :
1265 0 : ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1266 0 : hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1267 :
1268 : /* Mapping of VPG register blocks to HPO DP block instance:
1269 : * VPG[6] -> HPO_DP[0]
1270 : * VPG[7] -> HPO_DP[1]
1271 : * VPG[8] -> HPO_DP[2]
1272 : * VPG[9] -> HPO_DP[3]
1273 : */
1274 0 : vpg_inst = hpo_dp_inst + 6;
1275 :
1276 : /* Mapping of APG register blocks to HPO DP block instance:
1277 : * APG[0] -> HPO_DP[0]
1278 : * APG[1] -> HPO_DP[1]
1279 : * APG[2] -> HPO_DP[2]
1280 : * APG[3] -> HPO_DP[3]
1281 : */
1282 0 : apg_inst = hpo_dp_inst;
1283 :
1284 : /* allocate HPO stream encoder and create VPG sub-block */
1285 0 : hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1286 0 : vpg = dcn321_vpg_create(ctx, vpg_inst);
1287 0 : apg = dcn321_apg_create(ctx, apg_inst);
1288 :
1289 0 : if (!hpo_dp_enc31 || !vpg || !apg) {
1290 0 : kfree(hpo_dp_enc31);
1291 0 : kfree(vpg);
1292 0 : kfree(apg);
1293 0 : return NULL;
1294 : }
1295 :
1296 : #undef REG_STRUCT
1297 : #define REG_STRUCT hpo_dp_stream_enc_regs
1298 0 : hpo_dp_stream_encoder_reg_init(0),
1299 0 : hpo_dp_stream_encoder_reg_init(1),
1300 0 : hpo_dp_stream_encoder_reg_init(2),
1301 0 : hpo_dp_stream_encoder_reg_init(3);
1302 :
1303 0 : dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1304 : hpo_dp_inst, eng_id, vpg, apg,
1305 0 : &hpo_dp_stream_enc_regs[hpo_dp_inst],
1306 : &hpo_dp_se_shift, &hpo_dp_se_mask);
1307 :
1308 0 : return &hpo_dp_enc31->base;
1309 : }
1310 :
1311 0 : static struct hpo_dp_link_encoder *dcn321_hpo_dp_link_encoder_create(
1312 : uint8_t inst,
1313 : struct dc_context *ctx)
1314 : {
1315 : struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1316 :
1317 : /* allocate HPO link encoder */
1318 0 : hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1319 :
1320 : #undef REG_STRUCT
1321 : #define REG_STRUCT hpo_dp_link_enc_regs
1322 0 : hpo_dp_link_encoder_reg_init(0),
1323 0 : hpo_dp_link_encoder_reg_init(1);
1324 :
1325 0 : hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1326 0 : &hpo_dp_link_enc_regs[inst],
1327 : &hpo_dp_le_shift, &hpo_dp_le_mask);
1328 :
1329 0 : return &hpo_dp_enc31->base;
1330 : }
1331 :
1332 0 : static struct dce_hwseq *dcn321_hwseq_create(
1333 : struct dc_context *ctx)
1334 : {
1335 0 : struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1336 :
1337 : #undef REG_STRUCT
1338 : #define REG_STRUCT hwseq_reg
1339 0 : hwseq_reg_init();
1340 :
1341 0 : if (hws) {
1342 0 : hws->ctx = ctx;
1343 0 : hws->regs = &hwseq_reg;
1344 0 : hws->shifts = &hwseq_shift;
1345 0 : hws->masks = &hwseq_mask;
1346 : }
1347 0 : return hws;
1348 : }
1349 : static const struct resource_create_funcs res_create_funcs = {
1350 : .read_dce_straps = read_dce_straps,
1351 : .create_audio = dcn321_create_audio,
1352 : .create_stream_encoder = dcn321_stream_encoder_create,
1353 : .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1354 : .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1355 : .create_hwseq = dcn321_hwseq_create,
1356 : };
1357 :
1358 : static const struct resource_create_funcs res_create_maximus_funcs = {
1359 : .read_dce_straps = NULL,
1360 : .create_audio = NULL,
1361 : .create_stream_encoder = NULL,
1362 : .create_hpo_dp_stream_encoder = dcn321_hpo_dp_stream_encoder_create,
1363 : .create_hpo_dp_link_encoder = dcn321_hpo_dp_link_encoder_create,
1364 : .create_hwseq = dcn321_hwseq_create,
1365 : };
1366 :
1367 0 : static void dcn321_resource_destruct(struct dcn321_resource_pool *pool)
1368 : {
1369 : unsigned int i;
1370 :
1371 0 : for (i = 0; i < pool->base.stream_enc_count; i++) {
1372 0 : if (pool->base.stream_enc[i] != NULL) {
1373 0 : if (pool->base.stream_enc[i]->vpg != NULL) {
1374 0 : kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1375 0 : pool->base.stream_enc[i]->vpg = NULL;
1376 : }
1377 0 : if (pool->base.stream_enc[i]->afmt != NULL) {
1378 0 : kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1379 0 : pool->base.stream_enc[i]->afmt = NULL;
1380 : }
1381 0 : kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1382 0 : pool->base.stream_enc[i] = NULL;
1383 : }
1384 : }
1385 :
1386 0 : for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1387 0 : if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1388 0 : if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1389 0 : kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1390 0 : pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1391 : }
1392 0 : if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1393 0 : kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1394 0 : pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1395 : }
1396 0 : kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1397 0 : pool->base.hpo_dp_stream_enc[i] = NULL;
1398 : }
1399 : }
1400 :
1401 0 : for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1402 0 : if (pool->base.hpo_dp_link_enc[i] != NULL) {
1403 0 : kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1404 0 : pool->base.hpo_dp_link_enc[i] = NULL;
1405 : }
1406 : }
1407 :
1408 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1409 0 : if (pool->base.dscs[i] != NULL)
1410 0 : dcn20_dsc_destroy(&pool->base.dscs[i]);
1411 : }
1412 :
1413 0 : if (pool->base.mpc != NULL) {
1414 0 : kfree(TO_DCN20_MPC(pool->base.mpc));
1415 0 : pool->base.mpc = NULL;
1416 : }
1417 0 : if (pool->base.hubbub != NULL) {
1418 0 : kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1419 0 : pool->base.hubbub = NULL;
1420 : }
1421 0 : for (i = 0; i < pool->base.pipe_count; i++) {
1422 0 : if (pool->base.dpps[i] != NULL)
1423 0 : dcn321_dpp_destroy(&pool->base.dpps[i]);
1424 :
1425 0 : if (pool->base.ipps[i] != NULL)
1426 0 : pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1427 :
1428 0 : if (pool->base.hubps[i] != NULL) {
1429 0 : kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1430 0 : pool->base.hubps[i] = NULL;
1431 : }
1432 :
1433 0 : if (pool->base.irqs != NULL)
1434 0 : dal_irq_service_destroy(&pool->base.irqs);
1435 : }
1436 :
1437 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1438 0 : if (pool->base.engines[i] != NULL)
1439 0 : dce110_engine_destroy(&pool->base.engines[i]);
1440 0 : if (pool->base.hw_i2cs[i] != NULL) {
1441 0 : kfree(pool->base.hw_i2cs[i]);
1442 0 : pool->base.hw_i2cs[i] = NULL;
1443 : }
1444 0 : if (pool->base.sw_i2cs[i] != NULL) {
1445 0 : kfree(pool->base.sw_i2cs[i]);
1446 0 : pool->base.sw_i2cs[i] = NULL;
1447 : }
1448 : }
1449 :
1450 0 : for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1451 0 : if (pool->base.opps[i] != NULL)
1452 0 : pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1453 : }
1454 :
1455 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1456 0 : if (pool->base.timing_generators[i] != NULL) {
1457 0 : kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1458 0 : pool->base.timing_generators[i] = NULL;
1459 : }
1460 : }
1461 :
1462 0 : for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1463 0 : if (pool->base.dwbc[i] != NULL) {
1464 0 : kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1465 0 : pool->base.dwbc[i] = NULL;
1466 : }
1467 0 : if (pool->base.mcif_wb[i] != NULL) {
1468 0 : kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1469 0 : pool->base.mcif_wb[i] = NULL;
1470 : }
1471 : }
1472 :
1473 0 : for (i = 0; i < pool->base.audio_count; i++) {
1474 0 : if (pool->base.audios[i])
1475 0 : dce_aud_destroy(&pool->base.audios[i]);
1476 : }
1477 :
1478 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1479 0 : if (pool->base.clock_sources[i] != NULL) {
1480 0 : dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1481 0 : pool->base.clock_sources[i] = NULL;
1482 : }
1483 : }
1484 :
1485 0 : for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1486 0 : if (pool->base.mpc_lut[i] != NULL) {
1487 0 : dc_3dlut_func_release(pool->base.mpc_lut[i]);
1488 0 : pool->base.mpc_lut[i] = NULL;
1489 : }
1490 0 : if (pool->base.mpc_shaper[i] != NULL) {
1491 0 : dc_transfer_func_release(pool->base.mpc_shaper[i]);
1492 0 : pool->base.mpc_shaper[i] = NULL;
1493 : }
1494 : }
1495 :
1496 0 : if (pool->base.dp_clock_source != NULL) {
1497 0 : dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1498 0 : pool->base.dp_clock_source = NULL;
1499 : }
1500 :
1501 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1502 0 : if (pool->base.multiple_abms[i] != NULL)
1503 0 : dce_abm_destroy(&pool->base.multiple_abms[i]);
1504 : }
1505 :
1506 0 : if (pool->base.psr != NULL)
1507 0 : dmub_psr_destroy(&pool->base.psr);
1508 :
1509 0 : if (pool->base.dccg != NULL)
1510 0 : dcn_dccg_destroy(&pool->base.dccg);
1511 :
1512 0 : if (pool->base.oem_device != NULL)
1513 0 : dal_ddc_service_destroy(&pool->base.oem_device);
1514 0 : }
1515 :
1516 :
1517 0 : static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1518 : {
1519 : int i;
1520 0 : uint32_t dwb_count = pool->res_cap->num_dwb;
1521 :
1522 0 : for (i = 0; i < dwb_count; i++) {
1523 0 : struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1524 : GFP_KERNEL);
1525 :
1526 0 : if (!dwbc30) {
1527 0 : dm_error("DC: failed to create dwbc30!\n");
1528 : return false;
1529 : }
1530 :
1531 : #undef REG_STRUCT
1532 : #define REG_STRUCT dwbc30_regs
1533 0 : dwbc_regs_dcn3_init(0);
1534 :
1535 0 : dcn30_dwbc_construct(dwbc30, ctx,
1536 0 : &dwbc30_regs[i],
1537 : &dwbc30_shift,
1538 : &dwbc30_mask,
1539 : i);
1540 :
1541 0 : pool->dwbc[i] = &dwbc30->base;
1542 : }
1543 : return true;
1544 : }
1545 :
1546 0 : static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1547 : {
1548 : int i;
1549 0 : uint32_t dwb_count = pool->res_cap->num_dwb;
1550 :
1551 0 : for (i = 0; i < dwb_count; i++) {
1552 0 : struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1553 : GFP_KERNEL);
1554 :
1555 0 : if (!mcif_wb30) {
1556 0 : dm_error("DC: failed to create mcif_wb30!\n");
1557 : return false;
1558 : }
1559 :
1560 : #undef REG_STRUCT
1561 : #define REG_STRUCT mcif_wb30_regs
1562 0 : mcif_wb_regs_dcn3_init(0);
1563 :
1564 0 : dcn32_mmhubbub_construct(mcif_wb30, ctx,
1565 0 : &mcif_wb30_regs[i],
1566 : &mcif_wb30_shift,
1567 : &mcif_wb30_mask,
1568 : i);
1569 :
1570 0 : pool->mcif_wb[i] = &mcif_wb30->base;
1571 : }
1572 : return true;
1573 : }
1574 :
1575 0 : static struct display_stream_compressor *dcn321_dsc_create(
1576 : struct dc_context *ctx, uint32_t inst)
1577 : {
1578 0 : struct dcn20_dsc *dsc =
1579 : kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1580 :
1581 0 : if (!dsc) {
1582 0 : BREAK_TO_DEBUGGER();
1583 0 : return NULL;
1584 : }
1585 :
1586 : #undef REG_STRUCT
1587 : #define REG_STRUCT dsc_regs
1588 0 : dsc_regsDCN20_init(0),
1589 0 : dsc_regsDCN20_init(1),
1590 0 : dsc_regsDCN20_init(2),
1591 0 : dsc_regsDCN20_init(3);
1592 :
1593 0 : dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1594 :
1595 0 : dsc->max_image_width = 6016;
1596 :
1597 0 : return &dsc->base;
1598 : }
1599 :
1600 0 : static void dcn321_destroy_resource_pool(struct resource_pool **pool)
1601 : {
1602 0 : struct dcn321_resource_pool *dcn321_pool = TO_DCN321_RES_POOL(*pool);
1603 :
1604 0 : dcn321_resource_destruct(dcn321_pool);
1605 0 : kfree(dcn321_pool);
1606 0 : *pool = NULL;
1607 0 : }
1608 :
1609 : static struct dc_cap_funcs cap_funcs = {
1610 : .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1611 : };
1612 :
1613 0 : static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1614 : {
1615 0 : DC_FP_START();
1616 0 : dcn321_update_bw_bounding_box_fpu(dc, bw_params);
1617 0 : DC_FP_END();
1618 0 : }
1619 :
1620 : static struct resource_funcs dcn321_res_pool_funcs = {
1621 : .destroy = dcn321_destroy_resource_pool,
1622 : .link_enc_create = dcn321_link_encoder_create,
1623 : .link_enc_create_minimal = NULL,
1624 : .panel_cntl_create = dcn32_panel_cntl_create,
1625 : .validate_bandwidth = dcn32_validate_bandwidth,
1626 : .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1627 : .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1628 : .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1629 : .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1630 : .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1631 : .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1632 : .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1633 : .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1634 : .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1635 : .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1636 : .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1637 : .update_bw_bounding_box = dcn321_update_bw_bounding_box,
1638 : .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1639 : .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1640 : .add_phantom_pipes = dcn32_add_phantom_pipes,
1641 : .remove_phantom_pipes = dcn32_remove_phantom_pipes,
1642 : };
1643 :
1644 :
1645 0 : static bool dcn321_resource_construct(
1646 : uint8_t num_virtual_links,
1647 : struct dc *dc,
1648 : struct dcn321_resource_pool *pool)
1649 : {
1650 : int i, j;
1651 0 : struct dc_context *ctx = dc->ctx;
1652 : struct irq_service_init_data init_data;
1653 0 : struct ddc_service_init_data ddc_init_data = {0};
1654 0 : uint32_t pipe_fuses = 0;
1655 0 : uint32_t num_pipes = 4;
1656 :
1657 : #undef REG_STRUCT
1658 : #define REG_STRUCT bios_regs
1659 0 : bios_regs_init();
1660 :
1661 : #undef REG_STRUCT
1662 : #define REG_STRUCT clk_src_regs
1663 0 : clk_src_regs_init(0, A),
1664 0 : clk_src_regs_init(1, B),
1665 0 : clk_src_regs_init(2, C),
1666 0 : clk_src_regs_init(3, D),
1667 0 : clk_src_regs_init(4, E);
1668 :
1669 : #undef REG_STRUCT
1670 : #define REG_STRUCT abm_regs
1671 0 : abm_regs_init(0),
1672 0 : abm_regs_init(1),
1673 0 : abm_regs_init(2),
1674 0 : abm_regs_init(3);
1675 :
1676 : #undef REG_STRUCT
1677 : #define REG_STRUCT dccg_regs
1678 0 : dccg_regs_init();
1679 :
1680 :
1681 0 : ctx->dc_bios->regs = &bios_regs;
1682 :
1683 0 : pool->base.res_cap = &res_cap_dcn321;
1684 : /* max number of pipes for ASIC before checking for pipe fuses */
1685 0 : num_pipes = pool->base.res_cap->num_timing_generator;
1686 0 : pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
1687 :
1688 0 : for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1689 0 : if (pipe_fuses & 1 << i)
1690 0 : num_pipes--;
1691 :
1692 0 : if (pipe_fuses & 1)
1693 0 : ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1694 :
1695 0 : if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1696 0 : ASSERT(0); //Entire DCN is harvested!
1697 :
1698 : /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
1699 : * value will be changed, update max_num_dpp and max_num_otg for dml.
1700 : */
1701 0 : dcn3_21_ip.max_num_dpp = num_pipes;
1702 0 : dcn3_21_ip.max_num_otg = num_pipes;
1703 :
1704 0 : pool->base.funcs = &dcn321_res_pool_funcs;
1705 :
1706 : /*************************************************
1707 : * Resource + asic cap harcoding *
1708 : *************************************************/
1709 0 : pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1710 0 : pool->base.timing_generator_count = num_pipes;
1711 0 : pool->base.pipe_count = num_pipes;
1712 0 : pool->base.mpcc_count = num_pipes;
1713 0 : dc->caps.max_downscale_ratio = 600;
1714 0 : dc->caps.i2c_speed_in_khz = 100;
1715 0 : dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
1716 0 : dc->caps.max_cursor_size = 256;
1717 0 : dc->caps.min_horizontal_blanking_period = 80;
1718 0 : dc->caps.dmdata_alloc_size = 2048;
1719 0 : dc->caps.mall_size_per_mem_channel = 0;
1720 0 : dc->caps.mall_size_total = 0;
1721 0 : dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1722 0 : dc->caps.cache_line_size = 64;
1723 0 : dc->caps.cache_num_ways = 16;
1724 0 : dc->caps.max_cab_allocation_bytes = 33554432; // 32MB = 1024 * 1024 * 32
1725 0 : dc->caps.subvp_fw_processing_delay_us = 15;
1726 0 : dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1727 0 : dc->caps.subvp_swath_height_margin_lines = 16;
1728 0 : dc->caps.subvp_pstate_allow_width_us = 20;
1729 0 : dc->caps.subvp_vertical_int_margin_us = 30;
1730 0 : dc->caps.max_slave_planes = 1;
1731 0 : dc->caps.max_slave_yuv_planes = 1;
1732 0 : dc->caps.max_slave_rgb_planes = 1;
1733 0 : dc->caps.post_blend_color_processing = true;
1734 0 : dc->caps.force_dp_tps4_for_cp2520 = true;
1735 0 : dc->caps.dp_hpo = true;
1736 0 : dc->caps.dp_hdmi21_pcon_support = true;
1737 0 : dc->caps.edp_dsc_support = true;
1738 0 : dc->caps.extended_aux_timeout_support = true;
1739 0 : dc->caps.dmcub_support = true;
1740 :
1741 : /* Color pipeline capabilities */
1742 0 : dc->caps.color.dpp.dcn_arch = 1;
1743 0 : dc->caps.color.dpp.input_lut_shared = 0;
1744 0 : dc->caps.color.dpp.icsc = 1;
1745 0 : dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1746 0 : dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1747 0 : dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1748 0 : dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1749 0 : dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1750 0 : dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1751 0 : dc->caps.color.dpp.post_csc = 1;
1752 0 : dc->caps.color.dpp.gamma_corr = 1;
1753 0 : dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1754 :
1755 0 : dc->caps.color.dpp.hw_3d_lut = 1;
1756 0 : dc->caps.color.dpp.ogam_ram = 1;
1757 : // no OGAM ROM on DCN2 and later ASICs
1758 0 : dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1759 0 : dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1760 0 : dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1761 0 : dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1762 0 : dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1763 0 : dc->caps.color.dpp.ocsc = 0;
1764 :
1765 0 : dc->caps.color.mpc.gamut_remap = 1;
1766 0 : dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1767 0 : dc->caps.color.mpc.ogam_ram = 1;
1768 0 : dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1769 0 : dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1770 0 : dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1771 0 : dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1772 0 : dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1773 0 : dc->caps.color.mpc.ocsc = 1;
1774 :
1775 : /* read VBIOS LTTPR caps */
1776 : {
1777 0 : if (ctx->dc_bios->funcs->get_lttpr_caps) {
1778 : enum bp_result bp_query_result;
1779 0 : uint8_t is_vbios_lttpr_enable = 0;
1780 :
1781 0 : bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1782 0 : dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1783 : }
1784 :
1785 : /* interop bit is implicit */
1786 : {
1787 0 : dc->caps.vbios_lttpr_aware = true;
1788 : }
1789 : }
1790 :
1791 0 : if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1792 0 : dc->debug = debug_defaults_drv;
1793 0 : else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1794 0 : dc->debug = debug_defaults_diags;
1795 : } else
1796 0 : dc->debug = debug_defaults_diags;
1797 : // Init the vm_helper
1798 0 : if (dc->vm_helper)
1799 0 : vm_helper_init(dc->vm_helper, 16);
1800 :
1801 : /*************************************************
1802 : * Create resources *
1803 : *************************************************/
1804 :
1805 : /* Clock Sources for Pixel Clock*/
1806 0 : pool->base.clock_sources[DCN321_CLK_SRC_PLL0] =
1807 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1808 : CLOCK_SOURCE_COMBO_PHY_PLL0,
1809 : &clk_src_regs[0], false);
1810 0 : pool->base.clock_sources[DCN321_CLK_SRC_PLL1] =
1811 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1812 : CLOCK_SOURCE_COMBO_PHY_PLL1,
1813 : &clk_src_regs[1], false);
1814 0 : pool->base.clock_sources[DCN321_CLK_SRC_PLL2] =
1815 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1816 : CLOCK_SOURCE_COMBO_PHY_PLL2,
1817 : &clk_src_regs[2], false);
1818 0 : pool->base.clock_sources[DCN321_CLK_SRC_PLL3] =
1819 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1820 : CLOCK_SOURCE_COMBO_PHY_PLL3,
1821 : &clk_src_regs[3], false);
1822 0 : pool->base.clock_sources[DCN321_CLK_SRC_PLL4] =
1823 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1824 : CLOCK_SOURCE_COMBO_PHY_PLL4,
1825 : &clk_src_regs[4], false);
1826 :
1827 0 : pool->base.clk_src_count = DCN321_CLK_SRC_TOTAL;
1828 :
1829 : /* todo: not reuse phy_pll registers */
1830 0 : pool->base.dp_clock_source =
1831 0 : dcn321_clock_source_create(ctx, ctx->dc_bios,
1832 : CLOCK_SOURCE_ID_DP_DTO,
1833 : &clk_src_regs[0], true);
1834 :
1835 0 : for (i = 0; i < pool->base.clk_src_count; i++) {
1836 0 : if (pool->base.clock_sources[i] == NULL) {
1837 0 : dm_error("DC: failed to create clock sources!\n");
1838 0 : BREAK_TO_DEBUGGER();
1839 0 : goto create_fail;
1840 : }
1841 : }
1842 :
1843 : /* DCCG */
1844 0 : pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1845 0 : if (pool->base.dccg == NULL) {
1846 0 : dm_error("DC: failed to create dccg!\n");
1847 0 : BREAK_TO_DEBUGGER();
1848 0 : goto create_fail;
1849 : }
1850 :
1851 : /* DML */
1852 0 : if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1853 0 : dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
1854 :
1855 : /* IRQ Service */
1856 0 : init_data.ctx = dc->ctx;
1857 0 : pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
1858 0 : if (!pool->base.irqs)
1859 : goto create_fail;
1860 :
1861 : /* HUBBUB */
1862 0 : pool->base.hubbub = dcn321_hubbub_create(ctx);
1863 0 : if (pool->base.hubbub == NULL) {
1864 0 : BREAK_TO_DEBUGGER();
1865 0 : dm_error("DC: failed to create hubbub!\n");
1866 0 : goto create_fail;
1867 : }
1868 :
1869 : /* HUBPs, DPPs, OPPs, TGs, ABMs */
1870 0 : for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1871 :
1872 : /* if pipe is disabled, skip instance of HW pipe,
1873 : * i.e, skip ASIC register instance
1874 : */
1875 0 : if (pipe_fuses & 1 << i)
1876 0 : continue;
1877 :
1878 0 : pool->base.hubps[j] = dcn321_hubp_create(ctx, i);
1879 0 : if (pool->base.hubps[j] == NULL) {
1880 0 : BREAK_TO_DEBUGGER();
1881 0 : dm_error(
1882 : "DC: failed to create hubps!\n");
1883 0 : goto create_fail;
1884 : }
1885 :
1886 0 : pool->base.dpps[j] = dcn321_dpp_create(ctx, i);
1887 0 : if (pool->base.dpps[j] == NULL) {
1888 0 : BREAK_TO_DEBUGGER();
1889 0 : dm_error(
1890 : "DC: failed to create dpps!\n");
1891 0 : goto create_fail;
1892 : }
1893 :
1894 0 : pool->base.opps[j] = dcn321_opp_create(ctx, i);
1895 0 : if (pool->base.opps[j] == NULL) {
1896 0 : BREAK_TO_DEBUGGER();
1897 0 : dm_error(
1898 : "DC: failed to create output pixel processor!\n");
1899 0 : goto create_fail;
1900 : }
1901 :
1902 0 : pool->base.timing_generators[j] = dcn321_timing_generator_create(
1903 : ctx, i);
1904 0 : if (pool->base.timing_generators[j] == NULL) {
1905 0 : BREAK_TO_DEBUGGER();
1906 0 : dm_error("DC: failed to create tg!\n");
1907 0 : goto create_fail;
1908 : }
1909 :
1910 0 : pool->base.multiple_abms[j] = dmub_abm_create(ctx,
1911 0 : &abm_regs[i],
1912 : &abm_shift,
1913 : &abm_mask);
1914 0 : if (pool->base.multiple_abms[j] == NULL) {
1915 0 : dm_error("DC: failed to create abm for pipe %d!\n", i);
1916 0 : BREAK_TO_DEBUGGER();
1917 0 : goto create_fail;
1918 : }
1919 :
1920 : /* index for resource pool arrays for next valid pipe */
1921 0 : j++;
1922 : }
1923 :
1924 : /* PSR */
1925 0 : pool->base.psr = dmub_psr_create(ctx);
1926 0 : if (pool->base.psr == NULL) {
1927 0 : dm_error("DC: failed to create psr obj!\n");
1928 0 : BREAK_TO_DEBUGGER();
1929 0 : goto create_fail;
1930 : }
1931 :
1932 : /* MPCCs */
1933 0 : pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
1934 0 : if (pool->base.mpc == NULL) {
1935 0 : BREAK_TO_DEBUGGER();
1936 0 : dm_error("DC: failed to create mpc!\n");
1937 0 : goto create_fail;
1938 : }
1939 :
1940 : /* DSCs */
1941 0 : for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1942 0 : pool->base.dscs[i] = dcn321_dsc_create(ctx, i);
1943 0 : if (pool->base.dscs[i] == NULL) {
1944 0 : BREAK_TO_DEBUGGER();
1945 0 : dm_error("DC: failed to create display stream compressor %d!\n", i);
1946 0 : goto create_fail;
1947 : }
1948 : }
1949 :
1950 : /* DWB */
1951 0 : if (!dcn321_dwbc_create(ctx, &pool->base)) {
1952 0 : BREAK_TO_DEBUGGER();
1953 0 : dm_error("DC: failed to create dwbc!\n");
1954 0 : goto create_fail;
1955 : }
1956 :
1957 : /* MMHUBBUB */
1958 0 : if (!dcn321_mmhubbub_create(ctx, &pool->base)) {
1959 0 : BREAK_TO_DEBUGGER();
1960 0 : dm_error("DC: failed to create mcif_wb!\n");
1961 0 : goto create_fail;
1962 : }
1963 :
1964 : /* AUX and I2C */
1965 0 : for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1966 0 : pool->base.engines[i] = dcn321_aux_engine_create(ctx, i);
1967 0 : if (pool->base.engines[i] == NULL) {
1968 0 : BREAK_TO_DEBUGGER();
1969 0 : dm_error(
1970 : "DC:failed to create aux engine!!\n");
1971 0 : goto create_fail;
1972 : }
1973 0 : pool->base.hw_i2cs[i] = dcn321_i2c_hw_create(ctx, i);
1974 0 : if (pool->base.hw_i2cs[i] == NULL) {
1975 0 : BREAK_TO_DEBUGGER();
1976 0 : dm_error(
1977 : "DC:failed to create hw i2c!!\n");
1978 0 : goto create_fail;
1979 : }
1980 0 : pool->base.sw_i2cs[i] = NULL;
1981 : }
1982 :
1983 : /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1984 0 : if (!resource_construct(num_virtual_links, dc, &pool->base,
1985 0 : (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1986 : &res_create_funcs : &res_create_maximus_funcs)))
1987 : goto create_fail;
1988 :
1989 : /* HW Sequencer init functions and Plane caps */
1990 0 : dcn32_hw_sequencer_init_functions(dc);
1991 :
1992 0 : dc->caps.max_planes = pool->base.pipe_count;
1993 :
1994 0 : for (i = 0; i < dc->caps.max_planes; ++i)
1995 0 : dc->caps.planes[i] = plane_cap;
1996 :
1997 0 : dc->cap_funcs = cap_funcs;
1998 :
1999 0 : if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2000 0 : ddc_init_data.ctx = dc->ctx;
2001 0 : ddc_init_data.link = NULL;
2002 0 : ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2003 0 : ddc_init_data.id.enum_id = 0;
2004 0 : ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2005 0 : pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2006 : } else {
2007 0 : pool->base.oem_device = NULL;
2008 : }
2009 :
2010 : return true;
2011 :
2012 : create_fail:
2013 :
2014 0 : dcn321_resource_destruct(pool);
2015 :
2016 0 : return false;
2017 : }
2018 :
2019 0 : struct resource_pool *dcn321_create_resource_pool(
2020 : const struct dc_init_data *init_data,
2021 : struct dc *dc)
2022 : {
2023 0 : struct dcn321_resource_pool *pool =
2024 : kzalloc(sizeof(struct dcn321_resource_pool), GFP_KERNEL);
2025 :
2026 0 : if (!pool)
2027 : return NULL;
2028 :
2029 0 : if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
2030 0 : return &pool->base;
2031 :
2032 0 : BREAK_TO_DEBUGGER();
2033 0 : kfree(pool);
2034 0 : return NULL;
2035 : }
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