Line data Source code
1 : /*
2 : * Copyright 2015 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : /**
27 : * This file defines external dependencies of Display Core.
28 : */
29 :
30 : #ifndef __DM_SERVICES_H__
31 :
32 : #define __DM_SERVICES_H__
33 :
34 : /* TODO: remove when DC is complete. */
35 : #include "dm_services_types.h"
36 : #include "logger_interface.h"
37 : #include "link_service_types.h"
38 :
39 : #undef DEPRECATED
40 :
41 : struct dmub_srv;
42 : struct dc_dmub_srv;
43 :
44 : irq_handler_idx dm_register_interrupt(
45 : struct dc_context *ctx,
46 : struct dc_interrupt_params *int_params,
47 : interrupt_handler ih,
48 : void *handler_args);
49 :
50 : /*
51 : *
52 : * GPU registers access
53 : *
54 : */
55 : uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
56 : const char *func_name);
57 :
58 : /* enable for debugging new code, this adds 50k to the driver size. */
59 : /* #define DM_CHECK_ADDR_0 */
60 :
61 : void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
62 : uint32_t value, const char *func_name);
63 :
64 : #define dm_read_reg(ctx, address) \
65 : dm_read_reg_func(ctx, address, __func__)
66 :
67 : #define dm_write_reg(ctx, address, value) \
68 : dm_write_reg_func(ctx, address, value, __func__)
69 :
70 : static inline uint32_t dm_read_index_reg(
71 : const struct dc_context *ctx,
72 : enum cgs_ind_reg addr_space,
73 : uint32_t index)
74 : {
75 0 : return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
76 : }
77 :
78 : static inline void dm_write_index_reg(
79 : const struct dc_context *ctx,
80 : enum cgs_ind_reg addr_space,
81 : uint32_t index,
82 : uint32_t value)
83 : {
84 0 : cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
85 : }
86 :
87 : static inline uint32_t get_reg_field_value_ex(
88 : uint32_t reg_value,
89 : uint32_t mask,
90 : uint8_t shift)
91 : {
92 0 : return (mask & reg_value) >> shift;
93 : }
94 :
95 : #define get_reg_field_value(reg_value, reg_name, reg_field)\
96 : get_reg_field_value_ex(\
97 : (reg_value),\
98 : reg_name ## __ ## reg_field ## _MASK,\
99 : reg_name ## __ ## reg_field ## __SHIFT)
100 :
101 0 : static inline uint32_t set_reg_field_value_ex(
102 : uint32_t reg_value,
103 : uint32_t value,
104 : uint32_t mask,
105 : uint8_t shift)
106 : {
107 0 : ASSERT(mask != 0);
108 0 : return (reg_value & ~mask) | (mask & (value << shift));
109 : }
110 :
111 : #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
112 : (reg_value) = set_reg_field_value_ex(\
113 : (reg_value),\
114 : (value),\
115 : reg_name ## __ ## reg_field ## _MASK,\
116 : reg_name ## __ ## reg_field ## __SHIFT)
117 :
118 : uint32_t generic_reg_set_ex(const struct dc_context *ctx,
119 : uint32_t addr, uint32_t reg_val, int n,
120 : uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
121 :
122 : uint32_t generic_reg_update_ex(const struct dc_context *ctx,
123 : uint32_t addr, int n,
124 : uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
125 :
126 : struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
127 : void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
128 :
129 : void reg_sequence_start_gather(const struct dc_context *ctx);
130 : void reg_sequence_start_execute(const struct dc_context *ctx);
131 : void reg_sequence_wait_done(const struct dc_context *ctx);
132 :
133 : #define FD(reg_field) reg_field ## __SHIFT, \
134 : reg_field ## _MASK
135 :
136 : /*
137 : * return number of poll before condition is met
138 : * return 0 if condition is not meet after specified time out tries
139 : */
140 : void generic_reg_wait(const struct dc_context *ctx,
141 : uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
142 : unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
143 : const char *func_name, int line);
144 :
145 : unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
146 :
147 : /* These macros need to be used with soc15 registers in order to retrieve
148 : * the actual offset.
149 : */
150 : #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
151 : dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
152 :
153 : #define dm_read_reg_soc15(ctx, reg, inst_offset) \
154 : dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
155 :
156 : #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
157 : generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
158 : n, __VA_ARGS__)
159 :
160 : #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
161 : generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
162 : n, __VA_ARGS__)
163 :
164 : #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
165 : get_reg_field_value_ex(\
166 : (reg_value),\
167 : block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
168 : block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
169 :
170 : #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
171 : (reg_value) = set_reg_field_value_ex(\
172 : (reg_value),\
173 : (value),\
174 : block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
175 : block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
176 :
177 : /**************************************
178 : * Power Play (PP) interfaces
179 : **************************************/
180 :
181 : /* Gets valid clocks levels from pplib
182 : *
183 : * input: clk_type - display clk / sclk / mem clk
184 : *
185 : * output: array of valid clock levels for given type in ascending order,
186 : * with invalid levels filtered out
187 : *
188 : */
189 : bool dm_pp_get_clock_levels_by_type(
190 : const struct dc_context *ctx,
191 : enum dm_pp_clock_type clk_type,
192 : struct dm_pp_clock_levels *clk_level_info);
193 :
194 : bool dm_pp_get_clock_levels_by_type_with_latency(
195 : const struct dc_context *ctx,
196 : enum dm_pp_clock_type clk_type,
197 : struct dm_pp_clock_levels_with_latency *clk_level_info);
198 :
199 : bool dm_pp_get_clock_levels_by_type_with_voltage(
200 : const struct dc_context *ctx,
201 : enum dm_pp_clock_type clk_type,
202 : struct dm_pp_clock_levels_with_voltage *clk_level_info);
203 :
204 : bool dm_pp_notify_wm_clock_changes(
205 : const struct dc_context *ctx,
206 : struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
207 :
208 : void dm_pp_get_funcs(struct dc_context *ctx,
209 : struct pp_smu_funcs *funcs);
210 :
211 : /* DAL calls this function to notify PP about completion of Mode Set.
212 : * For PP it means that current DCE clocks are those which were returned
213 : * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
214 : *
215 : * If the clocks are higher than before, then PP does nothing.
216 : *
217 : * If the clocks are lower than before, then PP reduces the voltage.
218 : *
219 : * \returns true - call is successful
220 : * false - call failed
221 : */
222 : bool dm_pp_apply_display_requirements(
223 : const struct dc_context *ctx,
224 : const struct dm_pp_display_configuration *pp_display_cfg);
225 :
226 : bool dm_pp_apply_power_level_change_request(
227 : const struct dc_context *ctx,
228 : struct dm_pp_power_level_change_request *level_change_req);
229 :
230 : bool dm_pp_apply_clock_for_voltage_request(
231 : const struct dc_context *ctx,
232 : struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
233 :
234 : bool dm_pp_get_static_clocks(
235 : const struct dc_context *ctx,
236 : struct dm_pp_static_clock_info *static_clk_info);
237 :
238 : /****** end of PP interfaces ******/
239 :
240 : struct persistent_data_flag {
241 : bool save_per_link;
242 : bool save_per_edid;
243 : };
244 :
245 : bool dm_query_extended_brightness_caps
246 : (struct dc_context *ctx, enum dm_acpi_display_type display,
247 : struct dm_acpi_atif_backlight_caps *pCaps);
248 :
249 : bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
250 :
251 : /*
252 : *
253 : * print-out services
254 : *
255 : */
256 : #define dm_log_to_buffer(buffer, size, fmt, args)\
257 : vsnprintf(buffer, size, fmt, args)
258 :
259 : static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
260 : {
261 : return ktime_get_raw_ns();
262 : }
263 :
264 : unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
265 : unsigned long long current_time_stamp,
266 : unsigned long long last_time_stamp);
267 :
268 : /*
269 : * performance tracing
270 : */
271 : void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
272 :
273 : #define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__, CTX)
274 : #define PERF_TRACE_CTX(__CTX) dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
275 :
276 : /*
277 : * Debug and verification hooks
278 : */
279 :
280 : void dm_dtn_log_begin(struct dc_context *ctx,
281 : struct dc_log_buffer_ctx *log_ctx);
282 : void dm_dtn_log_append_v(struct dc_context *ctx,
283 : struct dc_log_buffer_ctx *log_ctx,
284 : const char *msg, ...);
285 : void dm_dtn_log_end(struct dc_context *ctx,
286 : struct dc_log_buffer_ctx *log_ctx);
287 :
288 : #endif /* __DM_SERVICES_H__ */
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