Line data Source code
1 : /*
2 : * Copyright 2015 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: AMD
23 : *
24 : */
25 :
26 : #include <linux/slab.h>
27 :
28 : #include "resource.h"
29 : #include "dm_services.h"
30 : #include "dce_calcs.h"
31 : #include "dc.h"
32 : #include "core_types.h"
33 : #include "dal_asic_id.h"
34 : #include "calcs_logger.h"
35 :
36 : /*
37 : * NOTE:
38 : * This file is gcc-parseable HW gospel, coming straight from HW engineers.
39 : *
40 : * It doesn't adhere to Linux kernel style and sometimes will do things in odd
41 : * ways. Unless there is something clearly wrong with it the code should
42 : * remain as-is as it provides us with a guarantee from HW that it is correct.
43 : */
44 :
45 : /*******************************************************************************
46 : * Private Functions
47 : ******************************************************************************/
48 :
49 0 : static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
50 : {
51 0 : switch (asic_id.chip_family) {
52 :
53 : case FAMILY_CZ:
54 0 : if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
55 : return BW_CALCS_VERSION_STONEY;
56 : return BW_CALCS_VERSION_CARRIZO;
57 :
58 : case FAMILY_VI:
59 0 : if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
60 : return BW_CALCS_VERSION_POLARIS12;
61 0 : if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
62 : return BW_CALCS_VERSION_POLARIS10;
63 0 : if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
64 : return BW_CALCS_VERSION_POLARIS11;
65 0 : if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
66 : return BW_CALCS_VERSION_VEGAM;
67 : return BW_CALCS_VERSION_INVALID;
68 :
69 : case FAMILY_AI:
70 : return BW_CALCS_VERSION_VEGA10;
71 :
72 : default:
73 : return BW_CALCS_VERSION_INVALID;
74 : }
75 : }
76 :
77 0 : static void calculate_bandwidth(
78 : const struct bw_calcs_dceip *dceip,
79 : const struct bw_calcs_vbios *vbios,
80 : struct bw_calcs_data *data)
81 :
82 : {
83 0 : const int32_t pixels_per_chunk = 512;
84 0 : const int32_t high = 2;
85 0 : const int32_t mid = 1;
86 0 : const int32_t low = 0;
87 0 : const uint32_t s_low = 0;
88 0 : const uint32_t s_mid1 = 1;
89 0 : const uint32_t s_mid2 = 2;
90 0 : const uint32_t s_mid3 = 3;
91 0 : const uint32_t s_mid4 = 4;
92 0 : const uint32_t s_mid5 = 5;
93 0 : const uint32_t s_mid6 = 6;
94 0 : const uint32_t s_high = 7;
95 0 : const uint32_t dmif_chunk_buff_margin = 1;
96 :
97 : uint32_t max_chunks_fbc_mode;
98 : int32_t num_cursor_lines;
99 :
100 : int32_t i, j, k;
101 : struct bw_fixed *yclk;
102 : struct bw_fixed *sclk;
103 : bool d0_underlay_enable;
104 : bool d1_underlay_enable;
105 : bool fbc_enabled;
106 : bool lpt_enabled;
107 : enum bw_defines sclk_message;
108 : enum bw_defines yclk_message;
109 : enum bw_defines *tiling_mode;
110 : enum bw_defines *surface_type;
111 : enum bw_defines voltage;
112 : enum bw_defines pipe_check;
113 : enum bw_defines hsr_check;
114 : enum bw_defines vsr_check;
115 : enum bw_defines lb_size_check;
116 : enum bw_defines fbc_check;
117 : enum bw_defines rotation_check;
118 : enum bw_defines mode_check;
119 : enum bw_defines nbp_state_change_enable_blank;
120 : /*initialize variables*/
121 0 : int32_t number_of_displays_enabled = 0;
122 0 : int32_t number_of_displays_enabled_with_margin = 0;
123 0 : int32_t number_of_aligned_displays_with_no_margin = 0;
124 :
125 0 : yclk = kcalloc(3, sizeof(*yclk), GFP_KERNEL);
126 0 : if (!yclk)
127 : return;
128 :
129 0 : sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
130 0 : if (!sclk)
131 : goto free_yclk;
132 :
133 0 : tiling_mode = kcalloc(maximum_number_of_surfaces, sizeof(*tiling_mode), GFP_KERNEL);
134 0 : if (!tiling_mode)
135 : goto free_sclk;
136 :
137 0 : surface_type = kcalloc(maximum_number_of_surfaces, sizeof(*surface_type), GFP_KERNEL);
138 0 : if (!surface_type)
139 : goto free_tiling_mode;
140 :
141 0 : yclk[low] = vbios->low_yclk;
142 0 : yclk[mid] = vbios->mid_yclk;
143 0 : yclk[high] = vbios->high_yclk;
144 0 : sclk[s_low] = vbios->low_sclk;
145 0 : sclk[s_mid1] = vbios->mid1_sclk;
146 0 : sclk[s_mid2] = vbios->mid2_sclk;
147 0 : sclk[s_mid3] = vbios->mid3_sclk;
148 0 : sclk[s_mid4] = vbios->mid4_sclk;
149 0 : sclk[s_mid5] = vbios->mid5_sclk;
150 0 : sclk[s_mid6] = vbios->mid6_sclk;
151 0 : sclk[s_high] = vbios->high_sclk;
152 : /*''''''''''''''''''*/
153 : /* surface assignment:*/
154 : /* 0: d0 underlay or underlay luma*/
155 : /* 1: d0 underlay chroma*/
156 : /* 2: d1 underlay or underlay luma*/
157 : /* 3: d1 underlay chroma*/
158 : /* 4: d0 graphics*/
159 : /* 5: d1 graphics*/
160 : /* 6: d2 graphics*/
161 : /* 7: d3 graphics, same mode as d2*/
162 : /* 8: d4 graphics, same mode as d2*/
163 : /* 9: d5 graphics, same mode as d2*/
164 : /* ...*/
165 : /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
166 : /* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
167 : /* underlay luma and chroma surface parameters from spreadsheet*/
168 :
169 :
170 :
171 :
172 0 : if (data->d0_underlay_mode == bw_def_none)
173 : d0_underlay_enable = false;
174 : else
175 0 : d0_underlay_enable = true;
176 0 : if (data->d1_underlay_mode == bw_def_none)
177 : d1_underlay_enable = false;
178 : else
179 0 : d1_underlay_enable = true;
180 0 : data->number_of_underlay_surfaces = d0_underlay_enable + d1_underlay_enable;
181 0 : switch (data->underlay_surface_type) {
182 : case bw_def_420:
183 0 : surface_type[0] = bw_def_underlay420_luma;
184 0 : surface_type[2] = bw_def_underlay420_luma;
185 0 : data->bytes_per_pixel[0] = 1;
186 0 : data->bytes_per_pixel[2] = 1;
187 0 : surface_type[1] = bw_def_underlay420_chroma;
188 0 : surface_type[3] = bw_def_underlay420_chroma;
189 0 : data->bytes_per_pixel[1] = 2;
190 0 : data->bytes_per_pixel[3] = 2;
191 0 : data->lb_size_per_component[0] = dceip->underlay420_luma_lb_size_per_component;
192 0 : data->lb_size_per_component[1] = dceip->underlay420_chroma_lb_size_per_component;
193 0 : data->lb_size_per_component[2] = dceip->underlay420_luma_lb_size_per_component;
194 0 : data->lb_size_per_component[3] = dceip->underlay420_chroma_lb_size_per_component;
195 0 : break;
196 : case bw_def_422:
197 0 : surface_type[0] = bw_def_underlay422;
198 0 : surface_type[2] = bw_def_underlay422;
199 0 : data->bytes_per_pixel[0] = 2;
200 0 : data->bytes_per_pixel[2] = 2;
201 0 : data->lb_size_per_component[0] = dceip->underlay422_lb_size_per_component;
202 0 : data->lb_size_per_component[2] = dceip->underlay422_lb_size_per_component;
203 0 : break;
204 : default:
205 0 : surface_type[0] = bw_def_underlay444;
206 0 : surface_type[2] = bw_def_underlay444;
207 0 : data->bytes_per_pixel[0] = 4;
208 0 : data->bytes_per_pixel[2] = 4;
209 0 : data->lb_size_per_component[0] = dceip->lb_size_per_component444;
210 0 : data->lb_size_per_component[2] = dceip->lb_size_per_component444;
211 0 : break;
212 : }
213 0 : if (d0_underlay_enable) {
214 0 : switch (data->underlay_surface_type) {
215 : case bw_def_420:
216 0 : data->enable[0] = 1;
217 0 : data->enable[1] = 1;
218 0 : break;
219 : default:
220 0 : data->enable[0] = 1;
221 0 : data->enable[1] = 0;
222 0 : break;
223 : }
224 : }
225 : else {
226 0 : data->enable[0] = 0;
227 0 : data->enable[1] = 0;
228 : }
229 0 : if (d1_underlay_enable) {
230 0 : switch (data->underlay_surface_type) {
231 : case bw_def_420:
232 0 : data->enable[2] = 1;
233 0 : data->enable[3] = 1;
234 0 : break;
235 : default:
236 0 : data->enable[2] = 1;
237 0 : data->enable[3] = 0;
238 0 : break;
239 : }
240 : }
241 : else {
242 0 : data->enable[2] = 0;
243 0 : data->enable[3] = 0;
244 : }
245 0 : data->use_alpha[0] = 0;
246 0 : data->use_alpha[1] = 0;
247 0 : data->use_alpha[2] = 0;
248 0 : data->use_alpha[3] = 0;
249 0 : data->scatter_gather_enable_for_pipe[0] = vbios->scatter_gather_enable;
250 0 : data->scatter_gather_enable_for_pipe[1] = vbios->scatter_gather_enable;
251 0 : data->scatter_gather_enable_for_pipe[2] = vbios->scatter_gather_enable;
252 0 : data->scatter_gather_enable_for_pipe[3] = vbios->scatter_gather_enable;
253 : /*underlay0 same and graphics display pipe0*/
254 0 : data->interlace_mode[0] = data->interlace_mode[4];
255 0 : data->interlace_mode[1] = data->interlace_mode[4];
256 : /*underlay1 same and graphics display pipe1*/
257 0 : data->interlace_mode[2] = data->interlace_mode[5];
258 0 : data->interlace_mode[3] = data->interlace_mode[5];
259 : /*underlay0 same and graphics display pipe0*/
260 0 : data->h_total[0] = data->h_total[4];
261 0 : data->v_total[0] = data->v_total[4];
262 0 : data->h_total[1] = data->h_total[4];
263 0 : data->v_total[1] = data->v_total[4];
264 : /*underlay1 same and graphics display pipe1*/
265 0 : data->h_total[2] = data->h_total[5];
266 0 : data->v_total[2] = data->v_total[5];
267 0 : data->h_total[3] = data->h_total[5];
268 0 : data->v_total[3] = data->v_total[5];
269 : /*underlay0 same and graphics display pipe0*/
270 0 : data->pixel_rate[0] = data->pixel_rate[4];
271 0 : data->pixel_rate[1] = data->pixel_rate[4];
272 : /*underlay1 same and graphics display pipe1*/
273 0 : data->pixel_rate[2] = data->pixel_rate[5];
274 0 : data->pixel_rate[3] = data->pixel_rate[5];
275 0 : if ((data->underlay_tiling_mode == bw_def_array_linear_general || data->underlay_tiling_mode == bw_def_array_linear_aligned)) {
276 0 : tiling_mode[0] = bw_def_linear;
277 0 : tiling_mode[1] = bw_def_linear;
278 0 : tiling_mode[2] = bw_def_linear;
279 0 : tiling_mode[3] = bw_def_linear;
280 : }
281 : else {
282 0 : tiling_mode[0] = bw_def_landscape;
283 0 : tiling_mode[1] = bw_def_landscape;
284 0 : tiling_mode[2] = bw_def_landscape;
285 0 : tiling_mode[3] = bw_def_landscape;
286 : }
287 0 : data->lb_bpc[0] = data->underlay_lb_bpc;
288 0 : data->lb_bpc[1] = data->underlay_lb_bpc;
289 0 : data->lb_bpc[2] = data->underlay_lb_bpc;
290 0 : data->lb_bpc[3] = data->underlay_lb_bpc;
291 0 : data->compression_rate[0] = bw_int_to_fixed(1);
292 0 : data->compression_rate[1] = bw_int_to_fixed(1);
293 0 : data->compression_rate[2] = bw_int_to_fixed(1);
294 0 : data->compression_rate[3] = bw_int_to_fixed(1);
295 0 : data->access_one_channel_only[0] = 0;
296 0 : data->access_one_channel_only[1] = 0;
297 0 : data->access_one_channel_only[2] = 0;
298 0 : data->access_one_channel_only[3] = 0;
299 0 : data->cursor_width_pixels[0] = bw_int_to_fixed(0);
300 0 : data->cursor_width_pixels[1] = bw_int_to_fixed(0);
301 0 : data->cursor_width_pixels[2] = bw_int_to_fixed(0);
302 0 : data->cursor_width_pixels[3] = bw_int_to_fixed(0);
303 : /* graphics surface parameters from spreadsheet*/
304 0 : fbc_enabled = false;
305 0 : lpt_enabled = false;
306 0 : for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
307 0 : if (i < data->number_of_displays + 4) {
308 0 : if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) {
309 0 : data->enable[i] = 0;
310 0 : data->use_alpha[i] = 0;
311 : }
312 0 : else if (i == 4 && data->d0_underlay_mode == bw_def_blend) {
313 0 : data->enable[i] = 1;
314 0 : data->use_alpha[i] = 1;
315 : }
316 0 : else if (i == 4) {
317 0 : data->enable[i] = 1;
318 0 : data->use_alpha[i] = 0;
319 : }
320 0 : else if (i == 5 && data->d1_underlay_mode == bw_def_underlay_only) {
321 0 : data->enable[i] = 0;
322 0 : data->use_alpha[i] = 0;
323 : }
324 0 : else if (i == 5 && data->d1_underlay_mode == bw_def_blend) {
325 0 : data->enable[i] = 1;
326 0 : data->use_alpha[i] = 1;
327 : }
328 : else {
329 0 : data->enable[i] = 1;
330 0 : data->use_alpha[i] = 0;
331 : }
332 : }
333 : else {
334 0 : data->enable[i] = 0;
335 0 : data->use_alpha[i] = 0;
336 : }
337 0 : data->scatter_gather_enable_for_pipe[i] = vbios->scatter_gather_enable;
338 0 : surface_type[i] = bw_def_graphics;
339 0 : data->lb_size_per_component[i] = dceip->lb_size_per_component444;
340 0 : if (data->graphics_tiling_mode == bw_def_array_linear_general || data->graphics_tiling_mode == bw_def_array_linear_aligned) {
341 0 : tiling_mode[i] = bw_def_linear;
342 : }
343 : else {
344 0 : tiling_mode[i] = bw_def_tiled;
345 : }
346 0 : data->lb_bpc[i] = data->graphics_lb_bpc;
347 0 : if ((data->fbc_en[i] == 1 && (dceip->argb_compression_support || data->d0_underlay_mode != bw_def_blended))) {
348 0 : data->compression_rate[i] = bw_int_to_fixed(vbios->average_compression_rate);
349 0 : data->access_one_channel_only[i] = data->lpt_en[i];
350 : }
351 : else {
352 0 : data->compression_rate[i] = bw_int_to_fixed(1);
353 0 : data->access_one_channel_only[i] = 0;
354 : }
355 0 : if (data->fbc_en[i] == 1) {
356 0 : fbc_enabled = true;
357 0 : if (data->lpt_en[i] == 1) {
358 0 : lpt_enabled = true;
359 : }
360 : }
361 0 : data->cursor_width_pixels[i] = bw_int_to_fixed(vbios->cursor_width);
362 : }
363 : /* display_write_back420*/
364 0 : data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;
365 0 : data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;
366 0 : if (data->d1_display_write_back_dwb_enable == 1) {
367 0 : data->enable[maximum_number_of_surfaces - 2] = 1;
368 0 : data->enable[maximum_number_of_surfaces - 1] = 1;
369 : }
370 : else {
371 0 : data->enable[maximum_number_of_surfaces - 2] = 0;
372 0 : data->enable[maximum_number_of_surfaces - 1] = 0;
373 : }
374 0 : surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma;
375 0 : surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma;
376 0 : data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component;
377 0 : data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component;
378 0 : data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;
379 0 : data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;
380 0 : data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5];
381 0 : data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5];
382 0 : data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
383 0 : data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
384 0 : data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
385 0 : data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
386 0 : data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
387 0 : data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
388 0 : tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
389 0 : tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
390 0 : data->lb_bpc[maximum_number_of_surfaces - 2] = 8;
391 0 : data->lb_bpc[maximum_number_of_surfaces - 1] = 8;
392 0 : data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
393 0 : data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
394 0 : data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
395 0 : data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
396 : /*assume display pipe1 has dwb enabled*/
397 0 : data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5];
398 0 : data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5];
399 0 : data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5];
400 0 : data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5];
401 0 : data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5];
402 0 : data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5];
403 0 : data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5];
404 0 : data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5];
405 0 : data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];
406 0 : data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];
407 0 : data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5];
408 0 : data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5];
409 0 : data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
410 0 : data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
411 0 : data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
412 0 : data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
413 0 : data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;
414 0 : data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;
415 0 : data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
416 0 : data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
417 0 : data->use_alpha[maximum_number_of_surfaces - 2] = 0;
418 0 : data->use_alpha[maximum_number_of_surfaces - 1] = 0;
419 : /*mode check calculations:*/
420 : /* mode within dce ip capabilities*/
421 : /* fbc*/
422 : /* hsr*/
423 : /* vsr*/
424 : /* lb size*/
425 : /*effective scaling source and ratios:*/
426 : /*for graphics, non-stereo, non-interlace surfaces when the size of the source and destination are the same, only one tap is used*/
427 : /*420 chroma has half the width, height, horizontal and vertical scaling ratios than luma*/
428 : /*rotating a graphic or underlay surface swaps the width, height, horizontal and vertical scaling ratios*/
429 : /*in top-bottom stereo mode there is 2:1 vertical downscaling for each eye*/
430 : /*in side-by-side stereo mode there is 2:1 horizontal downscaling for each eye*/
431 : /*in interlace mode there is 2:1 vertical downscaling for each field*/
432 : /*in panning or bezel adjustment mode the source width has an extra 128 pixels*/
433 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
434 0 : if (data->enable[i]) {
435 0 : if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {
436 0 : data->h_taps[i] = bw_int_to_fixed(1);
437 0 : data->v_taps[i] = bw_int_to_fixed(1);
438 : }
439 0 : if (surface_type[i] == bw_def_display_write_back420_chroma || surface_type[i] == bw_def_underlay420_chroma) {
440 0 : data->pitch_in_pixels_after_surface_type[i] = bw_div(data->pitch_in_pixels[i], bw_int_to_fixed(2));
441 0 : data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2));
442 0 : data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));
443 0 : data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));
444 0 : data->vsr_after_surface_type = bw_div(data->v_scale_ratio[i], bw_int_to_fixed(2));
445 : }
446 : else {
447 0 : data->pitch_in_pixels_after_surface_type[i] = data->pitch_in_pixels[i];
448 0 : data->src_width_after_surface_type = data->src_width[i];
449 0 : data->src_height_after_surface_type = data->src_height[i];
450 0 : data->hsr_after_surface_type = data->h_scale_ratio[i];
451 0 : data->vsr_after_surface_type = data->v_scale_ratio[i];
452 : }
453 0 : if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
454 0 : data->src_width_after_rotation = data->src_height_after_surface_type;
455 0 : data->src_height_after_rotation = data->src_width_after_surface_type;
456 0 : data->hsr_after_rotation = data->vsr_after_surface_type;
457 0 : data->vsr_after_rotation = data->hsr_after_surface_type;
458 : }
459 : else {
460 0 : data->src_width_after_rotation = data->src_width_after_surface_type;
461 0 : data->src_height_after_rotation = data->src_height_after_surface_type;
462 0 : data->hsr_after_rotation = data->hsr_after_surface_type;
463 0 : data->vsr_after_rotation = data->vsr_after_surface_type;
464 : }
465 0 : switch (data->stereo_mode[i]) {
466 : case bw_def_top_bottom:
467 0 : data->source_width_pixels[i] = data->src_width_after_rotation;
468 0 : data->source_height_pixels = bw_mul(bw_int_to_fixed(2), data->src_height_after_rotation);
469 0 : data->hsr_after_stereo = data->hsr_after_rotation;
470 0 : data->vsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->vsr_after_rotation);
471 0 : break;
472 : case bw_def_side_by_side:
473 0 : data->source_width_pixels[i] = bw_mul(bw_int_to_fixed(2), data->src_width_after_rotation);
474 0 : data->source_height_pixels = data->src_height_after_rotation;
475 0 : data->hsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->hsr_after_rotation);
476 0 : data->vsr_after_stereo = data->vsr_after_rotation;
477 0 : break;
478 : default:
479 0 : data->source_width_pixels[i] = data->src_width_after_rotation;
480 0 : data->source_height_pixels = data->src_height_after_rotation;
481 0 : data->hsr_after_stereo = data->hsr_after_rotation;
482 0 : data->vsr_after_stereo = data->vsr_after_rotation;
483 0 : break;
484 : }
485 0 : data->hsr[i] = data->hsr_after_stereo;
486 0 : if (data->interlace_mode[i]) {
487 0 : data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2));
488 : }
489 : else {
490 0 : data->vsr[i] = data->vsr_after_stereo;
491 : }
492 0 : if (data->panning_and_bezel_adjustment != bw_def_none) {
493 0 : data->source_width_rounded_up_to_chunks[i] = bw_add(bw_floor2(bw_sub(data->source_width_pixels[i], bw_int_to_fixed(1)), bw_int_to_fixed(128)), bw_int_to_fixed(256));
494 : }
495 : else {
496 0 : data->source_width_rounded_up_to_chunks[i] = bw_ceil2(data->source_width_pixels[i], bw_int_to_fixed(128));
497 : }
498 0 : data->source_height_rounded_up_to_chunks[i] = data->source_height_pixels;
499 : }
500 : }
501 : /*mode support checks:*/
502 : /*the number of graphics and underlay pipes is limited by the ip support*/
503 : /*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
504 : /*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
505 : /*the pre-downscaler reduces the line buffer source by the horizontal scale ratio*/
506 : /*the number of lines in the line buffer has to exceed the number of vertical taps*/
507 : /*the size of the line in the line buffer is the product of the source width and the bits per component, rounded up to a multiple of 48*/
508 : /*the size of the line in the line buffer in the case of 10 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
509 : /*the size of the line in the line buffer in the case of 8 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
510 : /*frame buffer compression is not supported with stereo mode, rotation, or non- 888 formats*/
511 : /*rotation is not supported with linear of stereo modes*/
512 0 : if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
513 : pipe_check = bw_def_ok;
514 : }
515 : else {
516 0 : pipe_check = bw_def_notok;
517 : }
518 0 : hsr_check = bw_def_ok;
519 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
520 0 : if (data->enable[i]) {
521 0 : if (bw_neq(data->hsr[i], bw_int_to_fixed(1))) {
522 0 : if (bw_mtn(data->hsr[i], bw_int_to_fixed(4))) {
523 : hsr_check = bw_def_hsr_mtn_4;
524 : }
525 : else {
526 0 : if (bw_mtn(data->hsr[i], data->h_taps[i])) {
527 : hsr_check = bw_def_hsr_mtn_h_taps;
528 : }
529 : else {
530 0 : if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) {
531 0 : hsr_check = bw_def_ceiling__h_taps_div_4___meq_hsr;
532 : }
533 : }
534 : }
535 : }
536 : }
537 : }
538 : vsr_check = bw_def_ok;
539 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
540 0 : if (data->enable[i]) {
541 0 : if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) {
542 0 : if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) {
543 : vsr_check = bw_def_vsr_mtn_4;
544 : }
545 : else {
546 0 : if (bw_mtn(data->vsr[i], data->v_taps[i])) {
547 0 : vsr_check = bw_def_vsr_mtn_v_taps;
548 : }
549 : }
550 : }
551 : }
552 : }
553 : lb_size_check = bw_def_ok;
554 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
555 0 : if (data->enable[i]) {
556 0 : if ((dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1)))) {
557 0 : data->source_width_in_lb = bw_div(data->source_width_pixels[i], data->hsr[i]);
558 : }
559 : else {
560 0 : data->source_width_in_lb = data->source_width_pixels[i];
561 : }
562 0 : switch (data->lb_bpc[i]) {
563 : case 8:
564 0 : data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
565 0 : break;
566 : case 10:
567 0 : data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
568 0 : break;
569 : default:
570 0 : data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));
571 0 : break;
572 : }
573 0 : data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
574 : /*clamp the partitions to the maxium number supported by the lb*/
575 0 : if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
576 0 : data->lb_partitions_max[i] = bw_int_to_fixed(10);
577 : }
578 : else {
579 0 : data->lb_partitions_max[i] = bw_int_to_fixed(7);
580 : }
581 0 : data->lb_partitions[i] = bw_min2(data->lb_partitions_max[i], data->lb_partitions[i]);
582 0 : if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
583 0 : lb_size_check = bw_def_notok;
584 : }
585 : }
586 : }
587 : fbc_check = bw_def_ok;
588 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
589 0 : if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {
590 : fbc_check = bw_def_invalid_rotation_or_bpp_or_stereo;
591 : }
592 : }
593 : rotation_check = bw_def_ok;
594 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
595 0 : if (data->enable[i]) {
596 0 : if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
597 0 : rotation_check = bw_def_invalid_linear_or_stereo_mode;
598 : }
599 : }
600 : }
601 0 : if (pipe_check == bw_def_ok && hsr_check == bw_def_ok && vsr_check == bw_def_ok && lb_size_check == bw_def_ok && fbc_check == bw_def_ok && rotation_check == bw_def_ok) {
602 : mode_check = bw_def_ok;
603 : }
604 : else {
605 0 : mode_check = bw_def_notok;
606 : }
607 : /*number of memory channels for write-back client*/
608 0 : data->number_of_dram_wrchannels = vbios->number_of_dram_channels;
609 0 : data->number_of_dram_channels = vbios->number_of_dram_channels;
610 : /*modify number of memory channels if lpt mode is enabled*/
611 : /* low power tiling mode register*/
612 : /* 0 = use channel 0*/
613 : /* 1 = use channel 0 and 1*/
614 : /* 2 = use channel 0,1,2,3*/
615 0 : if ((fbc_enabled == 1 && lpt_enabled == 1)) {
616 0 : if (vbios->memory_type == bw_def_hbm)
617 0 : data->dram_efficiency = bw_frc_to_fixed(5, 10);
618 : else
619 0 : data->dram_efficiency = bw_int_to_fixed(1);
620 :
621 :
622 0 : if (dceip->low_power_tiling_mode == 0) {
623 0 : data->number_of_dram_channels = 1;
624 : }
625 0 : else if (dceip->low_power_tiling_mode == 1) {
626 0 : data->number_of_dram_channels = 2;
627 : }
628 0 : else if (dceip->low_power_tiling_mode == 2) {
629 0 : data->number_of_dram_channels = 4;
630 : }
631 : else {
632 0 : data->number_of_dram_channels = 1;
633 : }
634 : }
635 : else {
636 0 : if (vbios->memory_type == bw_def_hbm)
637 0 : data->dram_efficiency = bw_frc_to_fixed(5, 10);
638 : else
639 0 : data->dram_efficiency = bw_frc_to_fixed(8, 10);
640 : }
641 : /*memory request size and latency hiding:*/
642 : /*request size is normally 64 byte, 2-line interleaved, with full latency hiding*/
643 : /*the display write-back requests are single line*/
644 : /*for tiled graphics surfaces, or undelay surfaces with width higher than the maximum size for full efficiency, request size is 32 byte in 8 and 16 bpp or if the rotation is orthogonal to the tiling grain. only half is useful of the bytes in the request size in 8 bpp or in 32 bpp if the rotation is orthogonal to the tiling grain.*/
645 : /*for undelay surfaces with width lower than the maximum size for full efficiency, requests are 4-line interleaved in 16bpp if the rotation is parallel to the tiling grain, and 8-line interleaved with 4-line latency hiding in 8bpp or if the rotation is orthogonal to the tiling grain.*/
646 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
647 0 : if (data->enable[i]) {
648 0 : if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)))) {
649 0 : if ((i < 4)) {
650 : /*underlay portrait tiling mode is not supported*/
651 0 : data->orthogonal_rotation[i] = 1;
652 : }
653 : else {
654 : /*graphics portrait tiling mode*/
655 0 : if (data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling) {
656 0 : data->orthogonal_rotation[i] = 0;
657 : }
658 : else {
659 0 : data->orthogonal_rotation[i] = 1;
660 : }
661 : }
662 : }
663 : else {
664 0 : if ((i < 4)) {
665 : /*underlay landscape tiling mode is only supported*/
666 0 : if (data->underlay_micro_tile_mode == bw_def_display_micro_tiling) {
667 0 : data->orthogonal_rotation[i] = 0;
668 : }
669 : else {
670 0 : data->orthogonal_rotation[i] = 1;
671 : }
672 : }
673 : else {
674 : /*graphics landscape tiling mode*/
675 0 : if (data->graphics_micro_tile_mode == bw_def_display_micro_tiling) {
676 0 : data->orthogonal_rotation[i] = 0;
677 : }
678 : else {
679 0 : data->orthogonal_rotation[i] = 1;
680 : }
681 : }
682 : }
683 0 : if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) {
684 0 : data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_height_efficient_for_tiling;
685 : }
686 : else {
687 0 : data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_width_efficient_for_tiling;
688 : }
689 0 : if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
690 0 : data->bytes_per_request[i] = bw_int_to_fixed(64);
691 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
692 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(1);
693 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(1);
694 : }
695 0 : else if (tiling_mode[i] == bw_def_linear) {
696 0 : data->bytes_per_request[i] = bw_int_to_fixed(64);
697 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
698 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
699 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
700 : }
701 : else {
702 0 : if (surface_type[i] == bw_def_graphics || (bw_mtn(data->source_width_rounded_up_to_chunks[i], bw_ceil2(data->underlay_maximum_source_efficient_for_tiling, bw_int_to_fixed(256))))) {
703 0 : switch (data->bytes_per_pixel[i]) {
704 : case 8:
705 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
706 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
707 0 : if (data->orthogonal_rotation[i]) {
708 0 : data->bytes_per_request[i] = bw_int_to_fixed(32);
709 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
710 : }
711 : else {
712 0 : data->bytes_per_request[i] = bw_int_to_fixed(64);
713 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
714 : }
715 : break;
716 : case 4:
717 0 : if (data->orthogonal_rotation[i]) {
718 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
719 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
720 0 : data->bytes_per_request[i] = bw_int_to_fixed(32);
721 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
722 : }
723 : else {
724 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
725 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
726 0 : data->bytes_per_request[i] = bw_int_to_fixed(64);
727 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
728 : }
729 : break;
730 : case 2:
731 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
732 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
733 0 : data->bytes_per_request[i] = bw_int_to_fixed(32);
734 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
735 0 : break;
736 : default:
737 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
738 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
739 0 : data->bytes_per_request[i] = bw_int_to_fixed(32);
740 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
741 0 : break;
742 : }
743 : }
744 : else {
745 0 : data->bytes_per_request[i] = bw_int_to_fixed(64);
746 0 : data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
747 0 : if (data->orthogonal_rotation[i]) {
748 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
749 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(4);
750 : }
751 : else {
752 0 : switch (data->bytes_per_pixel[i]) {
753 : case 4:
754 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
755 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(2);
756 0 : break;
757 : case 2:
758 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(4);
759 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(4);
760 0 : break;
761 : default:
762 0 : data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
763 0 : data->latency_hiding_lines[i] = bw_int_to_fixed(4);
764 0 : break;
765 : }
766 : }
767 : }
768 : }
769 : }
770 : }
771 : /*requested peak bandwidth:*/
772 : /*the peak request-per-second bandwidth is the product of the maximum source lines in per line out in the beginning*/
773 : /*and in the middle of the frame, the ratio of the source width to the line time, the ratio of line interleaving*/
774 : /*in memory to lines of latency hiding, and the ratio of bytes per pixel to useful bytes per request.*/
775 : /**/
776 : /*if the dmif data buffer size holds more than vta_ps worth of source lines, then only vsr is used.*/
777 : /*the peak bandwidth is the peak request-per-second bandwidth times the request size.*/
778 : /**/
779 : /*the line buffer lines in per line out in the beginning of the frame is the vertical filter initialization value*/
780 : /*rounded up to even and divided by the line times for initialization, which is normally three.*/
781 : /*the line buffer lines in per line out in the middle of the frame is at least one, or the vertical scale ratio,*/
782 : /*rounded up to line pairs if not doing line buffer prefetching.*/
783 : /**/
784 : /*the non-prefetching rounding up of the vertical scale ratio can also be done up to 1 (for a 0,2 pattern), 4/3 (for a 0,2,2 pattern),*/
785 : /*6/4 (for a 0,2,2,2 pattern), or 3 (for a 2,4 pattern).*/
786 : /**/
787 : /*the scaler vertical filter initialization value is calculated by the hardware as the floor of the average of the*/
788 : /*vertical scale ratio and the number of vertical taps increased by one. add one more for possible odd line*/
789 : /*panning/bezel adjustment mode.*/
790 : /**/
791 : /*for the bottom interlace field an extra 50% of the vertical scale ratio is considered for this calculation.*/
792 : /*in top-bottom stereo mode software has to set the filter initialization value manually and explicitly limit it to 4.*/
793 : /*furthermore, there is only one line time for initialization.*/
794 : /**/
795 : /*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus*/
796 : /*the ceiling of the vertical scale ratio.*/
797 : /**/
798 : /*multi-line buffer prefetching is only done in the graphics pipe when the scaler is disabled or when upscaling and the vsr <= 0.8.'*/
799 : /**/
800 : /*the horizontal blank and chunk granularity factor is indirectly used indicate the interval of time required to transfer the source pixels.*/
801 : /*the denominator of this term represents the total number of destination output pixels required for the input source pixels.*/
802 : /*it applies when the lines in per line out is not 2 or 4. it does not apply when there is a line buffer between the scl and blnd.*/
803 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
804 0 : if (data->enable[i]) {
805 0 : data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));
806 0 : if (data->panning_and_bezel_adjustment == bw_def_any_lines) {
807 0 : data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));
808 : }
809 0 : if (data->stereo_mode[i] == bw_def_top_bottom) {
810 0 : data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));
811 : }
812 0 : if (data->stereo_mode[i] == bw_def_top_bottom) {
813 0 : data->num_lines_at_frame_start = bw_int_to_fixed(1);
814 : }
815 : else {
816 0 : data->num_lines_at_frame_start = bw_int_to_fixed(3);
817 : }
818 0 : if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) {
819 0 : data->line_buffer_prefetch[i] = 0;
820 : }
821 0 : else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
822 0 : data->line_buffer_prefetch[i] = 1;
823 : }
824 : else {
825 0 : data->line_buffer_prefetch[i] = 0;
826 : }
827 0 : data->lb_lines_in_per_line_out_in_beginning_of_frame[i] = bw_div(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->num_lines_at_frame_start);
828 0 : if (data->line_buffer_prefetch[i] == 1) {
829 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]);
830 : }
831 0 : else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) {
832 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(1);
833 0 : } else if (bw_leq(data->vsr[i],
834 : bw_frc_to_fixed(4, 3))) {
835 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(4), bw_int_to_fixed(3));
836 0 : } else if (bw_leq(data->vsr[i],
837 : bw_frc_to_fixed(6, 4))) {
838 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(6), bw_int_to_fixed(4));
839 : }
840 0 : else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) {
841 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(2);
842 : }
843 0 : else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) {
844 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(3);
845 : }
846 : else {
847 0 : data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(4);
848 : }
849 0 : if (data->line_buffer_prefetch[i] == 1 || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(2)) || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(4))) {
850 0 : data->horizontal_blank_and_chunk_granularity_factor[i] = bw_int_to_fixed(1);
851 : }
852 : else {
853 0 : data->horizontal_blank_and_chunk_granularity_factor[i] = bw_div(data->h_total[i], (bw_div((bw_add(data->h_total[i], bw_div((bw_sub(data->source_width_pixels[i], bw_int_to_fixed(dceip->chunk_width))), data->hsr[i]))), bw_int_to_fixed(2))));
854 : }
855 0 : data->request_bandwidth[i] = bw_div(bw_mul(bw_div(bw_mul(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], data->lb_lines_in_per_line_out_in_middle_of_frame[i]), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to_fixed(data->bytes_per_pixel[i])), data->useful_bytes_per_request[i]), data->lines_interleaved_in_mem_access[i]), data->latency_hiding_lines[i]);
856 0 : data->display_bandwidth[i] = bw_mul(data->request_bandwidth[i], data->bytes_per_request[i]);
857 : }
858 : }
859 : /*outstanding chunk request limit*/
860 : /*if underlay buffer sharing is enabled, the data buffer size for underlay in 422 or 444 is the sum of the luma and chroma data buffer sizes.*/
861 : /*underlay buffer sharing mode is only permitted in orthogonal rotation modes.*/
862 : /**/
863 : /*if there is only one display enabled, the dmif data buffer size for the graphics surface is increased by concatenating the adjacent buffers.*/
864 : /**/
865 : /*the memory chunk size in bytes is 1024 for the writeback, and 256 times the memory line interleaving and the bytes per pixel for graphics*/
866 : /*and underlay.*/
867 : /**/
868 : /*the pipe chunk size uses 2 for line interleaving, except for the write back, in which case it is 1.*/
869 : /*graphics and underlay data buffer size is adjusted (limited) using the outstanding chunk request limit if there is more than one*/
870 : /*display enabled or if the dmif request buffer is not large enough for the total data buffer size.*/
871 : /*the outstanding chunk request limit is the ceiling of the adjusted data buffer size divided by the chunk size in bytes*/
872 : /*the adjusted data buffer size is the product of the display bandwidth and the minimum effective data buffer size in terms of time,*/
873 : /*rounded up to the chunk size in bytes, but should not exceed the original data buffer size*/
874 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
875 0 : if (data->enable[i]) {
876 0 : if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
877 0 : data->max_chunks_non_fbc_mode[i] = 128 - dmif_chunk_buff_margin;
878 : }
879 : else {
880 0 : data->max_chunks_non_fbc_mode[i] = 16 - dmif_chunk_buff_margin;
881 : }
882 : }
883 : if (data->fbc_en[i] == 1) {
884 : max_chunks_fbc_mode = 128 - dmif_chunk_buff_margin;
885 : }
886 : }
887 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
888 0 : if (data->enable[i]) {
889 0 : switch (surface_type[i]) {
890 : case bw_def_display_write_back420_luma:
891 0 : data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_luma_mcifwr_buffer_size);
892 0 : break;
893 : case bw_def_display_write_back420_chroma:
894 0 : data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_chroma_mcifwr_buffer_size);
895 0 : break;
896 : case bw_def_underlay420_luma:
897 0 : data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
898 0 : break;
899 : case bw_def_underlay420_chroma:
900 0 : data->data_buffer_size[i] = bw_div(bw_int_to_fixed(dceip->underlay_chroma_dmif_size), bw_int_to_fixed(2));
901 0 : break;
902 : case bw_def_underlay422:case bw_def_underlay444:
903 0 : if (data->orthogonal_rotation[i] == 0) {
904 0 : data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
905 : }
906 : else {
907 0 : data->data_buffer_size[i] = bw_add(bw_int_to_fixed(dceip->underlay_luma_dmif_size), bw_int_to_fixed(dceip->underlay_chroma_dmif_size));
908 : }
909 : break;
910 : default:
911 0 : if (data->fbc_en[i] == 1) {
912 : /*data_buffer_size(i) = max_dmif_buffer_allocated * graphics_dmif_size*/
913 0 : if (data->number_of_displays == 1) {
914 0 : data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
915 : }
916 : else {
917 0 : data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
918 : }
919 : }
920 : else {
921 : /*the effective dmif buffer size in non-fbc mode is limited by the 16 entry chunk tracker*/
922 0 : if (data->number_of_displays == 1) {
923 0 : data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
924 : }
925 : else {
926 0 : data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
927 : }
928 : }
929 : break;
930 : }
931 0 : if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
932 0 : data->memory_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
933 0 : data->pipe_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
934 : }
935 : else {
936 0 : data->memory_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), data->lines_interleaved_in_mem_access[i]), bw_int_to_fixed(data->bytes_per_pixel[i]));
937 0 : data->pipe_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_int_to_fixed(data->bytes_per_pixel[i]));
938 : }
939 : }
940 : }
941 0 : data->min_dmif_size_in_time = bw_int_to_fixed(9999);
942 0 : data->min_mcifwr_size_in_time = bw_int_to_fixed(9999);
943 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
944 0 : if (data->enable[i]) {
945 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
946 0 : if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_dmif_size_in_time)) {
947 0 : data->min_dmif_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
948 : }
949 : }
950 : else {
951 0 : if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_mcifwr_size_in_time)) {
952 0 : data->min_mcifwr_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
953 : }
954 : }
955 : }
956 : }
957 0 : data->total_requests_for_dmif_size = bw_int_to_fixed(0);
958 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
959 0 : if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
960 0 : data->total_requests_for_dmif_size = bw_add(data->total_requests_for_dmif_size, bw_div(data->data_buffer_size[i], data->useful_bytes_per_request[i]));
961 : }
962 : }
963 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
964 0 : if (data->enable[i]) {
965 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma && dceip->limit_excessive_outstanding_dmif_requests && (data->number_of_displays > 1 || bw_mtn(data->total_requests_for_dmif_size, dceip->dmif_request_buffer_size))) {
966 0 : data->adjusted_data_buffer_size[i] = bw_min2(data->data_buffer_size[i], bw_ceil2(bw_mul(data->min_dmif_size_in_time, data->display_bandwidth[i]), data->memory_chunk_size_in_bytes[i]));
967 : }
968 : else {
969 0 : data->adjusted_data_buffer_size[i] = data->data_buffer_size[i];
970 : }
971 : }
972 : }
973 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
974 0 : if (data->enable[i]) {
975 0 : if (data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0) {
976 : /*set maximum chunk limit if only one graphic pipe is enabled*/
977 0 : data->outstanding_chunk_request_limit[i] = bw_int_to_fixed(127);
978 : }
979 : else {
980 0 : data->outstanding_chunk_request_limit[i] = bw_ceil2(bw_div(data->adjusted_data_buffer_size[i], data->pipe_chunk_size_in_bytes[i]), bw_int_to_fixed(1));
981 : /*clamp maximum chunk limit in the graphic display pipe*/
982 0 : if (i >= 4) {
983 0 : data->outstanding_chunk_request_limit[i] = bw_max2(bw_int_to_fixed(127), data->outstanding_chunk_request_limit[i]);
984 : }
985 : }
986 : }
987 : }
988 : /*outstanding pte request limit*/
989 : /*in tiling mode with no rotation the sg pte requests are 8 useful pt_es, the sg row height is the page height and the sg page width x height is 64x64 for 8bpp, 64x32 for 16 bpp, 32x32 for 32 bpp*/
990 : /*in tiling mode with rotation the sg pte requests are only one useful pte, and the sg row height is also the page height, but the sg page width and height are swapped*/
991 : /*in linear mode the pte requests are 8 useful pt_es, the sg page width is 4096 divided by the bytes per pixel, the sg page height is 1, but there is just one row whose height is the lines of pte prefetching*/
992 : /*the outstanding pte request limit is obtained by multiplying the outstanding chunk request limit by the peak pte request to eviction limiting ratio, rounding up to integer, multiplying by the pte requests per chunk, and rounding up to integer again*/
993 : /*if not using peak pte request to eviction limiting, the outstanding pte request limit is the pte requests in the vblank*/
994 : /*the pte requests in the vblank is the product of the number of pte request rows times the number of pte requests in a row*/
995 : /*the number of pte requests in a row is the quotient of the source width divided by 256, multiplied by the pte requests per chunk, rounded up to even, multiplied by the scatter-gather row height and divided by the scatter-gather page height*/
996 : /*the pte requests per chunk is 256 divided by the scatter-gather page width and the useful pt_es per pte request*/
997 0 : if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {
998 0 : data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
999 : }
1000 : else {
1001 0 : data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
1002 : }
1003 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1004 0 : if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
1005 0 : if (tiling_mode[i] == bw_def_linear) {
1006 0 : data->useful_pte_per_pte_request = bw_int_to_fixed(8);
1007 0 : data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i]));
1008 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(1);
1009 0 : data->scatter_gather_pte_request_rows = bw_int_to_fixed(1);
1010 0 : data->scatter_gather_row_height = bw_int_to_fixed(dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
1011 : }
1012 0 : else if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(0)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(180))) {
1013 0 : data->useful_pte_per_pte_request = bw_int_to_fixed(8);
1014 0 : switch (data->bytes_per_pixel[i]) {
1015 : case 4:
1016 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1017 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1018 0 : break;
1019 : case 2:
1020 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1021 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1022 0 : break;
1023 : default:
1024 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1025 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1026 0 : break;
1027 : }
1028 0 : data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1029 0 : data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1030 : }
1031 : else {
1032 0 : data->useful_pte_per_pte_request = bw_int_to_fixed(1);
1033 0 : switch (data->bytes_per_pixel[i]) {
1034 : case 4:
1035 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1036 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1037 0 : break;
1038 : case 2:
1039 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1040 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1041 0 : break;
1042 : default:
1043 0 : data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1044 0 : data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1045 0 : break;
1046 : }
1047 0 : data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1048 0 : data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1049 : }
1050 0 : data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request);
1051 0 : data->scatter_gather_pte_requests_in_row[i] = bw_div(bw_mul(bw_ceil2(bw_mul(bw_div(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(dceip->chunk_width)), data->pte_request_per_chunk[i]), bw_int_to_fixed(1)), data->scatter_gather_row_height), data->scatter_gather_page_height[i]);
1052 0 : data->scatter_gather_pte_requests_in_vblank = bw_mul(data->scatter_gather_pte_request_rows, data->scatter_gather_pte_requests_in_row[i]);
1053 0 : if (bw_equ(data->peak_pte_request_to_eviction_ratio_limiting, bw_int_to_fixed(0))) {
1054 0 : data->scatter_gather_pte_request_limit[i] = data->scatter_gather_pte_requests_in_vblank;
1055 : }
1056 : else {
1057 0 : data->scatter_gather_pte_request_limit[i] = bw_max2(dceip->minimum_outstanding_pte_request_limit, bw_min2(data->scatter_gather_pte_requests_in_vblank, bw_ceil2(bw_mul(bw_mul(bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->memory_chunk_size_in_bytes[i]), data->pte_request_per_chunk[i]), data->peak_pte_request_to_eviction_ratio_limiting), bw_int_to_fixed(1))));
1058 : }
1059 : }
1060 : }
1061 : /*pitch padding recommended for efficiency in linear mode*/
1062 : /*in linear mode graphics or underlay with scatter gather, a pitch that is a multiple of the channel interleave (256 bytes) times the channel-bank rotation is not efficient*/
1063 : /*if that is the case it is recommended to pad the pitch by at least 256 pixels*/
1064 0 : data->inefficient_linear_pitch_in_bytes = bw_mul(bw_mul(bw_int_to_fixed(256), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels));
1065 :
1066 : /*pixel transfer time*/
1067 : /*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
1068 : /*for dmif, pte and cursor requests have to be included.*/
1069 : /*the dram data requirement is doubled when the data request size in bytes is less than the dram channel width times the burst size (8)*/
1070 : /*the dram data requirement is also multiplied by the number of channels in the case of low power tiling*/
1071 : /*the page close-open time is determined by trc and the number of page close-opens*/
1072 : /*in tiled mode graphics or underlay with scatter-gather enabled the bytes per page close-open is the product of the memory line interleave times the maximum of the scatter-gather page width and the product of the tile width (8 pixels) times the number of channels times the number of banks.*/
1073 : /*in linear mode graphics or underlay with scatter-gather enabled and inefficient pitch, the bytes per page close-open is the line request alternation slice, because different lines are in completely different 4k address bases.*/
1074 : /*otherwise, the bytes page close-open is the chunk size because that is the arbitration slice.*/
1075 : /*pte requests are grouped by pte requests per chunk if that is more than 1. each group costs a page close-open time for dmif reads*/
1076 : /*cursor requests outstanding are limited to a group of two source lines. each group costs a page close-open time for dmif reads*/
1077 : /*the display reads and writes time for data transfer is the minimum data or cursor buffer size in time minus the mc urgent latency*/
1078 : /*the mc urgent latency is experienced more than one time if the number of dmif requests in the data buffer exceeds the request buffer size plus the request slots reserved for dmif in the dram channel arbiter queues*/
1079 : /*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
1080 : /*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*/
1081 : /*the source line transfer time is the maximum for all surfaces of the maximum of the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the fist pixel, and the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the last pixel plus the active time.*/
1082 : /*the source pixels for the first output pixel is 512 if the scaler vertical filter initialization value is greater than 2, and it is 4 times the source width if it is greater than 4.*/
1083 : /*the source pixels for the last output pixel is the source width times the scaler vertical filter initialization value rounded up to even*/
1084 : /*the source data for these pixels is the number of pixels times the bytes per pixel times the bytes per request divided by the useful bytes per request.*/
1085 0 : data->cursor_total_data = bw_int_to_fixed(0);
1086 0 : data->cursor_total_request_groups = bw_int_to_fixed(0);
1087 0 : data->scatter_gather_total_pte_requests = bw_int_to_fixed(0);
1088 0 : data->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);
1089 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1090 0 : if (data->enable[i]) {
1091 0 : data->cursor_total_data = bw_add(data->cursor_total_data, bw_mul(bw_mul(bw_int_to_fixed(2), data->cursor_width_pixels[i]), bw_int_to_fixed(4)));
1092 0 : if (dceip->large_cursor == 1) {
1093 0 : data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_int_to_fixed((dceip->cursor_max_outstanding_group_num + 1)));
1094 : }
1095 : else {
1096 0 : data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_ceil2(bw_div(data->cursor_width_pixels[i], dceip->cursor_chunk_width), bw_int_to_fixed(1)));
1097 : }
1098 0 : if (data->scatter_gather_enable_for_pipe[i]) {
1099 0 : data->scatter_gather_total_pte_requests = bw_add(data->scatter_gather_total_pte_requests, data->scatter_gather_pte_request_limit[i]);
1100 0 : data->scatter_gather_total_pte_request_groups = bw_add(data->scatter_gather_total_pte_request_groups, bw_ceil2(bw_div(data->scatter_gather_pte_request_limit[i], bw_ceil2(data->pte_request_per_chunk[i], bw_int_to_fixed(1))), bw_int_to_fixed(1)));
1101 : }
1102 : }
1103 : }
1104 0 : data->tile_width_in_pixels = bw_int_to_fixed(8);
1105 0 : data->dmif_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1106 0 : data->mcifwr_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1107 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1108 0 : if (data->enable[i]) {
1109 0 : if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
1110 0 : data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i])));
1111 : }
1112 0 : else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {
1113 0 : data->bytes_per_page_close_open = dceip->linear_mode_line_request_alternation_slice;
1114 : }
1115 : else {
1116 0 : data->bytes_per_page_close_open = data->memory_chunk_size_in_bytes[i];
1117 : }
1118 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1119 0 : data->dmif_total_number_of_data_request_page_close_open = bw_add(data->dmif_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1120 : }
1121 : else {
1122 0 : data->mcifwr_total_number_of_data_request_page_close_open = bw_add(data->mcifwr_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1123 : }
1124 : }
1125 : }
1126 0 : data->dmif_total_page_close_open_time = bw_div(bw_mul((bw_add(bw_add(data->dmif_total_number_of_data_request_page_close_open, data->scatter_gather_total_pte_request_groups), data->cursor_total_request_groups)), vbios->trc), bw_int_to_fixed(1000));
1127 0 : data->mcifwr_total_page_close_open_time = bw_div(bw_mul(data->mcifwr_total_number_of_data_request_page_close_open, vbios->trc), bw_int_to_fixed(1000));
1128 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1129 0 : if (data->enable[i]) {
1130 0 : data->adjusted_data_buffer_size_in_memory[i] = bw_div(bw_mul(data->adjusted_data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1131 : }
1132 : }
1133 0 : data->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);
1134 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1135 0 : if (data->enable[i]) {
1136 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1137 0 : data->total_requests_for_adjusted_dmif_size = bw_add(data->total_requests_for_adjusted_dmif_size, bw_div(data->adjusted_data_buffer_size[i], data->useful_bytes_per_request[i]));
1138 : }
1139 : }
1140 : }
1141 0 : data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));
1142 0 : data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips);
1143 0 : data->total_display_reads_required_data = bw_int_to_fixed(0);
1144 0 : data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);
1145 0 : data->total_display_writes_required_data = bw_int_to_fixed(0);
1146 0 : data->total_display_writes_required_dram_access_data = bw_int_to_fixed(0);
1147 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1148 0 : if (data->enable[i]) {
1149 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1150 0 : data->display_reads_required_data = data->adjusted_data_buffer_size_in_memory[i];
1151 : /*for hbm memories, each channel is split into 2 pseudo-channels that are each 64 bits in width. each*/
1152 : /*pseudo-channel may be read independently of one another.*/
1153 : /*the read burst length (bl) for hbm memories is 4, so each read command will access 32 bytes of data.*/
1154 : /*the 64 or 32 byte sized data is stored in one pseudo-channel.*/
1155 : /*it will take 4 memclk cycles or 8 yclk cycles to fetch 64 bytes of data from the hbm memory (2 read commands).*/
1156 : /*it will take 2 memclk cycles or 4 yclk cycles to fetch 32 bytes of data from the hbm memory (1 read command).*/
1157 : /*for gddr5/ddr4 memories, there is additional overhead if the size of the request is smaller than 64 bytes.*/
1158 : /*the read burst length (bl) for gddr5/ddr4 memories is 8, regardless of the size of the data request.*/
1159 : /*therefore it will require 8 cycles to fetch 64 or 32 bytes of data from the memory.*/
1160 : /*the memory efficiency will be 50% for the 32 byte sized data.*/
1161 0 : if (vbios->memory_type == bw_def_hbm) {
1162 0 : data->display_reads_required_dram_access_data = data->adjusted_data_buffer_size_in_memory[i];
1163 : }
1164 : else {
1165 0 : data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));
1166 : }
1167 0 : data->total_display_reads_required_data = bw_add(data->total_display_reads_required_data, data->display_reads_required_data);
1168 0 : data->total_display_reads_required_dram_access_data = bw_add(data->total_display_reads_required_dram_access_data, data->display_reads_required_dram_access_data);
1169 : }
1170 : else {
1171 0 : data->total_display_writes_required_data = bw_add(data->total_display_writes_required_data, data->adjusted_data_buffer_size_in_memory[i]);
1172 0 : data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));
1173 : }
1174 : }
1175 : }
1176 0 : data->total_display_reads_required_data = bw_add(bw_add(data->total_display_reads_required_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1177 0 : data->total_display_reads_required_dram_access_data = bw_add(bw_add(data->total_display_reads_required_dram_access_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1178 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1179 0 : if (data->enable[i]) {
1180 0 : if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(4))) {
1181 0 : data->src_pixels_for_first_output_pixel[i] = bw_mul(bw_int_to_fixed(4), data->source_width_rounded_up_to_chunks[i]);
1182 : }
1183 : else {
1184 0 : if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(2))) {
1185 0 : data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(512);
1186 : }
1187 : else {
1188 0 : data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(0);
1189 : }
1190 : }
1191 0 : data->src_data_for_first_output_pixel[i] = bw_div(bw_mul(bw_mul(data->src_pixels_for_first_output_pixel[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1192 0 : data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i])));
1193 0 : data->src_data_for_last_output_pixel[i] = bw_div(bw_mul(bw_mul(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->lines_interleaved_in_mem_access[i])), bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1194 0 : data->active_time[i] = bw_div(bw_div(data->source_width_rounded_up_to_chunks[i], data->hsr[i]), data->pixel_rate[i]);
1195 : }
1196 : }
1197 0 : for (i = 0; i <= 2; i++) {
1198 0 : for (j = 0; j <= 7; j++) {
1199 0 : data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));
1200 0 : if (data->d1_display_write_back_dwb_enable == 1) {
1201 0 : data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));
1202 : }
1203 : }
1204 : }
1205 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1206 0 : for (j = 0; j <= 2; j++) {
1207 0 : for (k = 0; k <= 7; k++) {
1208 0 : if (data->enable[i]) {
1209 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1210 : /*time to transfer data from the dmif buffer to the lb. since the mc to dmif transfer time overlaps*/
1211 : /*with the dmif to lb transfer time, only time to transfer the last chunk is considered.*/
1212 0 : data->dmif_buffer_transfer_time[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], (bw_div(dceip->lb_write_pixels_per_dispclk, (bw_div(vbios->low_voltage_max_dispclk, dceip->display_pipe_throughput_factor)))));
1213 0 : data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
1214 : /*during an mclk switch the requests from the dce ip are stored in the gmc/arb. these requests should be serviced immediately*/
1215 : /*after the mclk switch sequence and not incur an urgent latency penalty. it is assumed that the gmc/arb can hold up to 256 requests*/
1216 : /*per memory channel. if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1217 : /*immediately serviced without a gap in the urgent requests.*/
1218 : /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1219 0 : if (surface_type[i] == bw_def_graphics) {
1220 0 : switch (data->lb_bpc[i]) {
1221 : case 6:
1222 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1223 0 : break;
1224 : case 8:
1225 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1226 0 : break;
1227 : case 10:
1228 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1229 0 : break;
1230 : default:
1231 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1232 0 : break;
1233 : }
1234 0 : if (data->use_alpha[i] == 1) {
1235 0 : data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1236 : }
1237 : }
1238 : else {
1239 0 : switch (data->lb_bpc[i]) {
1240 : case 6:
1241 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1242 0 : break;
1243 : case 8:
1244 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1245 0 : break;
1246 : case 10:
1247 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1248 0 : break;
1249 : default:
1250 0 : data->v_scaler_efficiency = bw_int_to_fixed(3);
1251 0 : break;
1252 : }
1253 : }
1254 0 : if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1255 0 : data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1256 : }
1257 : else {
1258 0 : data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1259 : }
1260 0 : data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
1261 : }
1262 : else {
1263 0 : data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
1264 0 : /*during an mclk switch the requests from the dce ip are stored in the gmc/arb. these requests should be serviced immediately*/
1265 : /*after the mclk switch sequence and not incur an urgent latency penalty. it is assumed that the gmc/arb can hold up to 256 requests*/
1266 : /*per memory channel. if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1267 : /*immediately serviced without a gap in the urgent requests.*/
1268 : /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1269 0 : data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
1270 : }
1271 : }
1272 : }
1273 0 : }
1274 : }
1275 : /*cpu c-state and p-state change enable*/
1276 : /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
1277 : /*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
1278 : /*condition for the blackout duration:*/
1279 : /* minimum latency hiding > blackout duration + dmif burst time + line source transfer time*/
1280 : /*condition for the blackout recovery:*/
1281 : /* recovery time > dmif burst time + 2 * urgent latency*/
1282 : /* recovery time > (display bw * blackout duration + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
1283 : /* / (dispclk - display bw)*/
1284 : /*the minimum latency hiding is the minimum for all pipes of one screen line time, plus one more line time if doing lb prefetch, plus the dmif data buffer size equivalent in time, minus the urgent latency.*/
1285 : /*the minimum latency hiding is further limited by the cursor. the cursor latency hiding is the number of lines of the cursor buffer, minus one if the downscaling is less than two, or minus three if it is more*/
1286 :
1287 : /*initialize variables*/
1288 : number_of_displays_enabled = 0;
1289 : number_of_displays_enabled_with_margin = 0;
1290 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1291 0 : if (data->enable[k]) {
1292 0 : number_of_displays_enabled = number_of_displays_enabled + 1;
1293 : }
1294 0 : data->display_pstate_change_enable[k] = 0;
1295 : }
1296 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1297 0 : if (data->enable[i]) {
1298 0 : if ((bw_equ(dceip->stutter_and_dram_clock_state_change_gated_before_cursor, bw_int_to_fixed(0)) && bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0)))) {
1299 0 : if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) {
1300 0 : data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1301 : }
1302 : else {
1303 0 : data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1304 : }
1305 : }
1306 : else {
1307 0 : data->cursor_latency_hiding[i] = bw_int_to_fixed(9999);
1308 : }
1309 : }
1310 : }
1311 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1312 0 : if (data->enable[i]) {
1313 0 : if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {
1314 0 : if (number_of_displays_enabled > 2)
1315 0 : data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1316 : else
1317 0 : data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1318 : }
1319 : else {
1320 0 : data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1321 : }
1322 0 : data->minimum_latency_hiding_with_cursor[i] = bw_min2(data->minimum_latency_hiding[i], data->cursor_latency_hiding[i]);
1323 : }
1324 : }
1325 0 : for (i = 0; i <= 2; i++) {
1326 0 : for (j = 0; j <= 7; j++) {
1327 0 : data->blackout_duration_margin[i][j] = bw_int_to_fixed(9999);
1328 0 : data->dispclk_required_for_blackout_duration[i][j] = bw_int_to_fixed(0);
1329 0 : data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(0);
1330 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1331 0 : if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
1332 0 : if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1333 0 : data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1334 0 : data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
1335 0 : if (bw_leq(vbios->maximum_blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))) {
1336 0 : data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1337 : }
1338 0 : else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1339 0 : data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1340 : }
1341 : }
1342 : else {
1343 0 : data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1344 0 : data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1345 0 : if (bw_ltn(vbios->maximum_blackout_recovery_time, bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))) {
1346 0 : data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1347 : }
1348 0 : else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1349 0 : data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1350 : }
1351 : }
1352 : }
1353 : }
1354 : }
1355 : }
1356 0 : if (bw_mtn(data->blackout_duration_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[high][s_high], vbios->high_voltage_max_dispclk)) {
1357 0 : data->cpup_state_change_enable = bw_def_yes;
1358 0 : if (bw_ltn(data->dispclk_required_for_blackout_recovery[high][s_high], vbios->high_voltage_max_dispclk)) {
1359 0 : data->cpuc_state_change_enable = bw_def_yes;
1360 : }
1361 : else {
1362 0 : data->cpuc_state_change_enable = bw_def_no;
1363 : }
1364 : }
1365 : else {
1366 0 : data->cpup_state_change_enable = bw_def_no;
1367 0 : data->cpuc_state_change_enable = bw_def_no;
1368 : }
1369 : /*nb p-state change enable*/
1370 : /*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
1371 : /*below the maximum.*/
1372 : /*the dram speed/p-state change margin is the minimum for all surfaces of the maximum latency hiding minus the dram speed/p-state change latency,*/
1373 : /*minus the dmif burst time, minus the source line transfer time*/
1374 : /*the maximum latency hiding is the minimum latency hiding plus one source line used for de-tiling in the line buffer, plus half the urgent latency*/
1375 : /*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
1376 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1377 0 : if (data->enable[i]) {
1378 : /*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) **/
1379 : /* h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
1380 0 : data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i],
1381 : bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
1382 0 : data->maximum_latency_hiding_with_cursor[i] = bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
1383 : }
1384 : }
1385 0 : for (i = 0; i <= 2; i++) {
1386 0 : for (j = 0; j <= 7; j++) {
1387 0 : data->min_dram_speed_change_margin[i][j] = bw_int_to_fixed(9999);
1388 0 : data->dram_speed_change_margin = bw_int_to_fixed(9999);
1389 0 : data->dispclk_required_for_dram_speed_change[i][j] = bw_int_to_fixed(0);
1390 0 : data->num_displays_with_margin[i][j] = 0;
1391 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1392 0 : if (data->enable[k]) {
1393 0 : if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1394 0 : data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1395 0 : if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1396 : /*determine the minimum dram clock change margin for each set of clock frequencies*/
1397 0 : data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1398 : /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1399 0 : data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
1400 0 : if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1401 0 : data->display_pstate_change_enable[k] = 1;
1402 0 : data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1403 0 : data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1404 : }
1405 : }
1406 : }
1407 : else {
1408 0 : data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1409 0 : if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1410 : /*determine the minimum dram clock change margin for each display pipe*/
1411 0 : data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1412 : /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1413 0 : data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1414 0 : if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1415 0 : data->display_pstate_change_enable[k] = 1;
1416 0 : data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1417 0 : data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1418 : }
1419 : }
1420 : }
1421 : }
1422 : }
1423 : }
1424 : }
1425 : /*determine the number of displays with margin to switch in the v_active region*/
1426 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1427 0 : if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
1428 0 : number_of_displays_enabled_with_margin = number_of_displays_enabled_with_margin + 1;
1429 : }
1430 : }
1431 : /*determine the number of displays that don't have any dram clock change margin, but*/
1432 : /*have the same resolution. these displays can switch in a common vblank region if*/
1433 : /*their frames are aligned.*/
1434 0 : data->min_vblank_dram_speed_change_margin = bw_int_to_fixed(9999);
1435 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1436 0 : if (data->enable[k]) {
1437 0 : if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1438 0 : data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1439 0 : data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1440 : }
1441 : else {
1442 0 : data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1443 0 : data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1444 : }
1445 : }
1446 : }
1447 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1448 0 : data->displays_with_same_mode[i] = bw_int_to_fixed(0);
1449 0 : if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
1450 0 : for (j = 0; j <= maximum_number_of_surfaces - 1; j++) {
1451 0 : if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {
1452 0 : data->displays_with_same_mode[i] = bw_add(data->displays_with_same_mode[i], bw_int_to_fixed(1));
1453 : }
1454 : }
1455 : }
1456 : }
1457 : /*compute the maximum number of aligned displays with no margin*/
1458 : number_of_aligned_displays_with_no_margin = 0;
1459 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1460 0 : number_of_aligned_displays_with_no_margin = bw_fixed_to_int(bw_max2(bw_int_to_fixed(number_of_aligned_displays_with_no_margin), data->displays_with_same_mode[i]));
1461 : }
1462 : /*dram clock change is possible, if all displays have positive margin except for one display or a group of*/
1463 : /*aligned displays with the same timing.*/
1464 : /*the display(s) with the negative margin can be switched in the v_blank region while the other*/
1465 : /*displays are in v_blank or v_active.*/
1466 0 : if (number_of_displays_enabled_with_margin > 0 && (number_of_displays_enabled_with_margin + number_of_aligned_displays_with_no_margin) == number_of_displays_enabled && bw_mtn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(9999)) && bw_ltn(data->dispclk_required_for_dram_speed_change[high][s_high], vbios->high_voltage_max_dispclk)) {
1467 0 : data->nbp_state_change_enable = bw_def_yes;
1468 : }
1469 : else {
1470 0 : data->nbp_state_change_enable = bw_def_no;
1471 : }
1472 : /*dram clock change is possible only in vblank if all displays are aligned and have no margin*/
1473 0 : if (number_of_aligned_displays_with_no_margin == number_of_displays_enabled) {
1474 : nbp_state_change_enable_blank = bw_def_yes;
1475 : }
1476 : else {
1477 0 : nbp_state_change_enable_blank = bw_def_no;
1478 : }
1479 :
1480 : /*average bandwidth*/
1481 : /*the average bandwidth with no compression is the vertical active time is the source width times the bytes per pixel divided by the line time, multiplied by the vertical scale ratio and the ratio of bytes per request divided by the useful bytes per request.*/
1482 : /*the average bandwidth with compression is the same, divided by the compression ratio*/
1483 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1484 0 : if (data->enable[i]) {
1485 0 : data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1486 0 : data->average_bandwidth[i] = bw_div(data->average_bandwidth_no_compression[i], data->compression_rate[i]);
1487 : }
1488 : }
1489 0 : data->total_average_bandwidth_no_compression = bw_int_to_fixed(0);
1490 0 : data->total_average_bandwidth = bw_int_to_fixed(0);
1491 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1492 0 : if (data->enable[i]) {
1493 0 : data->total_average_bandwidth_no_compression = bw_add(data->total_average_bandwidth_no_compression, data->average_bandwidth_no_compression[i]);
1494 0 : data->total_average_bandwidth = bw_add(data->total_average_bandwidth, data->average_bandwidth[i]);
1495 : }
1496 : }
1497 :
1498 : /*required yclk(pclk)*/
1499 : /*yclk requirement only makes sense if the dmif and mcifwr data total page close-open time is less than the time for data transfer and the total pte requests fit in the scatter-gather saw queque size*/
1500 : /*if that is the case, the yclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/low yclk(pclk) is chosen accordingly*/
1501 : /*high yclk(pclk) has to be selected when dram speed/p-state change is not possible.*/
1502 0 : data->min_cursor_memory_interface_buffer_size_in_time = bw_int_to_fixed(9999);
1503 : /* number of cursor lines stored in the cursor data return buffer*/
1504 0 : num_cursor_lines = 0;
1505 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1506 0 : if (data->enable[i]) {
1507 0 : if (bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0))) {
1508 : /*compute number of cursor lines stored in data return buffer*/
1509 0 : if (bw_leq(data->cursor_width_pixels[i], bw_int_to_fixed(64)) && dceip->large_cursor == 1) {
1510 : num_cursor_lines = 4;
1511 : }
1512 : else {
1513 0 : num_cursor_lines = 2;
1514 : }
1515 0 : data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i]));
1516 : }
1517 : }
1518 : }
1519 : /*compute minimum time to read one chunk from the dmif buffer*/
1520 0 : if (number_of_displays_enabled > 2) {
1521 0 : data->chunk_request_delay = 0;
1522 : }
1523 : else {
1524 0 : data->chunk_request_delay = bw_fixed_to_int(bw_div(bw_int_to_fixed(512), vbios->high_voltage_max_dispclk));
1525 : }
1526 0 : data->min_read_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, data->min_dmif_size_in_time);
1527 0 : data->display_reads_time_for_data_transfer = bw_sub(bw_sub(data->min_read_buffer_size_in_time, data->total_dmifmc_urgent_latency), bw_int_to_fixed(data->chunk_request_delay));
1528 0 : data->display_writes_time_for_data_transfer = bw_sub(data->min_mcifwr_size_in_time, vbios->mcifwrmc_urgent_latency);
1529 0 : data->dmif_required_dram_bandwidth = bw_div(data->total_display_reads_required_dram_access_data, data->display_reads_time_for_data_transfer);
1530 0 : data->mcifwr_required_dram_bandwidth = bw_div(data->total_display_writes_required_dram_access_data, data->display_writes_time_for_data_transfer);
1531 0 : data->required_dmifmc_urgent_latency_for_page_close_open = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_total_page_close_open_time)), data->total_dmifmc_urgent_trips);
1532 0 : data->required_mcifmcwr_urgent_latency = bw_sub(data->min_mcifwr_size_in_time, data->mcifwr_total_page_close_open_time);
1533 0 : if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1534 0 : data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1535 0 : yclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1536 0 : data->y_clk_level = high;
1537 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1538 : }
1539 0 : else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1540 0 : data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1541 0 : yclk_message = bw_def_exceeded_allowed_page_close_open;
1542 0 : data->y_clk_level = high;
1543 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1544 : }
1545 : else {
1546 0 : data->required_dram_bandwidth_gbyte_per_second = bw_div(bw_max2(data->dmif_required_dram_bandwidth, data->mcifwr_required_dram_bandwidth), bw_int_to_fixed(1000));
1547 0 : if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[low]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1548 0 : && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {
1549 0 : yclk_message = bw_fixed_to_int(vbios->low_yclk);
1550 0 : data->y_clk_level = low;
1551 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1552 0 : }
1553 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[mid]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1554 0 : && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {
1555 0 : yclk_message = bw_fixed_to_int(vbios->mid_yclk);
1556 0 : data->y_clk_level = mid;
1557 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1558 0 : }
1559 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[high]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1560 0 : && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {
1561 0 : yclk_message = bw_fixed_to_int(vbios->high_yclk);
1562 0 : data->y_clk_level = high;
1563 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1564 : }
1565 : else {
1566 0 : yclk_message = bw_def_exceeded_allowed_maximum_bw;
1567 0 : data->y_clk_level = high;
1568 0 : data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1569 : }
1570 : }
1571 : /*required sclk*/
1572 : /*sclk requirement only makes sense if the total pte requests fit in the scatter-gather saw queque size*/
1573 : /*if that is the case, the sclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/mid/low sclk is chosen accordingly, unless that choice results in foresaking dram speed/nb p-state change.*/
1574 : /*the dmif and mcifwr sclk required is the one that allows the transfer of all pipe's data buffer size through the sclk bus in the time for data transfer*/
1575 : /*for dmif, pte and cursor requests have to be included.*/
1576 0 : data->dmif_required_sclk = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
1577 0 : data->mcifwr_required_sclk = bw_div(bw_div(data->total_display_writes_required_data, data->display_writes_time_for_data_transfer), vbios->data_return_bus_width);
1578 0 : if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1579 0 : data->required_sclk = bw_int_to_fixed(9999);
1580 0 : sclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1581 0 : data->sclk_level = s_high;
1582 : }
1583 0 : else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1584 0 : data->required_sclk = bw_int_to_fixed(9999);
1585 0 : sclk_message = bw_def_exceeded_allowed_page_close_open;
1586 0 : data->sclk_level = s_high;
1587 : }
1588 : else {
1589 0 : data->required_sclk = bw_max2(data->dmif_required_sclk, data->mcifwr_required_sclk);
1590 0 : if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[low]),vbios->data_return_bus_width))
1591 0 : && bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) {
1592 0 : sclk_message = bw_def_low;
1593 0 : data->sclk_level = s_low;
1594 0 : data->required_sclk = vbios->low_sclk;
1595 0 : }
1596 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[mid]),vbios->data_return_bus_width))
1597 0 : && bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) {
1598 0 : sclk_message = bw_def_mid;
1599 0 : data->sclk_level = s_mid1;
1600 0 : data->required_sclk = vbios->mid1_sclk;
1601 0 : }
1602 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid2]),vbios->data_return_bus_width))
1603 0 : && bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) {
1604 0 : sclk_message = bw_def_mid;
1605 0 : data->sclk_level = s_mid2;
1606 0 : data->required_sclk = vbios->mid2_sclk;
1607 0 : }
1608 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid3]),vbios->data_return_bus_width))
1609 0 : && bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) {
1610 0 : sclk_message = bw_def_mid;
1611 0 : data->sclk_level = s_mid3;
1612 0 : data->required_sclk = vbios->mid3_sclk;
1613 0 : }
1614 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid4]),vbios->data_return_bus_width))
1615 0 : && bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) {
1616 0 : sclk_message = bw_def_mid;
1617 0 : data->sclk_level = s_mid4;
1618 0 : data->required_sclk = vbios->mid4_sclk;
1619 0 : }
1620 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid5]),vbios->data_return_bus_width))
1621 0 : && bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) {
1622 0 : sclk_message = bw_def_mid;
1623 0 : data->sclk_level = s_mid5;
1624 0 : data->required_sclk = vbios->mid5_sclk;
1625 0 : }
1626 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid6]),vbios->data_return_bus_width))
1627 0 : && bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) {
1628 0 : sclk_message = bw_def_mid;
1629 0 : data->sclk_level = s_mid6;
1630 0 : data->required_sclk = vbios->mid6_sclk;
1631 0 : }
1632 0 : else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1633 0 : && bw_ltn(data->required_sclk, sclk[s_high])) {
1634 0 : sclk_message = bw_def_high;
1635 0 : data->sclk_level = s_high;
1636 0 : data->required_sclk = vbios->high_sclk;
1637 : }
1638 0 : else if (bw_meq(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1639 0 : && bw_ltn(data->required_sclk, sclk[s_high])) {
1640 0 : sclk_message = bw_def_high;
1641 0 : data->sclk_level = s_high;
1642 0 : data->required_sclk = vbios->high_sclk;
1643 : }
1644 : else {
1645 0 : sclk_message = bw_def_exceeded_allowed_maximum_sclk;
1646 0 : data->sclk_level = s_high;
1647 : /*required_sclk = high_sclk*/
1648 : }
1649 : }
1650 : /*dispclk*/
1651 : /*if dispclk is set to the maximum, ramping is not required. dispclk required without ramping is less than the dispclk required with ramping.*/
1652 : /*if dispclk required without ramping is more than the maximum dispclk, that is the dispclk required, and the mode is not supported*/
1653 : /*if that does not happen, but dispclk required with ramping is more than the maximum dispclk, dispclk required is just the maximum dispclk*/
1654 : /*if that does not happen either, dispclk required is the dispclk required with ramping.*/
1655 : /*dispclk required without ramping is the maximum of the one required for display pipe pixel throughput, for scaler throughput, for total read request thrrougput and for dram/np p-state change if enabled.*/
1656 : /*the display pipe pixel throughput is the maximum of lines in per line out in the beginning of the frame and lines in per line out in the middle of the frame multiplied by the horizontal blank and chunk granularity factor, altogether multiplied by the ratio of the source width to the line time, divided by the line buffer pixels per dispclk throughput, and multiplied by the display pipe throughput factor.*/
1657 : /*the horizontal blank and chunk granularity factor is the ratio of the line time divided by the line time minus half the horizontal blank and chunk time. it applies when the lines in per line out is not 2 or 4.*/
1658 : /*the dispclk required for scaler throughput is the product of the pixel rate and the scaling limits factor.*/
1659 : /*the dispclk required for total read request throughput is the product of the peak request-per-second bandwidth and the dispclk cycles per request, divided by the request efficiency.*/
1660 : /*for the dispclk required with ramping, instead of multiplying just the pipe throughput by the display pipe throughput factor, we multiply the scaler and pipe throughput by the ramping factor.*/
1661 : /*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
1662 : /*the scaling limits factor itself it also clamped to at least 1*/
1663 : /*if doing downscaling with the pre-downscaler enabled, the horizontal scale ratio should not be considered above (use "1")*/
1664 0 : data->downspread_factor = bw_add(bw_int_to_fixed(1), bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));
1665 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1666 0 : if (data->enable[i]) {
1667 0 : if (surface_type[i] == bw_def_graphics) {
1668 0 : switch (data->lb_bpc[i]) {
1669 : case 6:
1670 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1671 0 : break;
1672 : case 8:
1673 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1674 0 : break;
1675 : case 10:
1676 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1677 0 : break;
1678 : default:
1679 0 : data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1680 0 : break;
1681 : }
1682 0 : if (data->use_alpha[i] == 1) {
1683 0 : data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1684 : }
1685 : }
1686 : else {
1687 0 : switch (data->lb_bpc[i]) {
1688 : case 6:
1689 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1690 0 : break;
1691 : case 8:
1692 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1693 0 : break;
1694 : case 10:
1695 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1696 0 : break;
1697 : default:
1698 0 : data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency12_bit_per_component;
1699 0 : break;
1700 : }
1701 : }
1702 0 : if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1703 0 : data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1704 : }
1705 : else {
1706 0 : data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1707 : }
1708 0 : data->display_pipe_pixel_throughput = bw_div(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], bw_mul(data->lb_lines_in_per_line_out_in_middle_of_frame[i], data->horizontal_blank_and_chunk_granularity_factor[i])), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), dceip->lb_write_pixels_per_dispclk);
1709 0 : data->dispclk_required_without_ramping[i] = bw_mul(data->downspread_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), bw_mul(dceip->display_pipe_throughput_factor, data->display_pipe_pixel_throughput)));
1710 0 : data->dispclk_required_with_ramping[i] = bw_mul(dceip->dispclk_ramping_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), data->display_pipe_pixel_throughput));
1711 : }
1712 : }
1713 0 : data->total_dispclk_required_with_ramping = bw_int_to_fixed(0);
1714 0 : data->total_dispclk_required_without_ramping = bw_int_to_fixed(0);
1715 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1716 0 : if (data->enable[i]) {
1717 0 : if (bw_ltn(data->total_dispclk_required_with_ramping, data->dispclk_required_with_ramping[i])) {
1718 0 : data->total_dispclk_required_with_ramping = data->dispclk_required_with_ramping[i];
1719 : }
1720 0 : if (bw_ltn(data->total_dispclk_required_without_ramping, data->dispclk_required_without_ramping[i])) {
1721 0 : data->total_dispclk_required_without_ramping = data->dispclk_required_without_ramping[i];
1722 : }
1723 : }
1724 : }
1725 0 : data->total_read_request_bandwidth = bw_int_to_fixed(0);
1726 0 : data->total_write_request_bandwidth = bw_int_to_fixed(0);
1727 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1728 0 : if (data->enable[i]) {
1729 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1730 0 : data->total_read_request_bandwidth = bw_add(data->total_read_request_bandwidth, data->request_bandwidth[i]);
1731 : }
1732 : else {
1733 0 : data->total_write_request_bandwidth = bw_add(data->total_write_request_bandwidth, data->request_bandwidth[i]);
1734 : }
1735 : }
1736 : }
1737 0 : data->dispclk_required_for_total_read_request_bandwidth = bw_div(bw_mul(data->total_read_request_bandwidth, dceip->dispclk_per_request), dceip->request_efficiency);
1738 0 : data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1739 0 : data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1740 0 : if (data->cpuc_state_change_enable == bw_def_yes) {
1741 0 : data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1742 0 : data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1743 : }
1744 0 : if (data->cpup_state_change_enable == bw_def_yes) {
1745 0 : data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1746 0 : data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1747 : }
1748 0 : if (data->nbp_state_change_enable == bw_def_yes && data->increase_voltage_to_support_mclk_switch) {
1749 0 : data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1750 0 : data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1751 : }
1752 0 : if (bw_ltn(data->total_dispclk_required_with_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1753 0 : data->dispclk = data->total_dispclk_required_with_ramping_with_request_bandwidth;
1754 : }
1755 0 : else if (bw_ltn(data->total_dispclk_required_without_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1756 0 : data->dispclk = vbios->high_voltage_max_dispclk;
1757 : }
1758 : else {
1759 0 : data->dispclk = data->total_dispclk_required_without_ramping_with_request_bandwidth;
1760 : }
1761 : /* required core voltage*/
1762 : /* the core voltage required is low if sclk, yclk(pclk)and dispclk are within the low limits*/
1763 : /* otherwise, the core voltage required is medium if yclk (pclk) is within the low limit and sclk and dispclk are within the medium limit*/
1764 : /* otherwise, the core voltage required is high if the three clocks are within the high limits*/
1765 : /* otherwise, or if the mode is not supported, core voltage requirement is not applicable*/
1766 0 : if (pipe_check == bw_def_notok) {
1767 : voltage = bw_def_na;
1768 : }
1769 0 : else if (mode_check == bw_def_notok) {
1770 : voltage = bw_def_notok;
1771 : }
1772 0 : else if (bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_voltage_max_dispclk)) {
1773 : voltage = bw_def_0_72;
1774 : }
1775 0 : else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_voltage_max_dispclk)) {
1776 : voltage = bw_def_0_8;
1777 : }
1778 0 : else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->high_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_voltage_max_dispclk)) {
1779 0 : if ((data->nbp_state_change_enable == bw_def_no && nbp_state_change_enable_blank == bw_def_no)) {
1780 : voltage = bw_def_high_no_nbp_state_change;
1781 : }
1782 : else {
1783 0 : voltage = bw_def_0_9;
1784 : }
1785 : }
1786 : else {
1787 : voltage = bw_def_notok;
1788 : }
1789 0 : if (voltage == bw_def_0_72) {
1790 0 : data->max_phyclk = vbios->low_voltage_max_phyclk;
1791 : }
1792 0 : else if (voltage == bw_def_0_8) {
1793 0 : data->max_phyclk = vbios->mid_voltage_max_phyclk;
1794 : }
1795 : else {
1796 0 : data->max_phyclk = vbios->high_voltage_max_phyclk;
1797 : }
1798 : /*required blackout recovery time*/
1799 0 : data->blackout_recovery_time = bw_int_to_fixed(0);
1800 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1801 0 : if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
1802 0 : if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1803 0 : data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]));
1804 0 : if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
1805 0 : data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1806 : }
1807 : }
1808 : else {
1809 0 : data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]));
1810 0 : if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
1811 0 : data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1812 : }
1813 : }
1814 : }
1815 0 : }
1816 0 : /*sclk deep sleep*/
1817 : /*during self-refresh, sclk can be reduced to dispclk divided by the minimum pixels in the data fifo entry, with 15% margin, but shoudl not be set to less than the request bandwidth.*/
1818 : /*the data fifo entry is 16 pixels for the writeback, 64 bytes/bytes_per_pixel for the graphics, 16 pixels for the parallel rotation underlay,*/
1819 : /*and 16 bytes/bytes_per_pixel for the orthogonal rotation underlay.*/
1820 : /*in parallel mode (underlay pipe), the data read from the dmifv buffer is variable and based on the pixel depth (8bbp - 16 bytes, 16 bpp - 32 bytes, 32 bpp - 64 bytes)*/
1821 : /*in orthogonal mode (underlay pipe), the data read from the dmifv buffer is fixed at 16 bytes.*/
1822 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1823 0 : if (data->enable[i]) {
1824 0 : if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
1825 0 : data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1826 : }
1827 0 : else if (surface_type[i] == bw_def_graphics) {
1828 0 : data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(64), bw_int_to_fixed(data->bytes_per_pixel[i]));
1829 : }
1830 0 : else if (data->orthogonal_rotation[i] == 0) {
1831 0 : data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1832 : }
1833 : else {
1834 0 : data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(16), bw_int_to_fixed(data->bytes_per_pixel[i]));
1835 : }
1836 : }
1837 : }
1838 0 : data->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);
1839 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1840 0 : if (data->enable[i]) {
1841 0 : if (bw_mtn(data->min_pixels_per_data_fifo_entry, data->pixels_per_data_fifo_entry[i])) {
1842 0 : data->min_pixels_per_data_fifo_entry = data->pixels_per_data_fifo_entry[i];
1843 : }
1844 : }
1845 : }
1846 0 : data->sclk_deep_sleep = bw_max2(bw_div(bw_mul(data->dispclk, bw_frc_to_fixed(115, 100)), data->min_pixels_per_data_fifo_entry), data->total_read_request_bandwidth);
1847 : /*urgent, stutter and nb-p_state watermark*/
1848 : /*the urgent watermark is the maximum of the urgent trip time plus the pixel transfer time, the urgent trip times to get data for the first pixel, and the urgent trip times to get data for the last pixel.*/
1849 : /*the stutter exit watermark is the self refresh exit time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel. it does not apply to the writeback.*/
1850 : /*the nb p-state change watermark is the dram speed/p-state change time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.*/
1851 : /*the pixel transfer time is the maximum of the time to transfer the source pixels required for the first output pixel, and the time to transfer the pixels for the last output pixel minus the active line time.*/
1852 : /*blackout_duration is added to the urgent watermark*/
1853 0 : data->chunk_request_time = bw_int_to_fixed(0);
1854 0 : data->cursor_request_time = bw_int_to_fixed(0);
1855 : /*compute total time to request one chunk from each active display pipe*/
1856 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1857 0 : if (data->enable[i]) {
1858 0 : data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
1859 : }
1860 : }
1861 : /*compute total time to request cursor data*/
1862 0 : data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level]))));
1863 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1864 0 : if (data->enable[i]) {
1865 0 : data->line_source_pixels_transfer_time = bw_max2(bw_div(bw_div(data->src_pixels_for_first_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), bw_sub(bw_div(bw_div(data->src_pixels_for_last_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), data->active_time[i]));
1866 0 : if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1867 0 : data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1868 0 : data->stutter_exit_watermark[i] = bw_add(bw_sub(vbios->stutter_self_refresh_exit_latency, data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1869 0 : data->stutter_entry_watermark[i] = bw_add(bw_sub(bw_add(vbios->stutter_self_refresh_exit_latency, vbios->stutter_self_refresh_entry_latency), data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1870 : /*unconditionally remove black out time from the nb p_state watermark*/
1871 0 : if (data->display_pstate_change_enable[i] == 1) {
1872 0 : data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1873 : }
1874 : else {
1875 : /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1876 0 : data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1877 : }
1878 : }
1879 : else {
1880 0 : data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1881 0 : data->stutter_exit_watermark[i] = bw_int_to_fixed(0);
1882 0 : data->stutter_entry_watermark[i] = bw_int_to_fixed(0);
1883 0 : if (data->display_pstate_change_enable[i] == 1) {
1884 0 : data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1885 : }
1886 : else {
1887 : /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1888 0 : data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1889 : }
1890 : }
1891 : }
1892 : }
1893 : /*stutter mode enable*/
1894 : /*in the multi-display case the stutter exit or entry watermark cannot exceed the minimum latency hiding capabilities of the*/
1895 : /*display pipe.*/
1896 0 : data->stutter_mode_enable = data->cpuc_state_change_enable;
1897 0 : if (data->number_of_displays > 1) {
1898 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1899 0 : if (data->enable[i]) {
1900 0 : if ((bw_mtn(data->stutter_exit_watermark[i], data->minimum_latency_hiding[i]) || bw_mtn(data->stutter_entry_watermark[i], data->minimum_latency_hiding[i]))) {
1901 0 : data->stutter_mode_enable = bw_def_no;
1902 : }
1903 : }
1904 : }
1905 : }
1906 : /*performance metrics*/
1907 : /* display read access efficiency (%)*/
1908 : /* display write back access efficiency (%)*/
1909 : /* stutter efficiency (%)*/
1910 : /* extra underlay pitch recommended for efficiency (pixels)*/
1911 : /* immediate flip time (us)*/
1912 : /* latency for other clients due to urgent display read (us)*/
1913 : /* latency for other clients due to urgent display write (us)*/
1914 : /* average bandwidth consumed by display (no compression) (gb/s)*/
1915 : /* required dram bandwidth (gb/s)*/
1916 : /* required sclk (m_hz)*/
1917 : /* required rd urgent latency (us)*/
1918 : /* nb p-state change margin (us)*/
1919 : /*dmif and mcifwr dram access efficiency*/
1920 : /*is the ratio between the ideal dram access time (which is the data buffer size in memory divided by the dram bandwidth), and the actual time which is the total page close-open time. but it cannot exceed the dram efficiency provided by the memory subsystem*/
1921 0 : data->dmifdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_reads_required_dram_access_data, data->dram_bandwidth), data->dmif_total_page_close_open_time), bw_int_to_fixed(1));
1922 0 : if (bw_mtn(data->total_display_writes_required_dram_access_data, bw_int_to_fixed(0))) {
1923 0 : data->mcifwrdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_writes_required_dram_access_data, data->dram_bandwidth), data->mcifwr_total_page_close_open_time), bw_int_to_fixed(1));
1924 : }
1925 : else {
1926 0 : data->mcifwrdram_access_efficiency = bw_int_to_fixed(0);
1927 : }
1928 : /*stutter efficiency*/
1929 : /*the stutter efficiency is the frame-average time in self-refresh divided by the frame-average stutter cycle duration. only applies if the display write-back is not enabled.*/
1930 : /*the frame-average stutter cycle used is the minimum for all pipes of the frame-average data buffer size in time, times the compression rate*/
1931 : /*the frame-average time in self-refresh is the stutter cycle minus the self refresh exit latency and the burst time*/
1932 : /*the stutter cycle is the dmif buffer size reduced by the excess of the stutter exit watermark over the lb size in time.*/
1933 : /*the burst time is the data needed during the stutter cycle divided by the available bandwidth*/
1934 : /*compute the time read all the data from the dmif buffer to the lb (dram refresh period)*/
1935 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1936 0 : if (data->enable[i]) {
1937 0 : data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));
1938 0 : data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]);
1939 : }
1940 : }
1941 0 : data->min_stutter_refresh_duration = bw_int_to_fixed(9999);
1942 0 : data->total_stutter_dmif_buffer_size = 0;
1943 0 : data->total_bytes_requested = 0;
1944 0 : data->min_stutter_dmif_buffer_size = 9999;
1945 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1946 0 : if (data->enable[i]) {
1947 0 : if (bw_mtn(data->min_stutter_refresh_duration, data->stutter_refresh_duration[i])) {
1948 0 : data->min_stutter_refresh_duration = data->stutter_refresh_duration[i];
1949 0 : data->total_bytes_requested = bw_fixed_to_int(bw_add(bw_int_to_fixed(data->total_bytes_requested), (bw_mul(bw_mul(data->source_height_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[i]), bw_int_to_fixed(data->bytes_per_pixel[i])))));
1950 0 : data->min_stutter_dmif_buffer_size = bw_fixed_to_int(data->stutter_dmif_buffer_size[i]);
1951 : }
1952 0 : data->total_stutter_dmif_buffer_size = bw_fixed_to_int(bw_add(data->stutter_dmif_buffer_size[i], bw_int_to_fixed(data->total_stutter_dmif_buffer_size)));
1953 : }
1954 : }
1955 0 : data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_mul(sclk[data->sclk_level], vbios->data_return_bus_width));
1956 0 : data->num_stutter_bursts = data->total_bytes_requested / data->min_stutter_dmif_buffer_size;
1957 0 : data->total_stutter_cycle_duration = bw_add(bw_add(data->min_stutter_refresh_duration, vbios->stutter_self_refresh_exit_latency), data->stutter_burst_time);
1958 0 : data->time_in_self_refresh = data->min_stutter_refresh_duration;
1959 0 : if (data->d1_display_write_back_dwb_enable == 1) {
1960 0 : data->stutter_efficiency = bw_int_to_fixed(0);
1961 : }
1962 0 : else if (bw_ltn(data->time_in_self_refresh, bw_int_to_fixed(0))) {
1963 0 : data->stutter_efficiency = bw_int_to_fixed(0);
1964 : }
1965 : else {
1966 : /*compute stutter efficiency assuming 60 hz refresh rate*/
1967 0 : data->stutter_efficiency = bw_max2(bw_int_to_fixed(0), bw_mul((bw_sub(bw_int_to_fixed(1), (bw_div(bw_mul((bw_add(vbios->stutter_self_refresh_exit_latency, data->stutter_burst_time)), bw_int_to_fixed(data->num_stutter_bursts)), bw_frc_to_fixed(166666667, 10000))))), bw_int_to_fixed(100)));
1968 : }
1969 : /*immediate flip time*/
1970 : /*if scatter gather is enabled, the immediate flip takes a number of urgent memory trips equivalent to the pte requests in a row divided by the pte request limit.*/
1971 : /*otherwise, it may take just one urgenr memory trip*/
1972 0 : data->worst_number_of_trips_to_memory = bw_int_to_fixed(1);
1973 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1974 0 : if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
1975 0 : data->number_of_trips_to_memory_for_getting_apte_row[i] = bw_ceil2(bw_div(data->scatter_gather_pte_requests_in_row[i], data->scatter_gather_pte_request_limit[i]), bw_int_to_fixed(1));
1976 0 : if (bw_ltn(data->worst_number_of_trips_to_memory, data->number_of_trips_to_memory_for_getting_apte_row[i])) {
1977 0 : data->worst_number_of_trips_to_memory = data->number_of_trips_to_memory_for_getting_apte_row[i];
1978 : }
1979 : }
1980 : }
1981 0 : data->immediate_flip_time = bw_mul(data->worst_number_of_trips_to_memory, data->total_dmifmc_urgent_latency);
1982 : /*worst latency for other clients*/
1983 : /*it is the urgent latency plus the urgent burst time*/
1984 0 : data->latency_for_non_dmif_clients = bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]);
1985 0 : if (data->d1_display_write_back_dwb_enable == 1) {
1986 0 : data->latency_for_non_mcifwr_clients = bw_add(vbios->mcifwrmc_urgent_latency, dceip->mcifwr_all_surfaces_burst_time);
1987 : }
1988 : else {
1989 0 : data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
1990 : }
1991 : /*dmif mc urgent latency supported in high sclk and yclk*/
1992 0 : data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_burst_time[high][s_high])), data->total_dmifmc_urgent_trips);
1993 : /*dram speed/p-state change margin*/
1994 : /*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
1995 0 : data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1996 0 : data->nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1997 0 : for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1998 0 : if (data->enable[i]) {
1999 0 : data->nbp_state_dram_speed_change_latency_supported = bw_min2(data->nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(data->maximum_latency_hiding_with_cursor[i], data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
2000 0 : data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
2001 : }
2002 : }
2003 : /*sclk required vs urgent latency*/
2004 0 : for (i = 1; i <= 5; i++) {
2005 0 : data->display_reads_time_for_data_transfer_and_urgent_latency = bw_sub(data->min_read_buffer_size_in_time, bw_mul(data->total_dmifmc_urgent_trips, bw_int_to_fixed(i)));
2006 0 : if (pipe_check == bw_def_ok && (bw_mtn(data->display_reads_time_for_data_transfer_and_urgent_latency, data->dmif_total_page_close_open_time))) {
2007 0 : data->dmif_required_sclk_for_urgent_latency[i] = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer_and_urgent_latency), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
2008 : }
2009 : else {
2010 0 : data->dmif_required_sclk_for_urgent_latency[i] = bw_int_to_fixed(bw_def_na);
2011 : }
2012 : }
2013 : /*output link bit per pixel supported*/
2014 0 : for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
2015 0 : data->output_bpphdmi[k] = bw_def_na;
2016 0 : data->output_bppdp4_lane_hbr[k] = bw_def_na;
2017 0 : data->output_bppdp4_lane_hbr2[k] = bw_def_na;
2018 0 : data->output_bppdp4_lane_hbr3[k] = bw_def_na;
2019 0 : if (data->enable[k]) {
2020 0 : data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
2021 0 : if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {
2022 0 : data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2023 : }
2024 0 : if (bw_meq(data->max_phyclk, bw_int_to_fixed(540))) {
2025 0 : data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2026 : }
2027 0 : if (bw_meq(data->max_phyclk, bw_int_to_fixed(810))) {
2028 0 : data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2029 : }
2030 : }
2031 : }
2032 :
2033 0 : kfree(surface_type);
2034 : free_tiling_mode:
2035 0 : kfree(tiling_mode);
2036 : free_sclk:
2037 0 : kfree(sclk);
2038 : free_yclk:
2039 0 : kfree(yclk);
2040 : }
2041 :
2042 : /*******************************************************************************
2043 : * Public functions
2044 : ******************************************************************************/
2045 0 : void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
2046 : struct bw_calcs_vbios *bw_vbios,
2047 : struct hw_asic_id asic_id)
2048 : {
2049 : struct bw_calcs_dceip *dceip;
2050 : struct bw_calcs_vbios *vbios;
2051 :
2052 0 : enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
2053 :
2054 0 : dceip = kzalloc(sizeof(*dceip), GFP_KERNEL);
2055 0 : if (!dceip)
2056 : return;
2057 :
2058 0 : vbios = kzalloc(sizeof(*vbios), GFP_KERNEL);
2059 0 : if (!vbios) {
2060 0 : kfree(dceip);
2061 0 : return;
2062 : }
2063 :
2064 0 : dceip->version = version;
2065 :
2066 0 : switch (version) {
2067 : case BW_CALCS_VERSION_CARRIZO:
2068 0 : vbios->memory_type = bw_def_gddr5;
2069 0 : vbios->dram_channel_width_in_bits = 64;
2070 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2071 0 : vbios->number_of_dram_banks = 8;
2072 0 : vbios->high_yclk = bw_int_to_fixed(1600);
2073 0 : vbios->mid_yclk = bw_int_to_fixed(1600);
2074 0 : vbios->low_yclk = bw_frc_to_fixed(66666, 100);
2075 0 : vbios->low_sclk = bw_int_to_fixed(200);
2076 0 : vbios->mid1_sclk = bw_int_to_fixed(300);
2077 0 : vbios->mid2_sclk = bw_int_to_fixed(300);
2078 0 : vbios->mid3_sclk = bw_int_to_fixed(300);
2079 0 : vbios->mid4_sclk = bw_int_to_fixed(300);
2080 0 : vbios->mid5_sclk = bw_int_to_fixed(300);
2081 0 : vbios->mid6_sclk = bw_int_to_fixed(300);
2082 0 : vbios->high_sclk = bw_frc_to_fixed(62609, 100);
2083 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(352);
2084 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(467);
2085 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(643);
2086 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2087 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2088 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2089 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2090 0 : vbios->trc = bw_int_to_fixed(50);
2091 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(4);
2092 0 : vbios->stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
2093 0 : vbios->stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2094 0 : vbios->nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
2095 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2096 0 : vbios->scatter_gather_enable = true;
2097 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2098 0 : vbios->cursor_width = 32;
2099 0 : vbios->average_compression_rate = 4;
2100 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2101 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2102 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2103 :
2104 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2105 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2106 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2107 0 : dceip->large_cursor = false;
2108 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(768);
2109 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = false;
2110 0 : dceip->cursor_max_outstanding_group_num = 1;
2111 0 : dceip->lines_interleaved_into_lb = 2;
2112 0 : dceip->chunk_width = 256;
2113 0 : dceip->number_of_graphics_pipes = 3;
2114 0 : dceip->number_of_underlay_pipes = 1;
2115 0 : dceip->low_power_tiling_mode = 0;
2116 0 : dceip->display_write_back_supported = false;
2117 0 : dceip->argb_compression_support = false;
2118 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2119 : bw_frc_to_fixed(35556, 10000);
2120 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2121 : bw_frc_to_fixed(34286, 10000);
2122 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2123 : bw_frc_to_fixed(32, 10);
2124 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2125 : bw_int_to_fixed(3);
2126 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2127 : bw_frc_to_fixed(35, 10);
2128 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2129 : bw_frc_to_fixed(34286, 10000);
2130 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2131 : bw_frc_to_fixed(32, 10);
2132 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2133 : bw_int_to_fixed(3);
2134 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2135 0 : dceip->max_dmif_buffer_allocated = 2;
2136 0 : dceip->graphics_dmif_size = 12288;
2137 0 : dceip->underlay_luma_dmif_size = 19456;
2138 0 : dceip->underlay_chroma_dmif_size = 23552;
2139 0 : dceip->pre_downscaler_enabled = true;
2140 0 : dceip->underlay_downscale_prefetch_enabled = true;
2141 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2142 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(82176);
2143 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = false;
2144 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2145 : bw_int_to_fixed(0);
2146 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2147 : 82176);
2148 0 : dceip->underlay420_chroma_lb_size_per_component =
2149 : bw_int_to_fixed(164352);
2150 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2151 : 82176);
2152 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2153 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2154 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2155 : bw_int_to_fixed(1920);
2156 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2157 : bw_int_to_fixed(1080);
2158 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2159 : bw_frc_to_fixed(3, 10);
2160 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2161 : bw_int_to_fixed(25);
2162 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2163 : 2);
2164 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2165 : bw_int_to_fixed(128);
2166 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2167 0 : dceip->linear_mode_line_request_alternation_slice =
2168 : bw_int_to_fixed(64);
2169 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2170 : 32;
2171 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2172 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2173 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2174 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2175 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2176 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2177 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2178 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
2179 0 : break;
2180 : case BW_CALCS_VERSION_POLARIS10:
2181 : /* TODO: Treat VEGAM the same as P10 for now
2182 : * Need to tune the para for VEGAM if needed */
2183 : case BW_CALCS_VERSION_VEGAM:
2184 0 : vbios->memory_type = bw_def_gddr5;
2185 0 : vbios->dram_channel_width_in_bits = 32;
2186 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2187 0 : vbios->number_of_dram_banks = 8;
2188 0 : vbios->high_yclk = bw_int_to_fixed(6000);
2189 0 : vbios->mid_yclk = bw_int_to_fixed(3200);
2190 0 : vbios->low_yclk = bw_int_to_fixed(1000);
2191 0 : vbios->low_sclk = bw_int_to_fixed(300);
2192 0 : vbios->mid1_sclk = bw_int_to_fixed(400);
2193 0 : vbios->mid2_sclk = bw_int_to_fixed(500);
2194 0 : vbios->mid3_sclk = bw_int_to_fixed(600);
2195 0 : vbios->mid4_sclk = bw_int_to_fixed(700);
2196 0 : vbios->mid5_sclk = bw_int_to_fixed(800);
2197 0 : vbios->mid6_sclk = bw_int_to_fixed(974);
2198 0 : vbios->high_sclk = bw_int_to_fixed(1154);
2199 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(459);
2200 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(654);
2201 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(1108);
2202 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2203 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2204 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2205 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2206 0 : vbios->trc = bw_int_to_fixed(48);
2207 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(3);
2208 0 : vbios->stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2209 0 : vbios->stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2210 0 : vbios->nbp_state_change_latency = bw_int_to_fixed(45);
2211 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2212 0 : vbios->scatter_gather_enable = true;
2213 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2214 0 : vbios->cursor_width = 32;
2215 0 : vbios->average_compression_rate = 4;
2216 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2217 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2218 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2219 :
2220 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2221 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2222 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2223 0 : dceip->large_cursor = false;
2224 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(768);
2225 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = false;
2226 0 : dceip->cursor_max_outstanding_group_num = 1;
2227 0 : dceip->lines_interleaved_into_lb = 2;
2228 0 : dceip->chunk_width = 256;
2229 0 : dceip->number_of_graphics_pipes = 6;
2230 0 : dceip->number_of_underlay_pipes = 0;
2231 0 : dceip->low_power_tiling_mode = 0;
2232 0 : dceip->display_write_back_supported = false;
2233 0 : dceip->argb_compression_support = true;
2234 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2235 : bw_frc_to_fixed(35556, 10000);
2236 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2237 : bw_frc_to_fixed(34286, 10000);
2238 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2239 : bw_frc_to_fixed(32, 10);
2240 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2241 : bw_int_to_fixed(3);
2242 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2243 : bw_frc_to_fixed(35, 10);
2244 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2245 : bw_frc_to_fixed(34286, 10000);
2246 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2247 : bw_frc_to_fixed(32, 10);
2248 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2249 : bw_int_to_fixed(3);
2250 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2251 0 : dceip->max_dmif_buffer_allocated = 4;
2252 0 : dceip->graphics_dmif_size = 12288;
2253 0 : dceip->underlay_luma_dmif_size = 19456;
2254 0 : dceip->underlay_chroma_dmif_size = 23552;
2255 0 : dceip->pre_downscaler_enabled = true;
2256 0 : dceip->underlay_downscale_prefetch_enabled = true;
2257 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2258 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(245952);
2259 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;
2260 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2261 : bw_int_to_fixed(1);
2262 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2263 : 82176);
2264 0 : dceip->underlay420_chroma_lb_size_per_component =
2265 : bw_int_to_fixed(164352);
2266 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2267 : 82176);
2268 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2269 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2270 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2271 : bw_int_to_fixed(1920);
2272 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2273 : bw_int_to_fixed(1080);
2274 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2275 : bw_frc_to_fixed(3, 10);
2276 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2277 : bw_int_to_fixed(25);
2278 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2279 : 2);
2280 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2281 : bw_int_to_fixed(128);
2282 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2283 0 : dceip->linear_mode_line_request_alternation_slice =
2284 : bw_int_to_fixed(64);
2285 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2286 : 32;
2287 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2288 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2289 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2290 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2291 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2292 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2293 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2294 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2295 0 : break;
2296 : case BW_CALCS_VERSION_POLARIS11:
2297 0 : vbios->memory_type = bw_def_gddr5;
2298 0 : vbios->dram_channel_width_in_bits = 32;
2299 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2300 0 : vbios->number_of_dram_banks = 8;
2301 0 : vbios->high_yclk = bw_int_to_fixed(6000);
2302 0 : vbios->mid_yclk = bw_int_to_fixed(3200);
2303 0 : vbios->low_yclk = bw_int_to_fixed(1000);
2304 0 : vbios->low_sclk = bw_int_to_fixed(300);
2305 0 : vbios->mid1_sclk = bw_int_to_fixed(400);
2306 0 : vbios->mid2_sclk = bw_int_to_fixed(500);
2307 0 : vbios->mid3_sclk = bw_int_to_fixed(600);
2308 0 : vbios->mid4_sclk = bw_int_to_fixed(700);
2309 0 : vbios->mid5_sclk = bw_int_to_fixed(800);
2310 0 : vbios->mid6_sclk = bw_int_to_fixed(974);
2311 0 : vbios->high_sclk = bw_int_to_fixed(1154);
2312 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(459);
2313 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(654);
2314 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(1108);
2315 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2316 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2317 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2318 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2319 0 : vbios->trc = bw_int_to_fixed(48);
2320 0 : if (vbios->number_of_dram_channels == 2) // 64-bit
2321 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(4);
2322 : else
2323 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(3);
2324 0 : vbios->stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2325 0 : vbios->stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2326 0 : vbios->nbp_state_change_latency = bw_int_to_fixed(45);
2327 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2328 0 : vbios->scatter_gather_enable = true;
2329 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2330 0 : vbios->cursor_width = 32;
2331 0 : vbios->average_compression_rate = 4;
2332 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2333 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2334 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2335 :
2336 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2337 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2338 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2339 0 : dceip->large_cursor = false;
2340 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(768);
2341 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = false;
2342 0 : dceip->cursor_max_outstanding_group_num = 1;
2343 0 : dceip->lines_interleaved_into_lb = 2;
2344 0 : dceip->chunk_width = 256;
2345 0 : dceip->number_of_graphics_pipes = 5;
2346 0 : dceip->number_of_underlay_pipes = 0;
2347 0 : dceip->low_power_tiling_mode = 0;
2348 0 : dceip->display_write_back_supported = false;
2349 0 : dceip->argb_compression_support = true;
2350 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2351 : bw_frc_to_fixed(35556, 10000);
2352 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2353 : bw_frc_to_fixed(34286, 10000);
2354 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2355 : bw_frc_to_fixed(32, 10);
2356 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2357 : bw_int_to_fixed(3);
2358 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2359 : bw_frc_to_fixed(35, 10);
2360 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2361 : bw_frc_to_fixed(34286, 10000);
2362 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2363 : bw_frc_to_fixed(32, 10);
2364 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2365 : bw_int_to_fixed(3);
2366 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2367 0 : dceip->max_dmif_buffer_allocated = 4;
2368 0 : dceip->graphics_dmif_size = 12288;
2369 0 : dceip->underlay_luma_dmif_size = 19456;
2370 0 : dceip->underlay_chroma_dmif_size = 23552;
2371 0 : dceip->pre_downscaler_enabled = true;
2372 0 : dceip->underlay_downscale_prefetch_enabled = true;
2373 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2374 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(245952);
2375 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;
2376 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2377 : bw_int_to_fixed(1);
2378 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2379 : 82176);
2380 0 : dceip->underlay420_chroma_lb_size_per_component =
2381 : bw_int_to_fixed(164352);
2382 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2383 : 82176);
2384 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2385 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2386 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2387 : bw_int_to_fixed(1920);
2388 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2389 : bw_int_to_fixed(1080);
2390 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2391 : bw_frc_to_fixed(3, 10);
2392 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2393 : bw_int_to_fixed(25);
2394 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2395 : 2);
2396 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2397 : bw_int_to_fixed(128);
2398 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2399 0 : dceip->linear_mode_line_request_alternation_slice =
2400 : bw_int_to_fixed(64);
2401 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2402 : 32;
2403 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2404 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2405 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2406 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2407 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2408 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2409 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2410 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2411 0 : break;
2412 : case BW_CALCS_VERSION_POLARIS12:
2413 0 : vbios->memory_type = bw_def_gddr5;
2414 0 : vbios->dram_channel_width_in_bits = 32;
2415 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2416 0 : vbios->number_of_dram_banks = 8;
2417 0 : vbios->high_yclk = bw_int_to_fixed(6000);
2418 0 : vbios->mid_yclk = bw_int_to_fixed(3200);
2419 0 : vbios->low_yclk = bw_int_to_fixed(1000);
2420 0 : vbios->low_sclk = bw_int_to_fixed(678);
2421 0 : vbios->mid1_sclk = bw_int_to_fixed(864);
2422 0 : vbios->mid2_sclk = bw_int_to_fixed(900);
2423 0 : vbios->mid3_sclk = bw_int_to_fixed(920);
2424 0 : vbios->mid4_sclk = bw_int_to_fixed(940);
2425 0 : vbios->mid5_sclk = bw_int_to_fixed(960);
2426 0 : vbios->mid6_sclk = bw_int_to_fixed(980);
2427 0 : vbios->high_sclk = bw_int_to_fixed(1049);
2428 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(459);
2429 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(654);
2430 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(1108);
2431 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2432 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2433 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2434 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2435 0 : vbios->trc = bw_int_to_fixed(48);
2436 0 : if (vbios->number_of_dram_channels == 2) // 64-bit
2437 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(4);
2438 : else
2439 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(3);
2440 0 : vbios->stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2441 0 : vbios->stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2442 0 : vbios->nbp_state_change_latency = bw_int_to_fixed(250);
2443 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2444 0 : vbios->scatter_gather_enable = false;
2445 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2446 0 : vbios->cursor_width = 32;
2447 0 : vbios->average_compression_rate = 4;
2448 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2449 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2450 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2451 :
2452 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2453 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2454 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2455 0 : dceip->large_cursor = false;
2456 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(768);
2457 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = false;
2458 0 : dceip->cursor_max_outstanding_group_num = 1;
2459 0 : dceip->lines_interleaved_into_lb = 2;
2460 0 : dceip->chunk_width = 256;
2461 0 : dceip->number_of_graphics_pipes = 5;
2462 0 : dceip->number_of_underlay_pipes = 0;
2463 0 : dceip->low_power_tiling_mode = 0;
2464 0 : dceip->display_write_back_supported = true;
2465 0 : dceip->argb_compression_support = true;
2466 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2467 : bw_frc_to_fixed(35556, 10000);
2468 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2469 : bw_frc_to_fixed(34286, 10000);
2470 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2471 : bw_frc_to_fixed(32, 10);
2472 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2473 : bw_int_to_fixed(3);
2474 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2475 : bw_frc_to_fixed(35, 10);
2476 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2477 : bw_frc_to_fixed(34286, 10000);
2478 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2479 : bw_frc_to_fixed(32, 10);
2480 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2481 : bw_int_to_fixed(3);
2482 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2483 0 : dceip->max_dmif_buffer_allocated = 4;
2484 0 : dceip->graphics_dmif_size = 12288;
2485 0 : dceip->underlay_luma_dmif_size = 19456;
2486 0 : dceip->underlay_chroma_dmif_size = 23552;
2487 0 : dceip->pre_downscaler_enabled = true;
2488 0 : dceip->underlay_downscale_prefetch_enabled = true;
2489 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2490 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(245952);
2491 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;
2492 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2493 : bw_int_to_fixed(1);
2494 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2495 : 82176);
2496 0 : dceip->underlay420_chroma_lb_size_per_component =
2497 : bw_int_to_fixed(164352);
2498 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2499 : 82176);
2500 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2501 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2502 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2503 : bw_int_to_fixed(1920);
2504 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2505 : bw_int_to_fixed(1080);
2506 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2507 : bw_frc_to_fixed(3, 10);
2508 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2509 : bw_int_to_fixed(25);
2510 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2511 : 2);
2512 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2513 : bw_int_to_fixed(128);
2514 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2515 0 : dceip->linear_mode_line_request_alternation_slice =
2516 : bw_int_to_fixed(64);
2517 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2518 : 32;
2519 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2520 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2521 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2522 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2523 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2524 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2525 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2526 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2527 0 : break;
2528 : case BW_CALCS_VERSION_STONEY:
2529 0 : vbios->memory_type = bw_def_gddr5;
2530 0 : vbios->dram_channel_width_in_bits = 64;
2531 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2532 0 : vbios->number_of_dram_banks = 8;
2533 0 : vbios->high_yclk = bw_int_to_fixed(1866);
2534 0 : vbios->mid_yclk = bw_int_to_fixed(1866);
2535 0 : vbios->low_yclk = bw_int_to_fixed(1333);
2536 0 : vbios->low_sclk = bw_int_to_fixed(200);
2537 0 : vbios->mid1_sclk = bw_int_to_fixed(600);
2538 0 : vbios->mid2_sclk = bw_int_to_fixed(600);
2539 0 : vbios->mid3_sclk = bw_int_to_fixed(600);
2540 0 : vbios->mid4_sclk = bw_int_to_fixed(600);
2541 0 : vbios->mid5_sclk = bw_int_to_fixed(600);
2542 0 : vbios->mid6_sclk = bw_int_to_fixed(600);
2543 0 : vbios->high_sclk = bw_int_to_fixed(800);
2544 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(352);
2545 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(467);
2546 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(643);
2547 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2548 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2549 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2550 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2551 0 : vbios->trc = bw_int_to_fixed(50);
2552 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(4);
2553 0 : vbios->stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
2554 0 : vbios->stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2555 0 : vbios->nbp_state_change_latency = bw_frc_to_fixed(2008, 100);
2556 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2557 0 : vbios->scatter_gather_enable = true;
2558 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2559 0 : vbios->cursor_width = 32;
2560 0 : vbios->average_compression_rate = 4;
2561 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2562 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2563 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2564 :
2565 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2566 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2567 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2568 0 : dceip->large_cursor = false;
2569 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(768);
2570 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = false;
2571 0 : dceip->cursor_max_outstanding_group_num = 1;
2572 0 : dceip->lines_interleaved_into_lb = 2;
2573 0 : dceip->chunk_width = 256;
2574 0 : dceip->number_of_graphics_pipes = 2;
2575 0 : dceip->number_of_underlay_pipes = 1;
2576 0 : dceip->low_power_tiling_mode = 0;
2577 0 : dceip->display_write_back_supported = false;
2578 0 : dceip->argb_compression_support = true;
2579 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2580 : bw_frc_to_fixed(35556, 10000);
2581 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2582 : bw_frc_to_fixed(34286, 10000);
2583 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2584 : bw_frc_to_fixed(32, 10);
2585 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2586 : bw_int_to_fixed(3);
2587 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2588 : bw_frc_to_fixed(35, 10);
2589 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2590 : bw_frc_to_fixed(34286, 10000);
2591 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2592 : bw_frc_to_fixed(32, 10);
2593 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2594 : bw_int_to_fixed(3);
2595 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2596 0 : dceip->max_dmif_buffer_allocated = 2;
2597 0 : dceip->graphics_dmif_size = 12288;
2598 0 : dceip->underlay_luma_dmif_size = 19456;
2599 0 : dceip->underlay_chroma_dmif_size = 23552;
2600 0 : dceip->pre_downscaler_enabled = true;
2601 0 : dceip->underlay_downscale_prefetch_enabled = true;
2602 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2603 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(82176);
2604 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = false;
2605 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2606 : bw_int_to_fixed(0);
2607 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2608 : 82176);
2609 0 : dceip->underlay420_chroma_lb_size_per_component =
2610 : bw_int_to_fixed(164352);
2611 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2612 : 82176);
2613 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2614 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2615 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2616 : bw_int_to_fixed(1920);
2617 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2618 : bw_int_to_fixed(1080);
2619 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2620 : bw_frc_to_fixed(3, 10);
2621 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2622 : bw_int_to_fixed(25);
2623 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2624 : 2);
2625 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2626 : bw_int_to_fixed(128);
2627 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2628 0 : dceip->linear_mode_line_request_alternation_slice =
2629 : bw_int_to_fixed(64);
2630 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2631 : 32;
2632 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2633 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2634 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2635 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2636 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2637 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2638 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2639 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2640 0 : break;
2641 : case BW_CALCS_VERSION_VEGA10:
2642 0 : vbios->memory_type = bw_def_hbm;
2643 0 : vbios->dram_channel_width_in_bits = 128;
2644 0 : vbios->number_of_dram_channels = asic_id.vram_width / vbios->dram_channel_width_in_bits;
2645 0 : vbios->number_of_dram_banks = 16;
2646 0 : vbios->high_yclk = bw_int_to_fixed(2400);
2647 0 : vbios->mid_yclk = bw_int_to_fixed(1700);
2648 0 : vbios->low_yclk = bw_int_to_fixed(1000);
2649 0 : vbios->low_sclk = bw_int_to_fixed(300);
2650 0 : vbios->mid1_sclk = bw_int_to_fixed(350);
2651 0 : vbios->mid2_sclk = bw_int_to_fixed(400);
2652 0 : vbios->mid3_sclk = bw_int_to_fixed(500);
2653 0 : vbios->mid4_sclk = bw_int_to_fixed(600);
2654 0 : vbios->mid5_sclk = bw_int_to_fixed(700);
2655 0 : vbios->mid6_sclk = bw_int_to_fixed(760);
2656 0 : vbios->high_sclk = bw_int_to_fixed(776);
2657 0 : vbios->low_voltage_max_dispclk = bw_int_to_fixed(460);
2658 0 : vbios->mid_voltage_max_dispclk = bw_int_to_fixed(670);
2659 0 : vbios->high_voltage_max_dispclk = bw_int_to_fixed(1133);
2660 0 : vbios->low_voltage_max_phyclk = bw_int_to_fixed(540);
2661 0 : vbios->mid_voltage_max_phyclk = bw_int_to_fixed(810);
2662 0 : vbios->high_voltage_max_phyclk = bw_int_to_fixed(810);
2663 0 : vbios->data_return_bus_width = bw_int_to_fixed(32);
2664 0 : vbios->trc = bw_int_to_fixed(48);
2665 0 : vbios->dmifmc_urgent_latency = bw_int_to_fixed(3);
2666 0 : vbios->stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10);
2667 0 : vbios->stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10);
2668 0 : vbios->nbp_state_change_latency = bw_int_to_fixed(39);
2669 0 : vbios->mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2670 0 : vbios->scatter_gather_enable = false;
2671 0 : vbios->down_spread_percentage = bw_frc_to_fixed(5, 10);
2672 0 : vbios->cursor_width = 32;
2673 0 : vbios->average_compression_rate = 4;
2674 0 : vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8;
2675 0 : vbios->blackout_duration = bw_int_to_fixed(0); /* us */
2676 0 : vbios->maximum_blackout_recovery_time = bw_int_to_fixed(0);
2677 :
2678 0 : dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2679 0 : dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2680 0 : dceip->percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2681 0 : dceip->large_cursor = false;
2682 0 : dceip->dmif_request_buffer_size = bw_int_to_fixed(2304);
2683 0 : dceip->dmif_pipe_en_fbc_chunk_tracker = true;
2684 0 : dceip->cursor_max_outstanding_group_num = 1;
2685 0 : dceip->lines_interleaved_into_lb = 2;
2686 0 : dceip->chunk_width = 256;
2687 0 : dceip->number_of_graphics_pipes = 6;
2688 0 : dceip->number_of_underlay_pipes = 0;
2689 0 : dceip->low_power_tiling_mode = 0;
2690 0 : dceip->display_write_back_supported = true;
2691 0 : dceip->argb_compression_support = true;
2692 0 : dceip->underlay_vscaler_efficiency6_bit_per_component =
2693 : bw_frc_to_fixed(35556, 10000);
2694 0 : dceip->underlay_vscaler_efficiency8_bit_per_component =
2695 : bw_frc_to_fixed(34286, 10000);
2696 0 : dceip->underlay_vscaler_efficiency10_bit_per_component =
2697 : bw_frc_to_fixed(32, 10);
2698 0 : dceip->underlay_vscaler_efficiency12_bit_per_component =
2699 : bw_int_to_fixed(3);
2700 0 : dceip->graphics_vscaler_efficiency6_bit_per_component =
2701 : bw_frc_to_fixed(35, 10);
2702 0 : dceip->graphics_vscaler_efficiency8_bit_per_component =
2703 : bw_frc_to_fixed(34286, 10000);
2704 0 : dceip->graphics_vscaler_efficiency10_bit_per_component =
2705 : bw_frc_to_fixed(32, 10);
2706 0 : dceip->graphics_vscaler_efficiency12_bit_per_component =
2707 : bw_int_to_fixed(3);
2708 0 : dceip->alpha_vscaler_efficiency = bw_int_to_fixed(3);
2709 0 : dceip->max_dmif_buffer_allocated = 4;
2710 0 : dceip->graphics_dmif_size = 24576;
2711 0 : dceip->underlay_luma_dmif_size = 19456;
2712 0 : dceip->underlay_chroma_dmif_size = 23552;
2713 0 : dceip->pre_downscaler_enabled = true;
2714 0 : dceip->underlay_downscale_prefetch_enabled = false;
2715 0 : dceip->lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2716 0 : dceip->lb_size_per_component444 = bw_int_to_fixed(245952);
2717 0 : dceip->graphics_lb_nodownscaling_multi_line_prefetching = true;
2718 0 : dceip->stutter_and_dram_clock_state_change_gated_before_cursor =
2719 : bw_int_to_fixed(1);
2720 0 : dceip->underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2721 : 82176);
2722 0 : dceip->underlay420_chroma_lb_size_per_component =
2723 : bw_int_to_fixed(164352);
2724 0 : dceip->underlay422_lb_size_per_component = bw_int_to_fixed(
2725 : 82176);
2726 0 : dceip->cursor_chunk_width = bw_int_to_fixed(64);
2727 0 : dceip->cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2728 0 : dceip->underlay_maximum_width_efficient_for_tiling =
2729 : bw_int_to_fixed(1920);
2730 0 : dceip->underlay_maximum_height_efficient_for_tiling =
2731 : bw_int_to_fixed(1080);
2732 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2733 : bw_frc_to_fixed(3, 10);
2734 0 : dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2735 : bw_int_to_fixed(25);
2736 0 : dceip->minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2737 : 2);
2738 0 : dceip->maximum_total_outstanding_pte_requests_allowed_by_saw =
2739 : bw_int_to_fixed(128);
2740 0 : dceip->limit_excessive_outstanding_dmif_requests = true;
2741 0 : dceip->linear_mode_line_request_alternation_slice =
2742 : bw_int_to_fixed(64);
2743 0 : dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2744 : 32;
2745 0 : dceip->display_write_back420_luma_mcifwr_buffer_size = 12288;
2746 0 : dceip->display_write_back420_chroma_mcifwr_buffer_size = 8192;
2747 0 : dceip->request_efficiency = bw_frc_to_fixed(8, 10);
2748 0 : dceip->dispclk_per_request = bw_int_to_fixed(2);
2749 0 : dceip->dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2750 0 : dceip->display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2751 0 : dceip->scatter_gather_pte_request_rows_in_tiling_mode = 2;
2752 0 : dceip->mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2753 0 : break;
2754 : default:
2755 : break;
2756 : }
2757 0 : *bw_dceip = *dceip;
2758 0 : *bw_vbios = *vbios;
2759 :
2760 0 : kfree(dceip);
2761 0 : kfree(vbios);
2762 : }
2763 :
2764 : /*
2765 : * Compare calculated (required) clocks against the clocks available at
2766 : * maximum voltage (max Performance Level).
2767 : */
2768 : static bool is_display_configuration_supported(
2769 : const struct bw_calcs_vbios *vbios,
2770 : const struct dce_bw_output *calcs_output)
2771 : {
2772 : uint32_t int_max_clk;
2773 :
2774 0 : int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk);
2775 0 : int_max_clk *= 1000; /* MHz to kHz */
2776 0 : if (calcs_output->dispclk_khz > int_max_clk)
2777 : return false;
2778 :
2779 0 : int_max_clk = bw_fixed_to_int(vbios->high_sclk);
2780 0 : int_max_clk *= 1000; /* MHz to kHz */
2781 0 : if (calcs_output->sclk_khz > int_max_clk)
2782 : return false;
2783 :
2784 : return true;
2785 : }
2786 :
2787 0 : static void populate_initial_data(
2788 : const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
2789 : {
2790 : int i, j;
2791 0 : int num_displays = 0;
2792 :
2793 0 : data->underlay_surface_type = bw_def_420;
2794 0 : data->panning_and_bezel_adjustment = bw_def_none;
2795 0 : data->graphics_lb_bpc = 10;
2796 0 : data->underlay_lb_bpc = 8;
2797 0 : data->underlay_tiling_mode = bw_def_tiled;
2798 0 : data->graphics_tiling_mode = bw_def_tiled;
2799 0 : data->underlay_micro_tile_mode = bw_def_display_micro_tiling;
2800 0 : data->graphics_micro_tile_mode = bw_def_display_micro_tiling;
2801 0 : data->increase_voltage_to_support_mclk_switch = true;
2802 :
2803 : /* Pipes with underlay first */
2804 0 : for (i = 0; i < pipe_count; i++) {
2805 0 : if (!pipe[i].stream || !pipe[i].bottom_pipe)
2806 0 : continue;
2807 :
2808 0 : ASSERT(pipe[i].plane_state);
2809 :
2810 0 : if (num_displays == 0) {
2811 0 : if (!pipe[i].plane_state->visible)
2812 0 : data->d0_underlay_mode = bw_def_underlay_only;
2813 : else
2814 0 : data->d0_underlay_mode = bw_def_blend;
2815 : } else {
2816 0 : if (!pipe[i].plane_state->visible)
2817 0 : data->d1_underlay_mode = bw_def_underlay_only;
2818 : else
2819 0 : data->d1_underlay_mode = bw_def_blend;
2820 : }
2821 :
2822 0 : data->fbc_en[num_displays + 4] = false;
2823 0 : data->lpt_en[num_displays + 4] = false;
2824 0 : data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2825 0 : data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2826 0 : data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);
2827 0 : data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2828 0 : data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2829 0 : data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2830 0 : data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2831 0 : data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2832 0 : data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2833 0 : data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2834 0 : switch (pipe[i].plane_state->rotation) {
2835 : case ROTATION_ANGLE_0:
2836 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2837 0 : break;
2838 : case ROTATION_ANGLE_90:
2839 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2840 0 : break;
2841 : case ROTATION_ANGLE_180:
2842 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2843 0 : break;
2844 : case ROTATION_ANGLE_270:
2845 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2846 0 : break;
2847 : default:
2848 : break;
2849 : }
2850 0 : switch (pipe[i].plane_state->format) {
2851 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2852 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2853 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2854 0 : data->bytes_per_pixel[num_displays + 4] = 2;
2855 0 : break;
2856 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2857 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2858 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2859 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2860 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2861 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2862 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2863 0 : data->bytes_per_pixel[num_displays + 4] = 4;
2864 0 : break;
2865 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2866 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
2867 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2868 0 : data->bytes_per_pixel[num_displays + 4] = 8;
2869 0 : break;
2870 : default:
2871 0 : data->bytes_per_pixel[num_displays + 4] = 4;
2872 0 : break;
2873 : }
2874 0 : data->interlace_mode[num_displays + 4] = false;
2875 0 : data->stereo_mode[num_displays + 4] = bw_def_mono;
2876 :
2877 :
2878 0 : for (j = 0; j < 2; j++) {
2879 0 : data->fbc_en[num_displays * 2 + j] = false;
2880 0 : data->lpt_en[num_displays * 2 + j] = false;
2881 :
2882 0 : data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2883 0 : data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2884 0 : data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
2885 0 : pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
2886 0 : data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2887 0 : data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
2888 0 : data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2889 0 : pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
2890 0 : data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2891 0 : pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
2892 0 : switch (pipe[i].bottom_pipe->plane_state->rotation) {
2893 : case ROTATION_ANGLE_0:
2894 0 : data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);
2895 0 : break;
2896 : case ROTATION_ANGLE_90:
2897 0 : data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(90);
2898 0 : break;
2899 : case ROTATION_ANGLE_180:
2900 0 : data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(180);
2901 0 : break;
2902 : case ROTATION_ANGLE_270:
2903 0 : data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(270);
2904 0 : break;
2905 : default:
2906 : break;
2907 : }
2908 0 : data->stereo_mode[num_displays * 2 + j] = bw_def_mono;
2909 : }
2910 :
2911 0 : num_displays++;
2912 : }
2913 :
2914 : /* Pipes without underlay after */
2915 0 : for (i = 0; i < pipe_count; i++) {
2916 : unsigned int pixel_clock_100hz;
2917 0 : if (!pipe[i].stream || pipe[i].bottom_pipe)
2918 0 : continue;
2919 :
2920 :
2921 0 : data->fbc_en[num_displays + 4] = false;
2922 0 : data->lpt_en[num_displays + 4] = false;
2923 0 : data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2924 0 : data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2925 0 : pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;
2926 0 : if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2927 0 : pixel_clock_100hz *= 2;
2928 0 : data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_100hz, 10000);
2929 0 : if (pipe[i].plane_state) {
2930 0 : data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2931 0 : data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2932 0 : data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2933 0 : data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2934 0 : data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2935 0 : data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2936 0 : data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2937 0 : switch (pipe[i].plane_state->rotation) {
2938 : case ROTATION_ANGLE_0:
2939 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2940 0 : break;
2941 : case ROTATION_ANGLE_90:
2942 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2943 0 : break;
2944 : case ROTATION_ANGLE_180:
2945 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2946 0 : break;
2947 : case ROTATION_ANGLE_270:
2948 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2949 0 : break;
2950 : default:
2951 : break;
2952 : }
2953 0 : switch (pipe[i].plane_state->format) {
2954 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2955 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2956 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2957 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2958 0 : data->bytes_per_pixel[num_displays + 4] = 2;
2959 0 : break;
2960 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2961 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2962 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2963 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2964 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2965 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2966 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2967 0 : data->bytes_per_pixel[num_displays + 4] = 4;
2968 0 : break;
2969 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2970 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
2971 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2972 0 : data->bytes_per_pixel[num_displays + 4] = 8;
2973 0 : break;
2974 : default:
2975 0 : data->bytes_per_pixel[num_displays + 4] = 4;
2976 0 : break;
2977 : }
2978 0 : } else if (pipe[i].stream->dst.width != 0 &&
2979 0 : pipe[i].stream->dst.height != 0 &&
2980 0 : pipe[i].stream->src.width != 0 &&
2981 0 : pipe[i].stream->src.height != 0) {
2982 0 : data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
2983 0 : data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2984 0 : data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
2985 0 : data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2986 0 : data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2987 0 : data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
2988 0 : data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
2989 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2990 0 : data->bytes_per_pixel[num_displays + 4] = 4;
2991 : } else {
2992 0 : data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
2993 0 : data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2994 0 : data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
2995 0 : data->h_taps[num_displays + 4] = bw_int_to_fixed(1);
2996 0 : data->v_taps[num_displays + 4] = bw_int_to_fixed(1);
2997 0 : data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2998 0 : data->v_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2999 0 : data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
3000 0 : data->bytes_per_pixel[num_displays + 4] = 4;
3001 : }
3002 :
3003 0 : data->interlace_mode[num_displays + 4] = false;
3004 0 : data->stereo_mode[num_displays + 4] = bw_def_mono;
3005 0 : num_displays++;
3006 : }
3007 :
3008 0 : data->number_of_displays = num_displays;
3009 0 : }
3010 :
3011 0 : static bool all_displays_in_sync(const struct pipe_ctx pipe[],
3012 : int pipe_count)
3013 : {
3014 : const struct pipe_ctx *active_pipes[MAX_PIPES];
3015 0 : int i, num_active_pipes = 0;
3016 :
3017 0 : for (i = 0; i < pipe_count; i++) {
3018 0 : if (!pipe[i].stream || pipe[i].top_pipe)
3019 0 : continue;
3020 :
3021 0 : active_pipes[num_active_pipes++] = &pipe[i];
3022 : }
3023 :
3024 0 : if (!num_active_pipes)
3025 : return false;
3026 :
3027 0 : for (i = 1; i < num_active_pipes; ++i) {
3028 0 : if (!resource_are_streams_timing_synchronizable(
3029 0 : active_pipes[0]->stream, active_pipes[i]->stream)) {
3030 : return false;
3031 : }
3032 : }
3033 :
3034 : return true;
3035 : }
3036 :
3037 : /*
3038 : * Return:
3039 : * true - Display(s) configuration supported.
3040 : * In this case 'calcs_output' contains data for HW programming
3041 : * false - Display(s) configuration not supported (not enough bandwidth).
3042 : */
3043 0 : bool bw_calcs(struct dc_context *ctx,
3044 : const struct bw_calcs_dceip *dceip,
3045 : const struct bw_calcs_vbios *vbios,
3046 : const struct pipe_ctx pipe[],
3047 : int pipe_count,
3048 : struct dce_bw_output *calcs_output)
3049 : {
3050 0 : struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data),
3051 : GFP_KERNEL);
3052 0 : if (!data)
3053 : return false;
3054 :
3055 0 : populate_initial_data(pipe, pipe_count, data);
3056 :
3057 0 : if (ctx->dc->config.multi_mon_pp_mclk_switch)
3058 0 : calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
3059 : else
3060 0 : calcs_output->all_displays_in_sync = false;
3061 :
3062 0 : if (data->number_of_displays != 0) {
3063 : uint8_t yclk_lvl;
3064 0 : struct bw_fixed high_sclk = vbios->high_sclk;
3065 0 : struct bw_fixed mid1_sclk = vbios->mid1_sclk;
3066 0 : struct bw_fixed mid2_sclk = vbios->mid2_sclk;
3067 0 : struct bw_fixed mid3_sclk = vbios->mid3_sclk;
3068 0 : struct bw_fixed mid4_sclk = vbios->mid4_sclk;
3069 0 : struct bw_fixed mid5_sclk = vbios->mid5_sclk;
3070 0 : struct bw_fixed mid6_sclk = vbios->mid6_sclk;
3071 0 : struct bw_fixed low_sclk = vbios->low_sclk;
3072 0 : struct bw_fixed high_yclk = vbios->high_yclk;
3073 0 : struct bw_fixed mid_yclk = vbios->mid_yclk;
3074 0 : struct bw_fixed low_yclk = vbios->low_yclk;
3075 :
3076 : if (ctx->dc->debug.bandwidth_calcs_trace) {
3077 : print_bw_calcs_dceip(ctx, dceip);
3078 : print_bw_calcs_vbios(ctx, vbios);
3079 : print_bw_calcs_data(ctx, data);
3080 : }
3081 0 : calculate_bandwidth(dceip, vbios, data);
3082 :
3083 0 : yclk_lvl = data->y_clk_level;
3084 :
3085 0 : calcs_output->nbp_state_change_enable =
3086 0 : data->nbp_state_change_enable;
3087 0 : calcs_output->cpuc_state_change_enable =
3088 0 : data->cpuc_state_change_enable;
3089 0 : calcs_output->cpup_state_change_enable =
3090 0 : data->cpup_state_change_enable;
3091 0 : calcs_output->stutter_mode_enable =
3092 0 : data->stutter_mode_enable;
3093 0 : calcs_output->dispclk_khz =
3094 0 : bw_fixed_to_int(bw_mul(data->dispclk,
3095 : bw_int_to_fixed(1000)));
3096 0 : calcs_output->blackout_recovery_time_us =
3097 : bw_fixed_to_int(data->blackout_recovery_time);
3098 0 : calcs_output->sclk_khz =
3099 0 : bw_fixed_to_int(bw_mul(data->required_sclk,
3100 : bw_int_to_fixed(1000)));
3101 0 : calcs_output->sclk_deep_sleep_khz =
3102 0 : bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,
3103 : bw_int_to_fixed(1000)));
3104 0 : if (yclk_lvl == 0)
3105 0 : calcs_output->yclk_khz = bw_fixed_to_int(
3106 : bw_mul(low_yclk, bw_int_to_fixed(1000)));
3107 0 : else if (yclk_lvl == 1)
3108 0 : calcs_output->yclk_khz = bw_fixed_to_int(
3109 : bw_mul(mid_yclk, bw_int_to_fixed(1000)));
3110 : else
3111 0 : calcs_output->yclk_khz = bw_fixed_to_int(
3112 : bw_mul(high_yclk, bw_int_to_fixed(1000)));
3113 :
3114 : /* units: nanosecond, 16bit storage. */
3115 :
3116 0 : calcs_output->nbp_state_change_wm_ns[0].a_mark =
3117 0 : bw_fixed_to_int(bw_mul(data->
3118 : nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3119 0 : calcs_output->nbp_state_change_wm_ns[1].a_mark =
3120 0 : bw_fixed_to_int(bw_mul(data->
3121 : nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3122 0 : calcs_output->nbp_state_change_wm_ns[2].a_mark =
3123 0 : bw_fixed_to_int(bw_mul(data->
3124 : nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3125 :
3126 0 : if (ctx->dc->caps.max_slave_planes) {
3127 0 : calcs_output->nbp_state_change_wm_ns[3].a_mark =
3128 0 : bw_fixed_to_int(bw_mul(data->
3129 : nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3130 0 : calcs_output->nbp_state_change_wm_ns[4].a_mark =
3131 0 : bw_fixed_to_int(bw_mul(data->
3132 : nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3133 : } else {
3134 0 : calcs_output->nbp_state_change_wm_ns[3].a_mark =
3135 0 : bw_fixed_to_int(bw_mul(data->
3136 : nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3137 0 : calcs_output->nbp_state_change_wm_ns[4].a_mark =
3138 0 : bw_fixed_to_int(bw_mul(data->
3139 : nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3140 : }
3141 0 : calcs_output->nbp_state_change_wm_ns[5].a_mark =
3142 0 : bw_fixed_to_int(bw_mul(data->
3143 : nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3144 :
3145 :
3146 :
3147 0 : calcs_output->stutter_exit_wm_ns[0].a_mark =
3148 0 : bw_fixed_to_int(bw_mul(data->
3149 : stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3150 0 : calcs_output->stutter_exit_wm_ns[1].a_mark =
3151 0 : bw_fixed_to_int(bw_mul(data->
3152 : stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3153 0 : calcs_output->stutter_exit_wm_ns[2].a_mark =
3154 0 : bw_fixed_to_int(bw_mul(data->
3155 : stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3156 0 : if (ctx->dc->caps.max_slave_planes) {
3157 0 : calcs_output->stutter_exit_wm_ns[3].a_mark =
3158 0 : bw_fixed_to_int(bw_mul(data->
3159 : stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3160 0 : calcs_output->stutter_exit_wm_ns[4].a_mark =
3161 0 : bw_fixed_to_int(bw_mul(data->
3162 : stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3163 : } else {
3164 0 : calcs_output->stutter_exit_wm_ns[3].a_mark =
3165 0 : bw_fixed_to_int(bw_mul(data->
3166 : stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3167 0 : calcs_output->stutter_exit_wm_ns[4].a_mark =
3168 0 : bw_fixed_to_int(bw_mul(data->
3169 : stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3170 : }
3171 0 : calcs_output->stutter_exit_wm_ns[5].a_mark =
3172 0 : bw_fixed_to_int(bw_mul(data->
3173 : stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3174 :
3175 0 : calcs_output->stutter_entry_wm_ns[0].a_mark =
3176 0 : bw_fixed_to_int(bw_mul(data->
3177 : stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3178 0 : calcs_output->stutter_entry_wm_ns[1].a_mark =
3179 0 : bw_fixed_to_int(bw_mul(data->
3180 : stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3181 0 : calcs_output->stutter_entry_wm_ns[2].a_mark =
3182 0 : bw_fixed_to_int(bw_mul(data->
3183 : stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3184 0 : if (ctx->dc->caps.max_slave_planes) {
3185 0 : calcs_output->stutter_entry_wm_ns[3].a_mark =
3186 0 : bw_fixed_to_int(bw_mul(data->
3187 : stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3188 0 : calcs_output->stutter_entry_wm_ns[4].a_mark =
3189 0 : bw_fixed_to_int(bw_mul(data->
3190 : stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3191 : } else {
3192 0 : calcs_output->stutter_entry_wm_ns[3].a_mark =
3193 0 : bw_fixed_to_int(bw_mul(data->
3194 : stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3195 0 : calcs_output->stutter_entry_wm_ns[4].a_mark =
3196 0 : bw_fixed_to_int(bw_mul(data->
3197 : stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3198 : }
3199 0 : calcs_output->stutter_entry_wm_ns[5].a_mark =
3200 0 : bw_fixed_to_int(bw_mul(data->
3201 : stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3202 :
3203 0 : calcs_output->urgent_wm_ns[0].a_mark =
3204 0 : bw_fixed_to_int(bw_mul(data->
3205 : urgent_watermark[4], bw_int_to_fixed(1000)));
3206 0 : calcs_output->urgent_wm_ns[1].a_mark =
3207 0 : bw_fixed_to_int(bw_mul(data->
3208 : urgent_watermark[5], bw_int_to_fixed(1000)));
3209 0 : calcs_output->urgent_wm_ns[2].a_mark =
3210 0 : bw_fixed_to_int(bw_mul(data->
3211 : urgent_watermark[6], bw_int_to_fixed(1000)));
3212 0 : if (ctx->dc->caps.max_slave_planes) {
3213 0 : calcs_output->urgent_wm_ns[3].a_mark =
3214 0 : bw_fixed_to_int(bw_mul(data->
3215 : urgent_watermark[0], bw_int_to_fixed(1000)));
3216 0 : calcs_output->urgent_wm_ns[4].a_mark =
3217 0 : bw_fixed_to_int(bw_mul(data->
3218 : urgent_watermark[1], bw_int_to_fixed(1000)));
3219 : } else {
3220 0 : calcs_output->urgent_wm_ns[3].a_mark =
3221 0 : bw_fixed_to_int(bw_mul(data->
3222 : urgent_watermark[7], bw_int_to_fixed(1000)));
3223 0 : calcs_output->urgent_wm_ns[4].a_mark =
3224 0 : bw_fixed_to_int(bw_mul(data->
3225 : urgent_watermark[8], bw_int_to_fixed(1000)));
3226 : }
3227 0 : calcs_output->urgent_wm_ns[5].a_mark =
3228 0 : bw_fixed_to_int(bw_mul(data->
3229 : urgent_watermark[9], bw_int_to_fixed(1000)));
3230 :
3231 0 : if (dceip->version != BW_CALCS_VERSION_CARRIZO) {
3232 0 : ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3233 0 : ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3234 0 : ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3235 0 : calculate_bandwidth(dceip, vbios, data);
3236 :
3237 0 : calcs_output->nbp_state_change_wm_ns[0].b_mark =
3238 0 : bw_fixed_to_int(bw_mul(data->
3239 : nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
3240 0 : calcs_output->nbp_state_change_wm_ns[1].b_mark =
3241 0 : bw_fixed_to_int(bw_mul(data->
3242 : nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3243 0 : calcs_output->nbp_state_change_wm_ns[2].b_mark =
3244 0 : bw_fixed_to_int(bw_mul(data->
3245 : nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3246 :
3247 0 : if (ctx->dc->caps.max_slave_planes) {
3248 0 : calcs_output->nbp_state_change_wm_ns[3].b_mark =
3249 0 : bw_fixed_to_int(bw_mul(data->
3250 : nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3251 0 : calcs_output->nbp_state_change_wm_ns[4].b_mark =
3252 0 : bw_fixed_to_int(bw_mul(data->
3253 : nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3254 : } else {
3255 0 : calcs_output->nbp_state_change_wm_ns[3].b_mark =
3256 0 : bw_fixed_to_int(bw_mul(data->
3257 : nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3258 0 : calcs_output->nbp_state_change_wm_ns[4].b_mark =
3259 0 : bw_fixed_to_int(bw_mul(data->
3260 : nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3261 : }
3262 0 : calcs_output->nbp_state_change_wm_ns[5].b_mark =
3263 0 : bw_fixed_to_int(bw_mul(data->
3264 : nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3265 :
3266 :
3267 :
3268 0 : calcs_output->stutter_exit_wm_ns[0].b_mark =
3269 0 : bw_fixed_to_int(bw_mul(data->
3270 : stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3271 0 : calcs_output->stutter_exit_wm_ns[1].b_mark =
3272 0 : bw_fixed_to_int(bw_mul(data->
3273 : stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3274 0 : calcs_output->stutter_exit_wm_ns[2].b_mark =
3275 0 : bw_fixed_to_int(bw_mul(data->
3276 : stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3277 0 : if (ctx->dc->caps.max_slave_planes) {
3278 0 : calcs_output->stutter_exit_wm_ns[3].b_mark =
3279 0 : bw_fixed_to_int(bw_mul(data->
3280 : stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3281 0 : calcs_output->stutter_exit_wm_ns[4].b_mark =
3282 0 : bw_fixed_to_int(bw_mul(data->
3283 : stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3284 : } else {
3285 0 : calcs_output->stutter_exit_wm_ns[3].b_mark =
3286 0 : bw_fixed_to_int(bw_mul(data->
3287 : stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3288 0 : calcs_output->stutter_exit_wm_ns[4].b_mark =
3289 0 : bw_fixed_to_int(bw_mul(data->
3290 : stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3291 : }
3292 0 : calcs_output->stutter_exit_wm_ns[5].b_mark =
3293 0 : bw_fixed_to_int(bw_mul(data->
3294 : stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3295 :
3296 0 : calcs_output->stutter_entry_wm_ns[0].b_mark =
3297 0 : bw_fixed_to_int(bw_mul(data->
3298 : stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3299 0 : calcs_output->stutter_entry_wm_ns[1].b_mark =
3300 0 : bw_fixed_to_int(bw_mul(data->
3301 : stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3302 0 : calcs_output->stutter_entry_wm_ns[2].b_mark =
3303 0 : bw_fixed_to_int(bw_mul(data->
3304 : stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3305 0 : if (ctx->dc->caps.max_slave_planes) {
3306 0 : calcs_output->stutter_entry_wm_ns[3].b_mark =
3307 0 : bw_fixed_to_int(bw_mul(data->
3308 : stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3309 0 : calcs_output->stutter_entry_wm_ns[4].b_mark =
3310 0 : bw_fixed_to_int(bw_mul(data->
3311 : stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3312 : } else {
3313 0 : calcs_output->stutter_entry_wm_ns[3].b_mark =
3314 0 : bw_fixed_to_int(bw_mul(data->
3315 : stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3316 0 : calcs_output->stutter_entry_wm_ns[4].b_mark =
3317 0 : bw_fixed_to_int(bw_mul(data->
3318 : stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3319 : }
3320 0 : calcs_output->stutter_entry_wm_ns[5].b_mark =
3321 0 : bw_fixed_to_int(bw_mul(data->
3322 : stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3323 :
3324 0 : calcs_output->urgent_wm_ns[0].b_mark =
3325 0 : bw_fixed_to_int(bw_mul(data->
3326 : urgent_watermark[4], bw_int_to_fixed(1000)));
3327 0 : calcs_output->urgent_wm_ns[1].b_mark =
3328 0 : bw_fixed_to_int(bw_mul(data->
3329 : urgent_watermark[5], bw_int_to_fixed(1000)));
3330 0 : calcs_output->urgent_wm_ns[2].b_mark =
3331 0 : bw_fixed_to_int(bw_mul(data->
3332 : urgent_watermark[6], bw_int_to_fixed(1000)));
3333 0 : if (ctx->dc->caps.max_slave_planes) {
3334 0 : calcs_output->urgent_wm_ns[3].b_mark =
3335 0 : bw_fixed_to_int(bw_mul(data->
3336 : urgent_watermark[0], bw_int_to_fixed(1000)));
3337 0 : calcs_output->urgent_wm_ns[4].b_mark =
3338 0 : bw_fixed_to_int(bw_mul(data->
3339 : urgent_watermark[1], bw_int_to_fixed(1000)));
3340 : } else {
3341 0 : calcs_output->urgent_wm_ns[3].b_mark =
3342 0 : bw_fixed_to_int(bw_mul(data->
3343 : urgent_watermark[7], bw_int_to_fixed(1000)));
3344 0 : calcs_output->urgent_wm_ns[4].b_mark =
3345 0 : bw_fixed_to_int(bw_mul(data->
3346 : urgent_watermark[8], bw_int_to_fixed(1000)));
3347 : }
3348 0 : calcs_output->urgent_wm_ns[5].b_mark =
3349 0 : bw_fixed_to_int(bw_mul(data->
3350 : urgent_watermark[9], bw_int_to_fixed(1000)));
3351 :
3352 0 : ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3353 0 : ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3354 0 : ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3355 0 : ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3356 0 : calculate_bandwidth(dceip, vbios, data);
3357 :
3358 0 : calcs_output->nbp_state_change_wm_ns[0].c_mark =
3359 0 : bw_fixed_to_int(bw_mul(data->
3360 : nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3361 0 : calcs_output->nbp_state_change_wm_ns[1].c_mark =
3362 0 : bw_fixed_to_int(bw_mul(data->
3363 : nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3364 0 : calcs_output->nbp_state_change_wm_ns[2].c_mark =
3365 0 : bw_fixed_to_int(bw_mul(data->
3366 : nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3367 0 : if (ctx->dc->caps.max_slave_planes) {
3368 0 : calcs_output->nbp_state_change_wm_ns[3].c_mark =
3369 0 : bw_fixed_to_int(bw_mul(data->
3370 : nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3371 0 : calcs_output->nbp_state_change_wm_ns[4].c_mark =
3372 0 : bw_fixed_to_int(bw_mul(data->
3373 : nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3374 : } else {
3375 0 : calcs_output->nbp_state_change_wm_ns[3].c_mark =
3376 0 : bw_fixed_to_int(bw_mul(data->
3377 : nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3378 0 : calcs_output->nbp_state_change_wm_ns[4].c_mark =
3379 0 : bw_fixed_to_int(bw_mul(data->
3380 : nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3381 : }
3382 0 : calcs_output->nbp_state_change_wm_ns[5].c_mark =
3383 0 : bw_fixed_to_int(bw_mul(data->
3384 : nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3385 :
3386 :
3387 0 : calcs_output->stutter_exit_wm_ns[0].c_mark =
3388 0 : bw_fixed_to_int(bw_mul(data->
3389 : stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3390 0 : calcs_output->stutter_exit_wm_ns[1].c_mark =
3391 0 : bw_fixed_to_int(bw_mul(data->
3392 : stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3393 0 : calcs_output->stutter_exit_wm_ns[2].c_mark =
3394 0 : bw_fixed_to_int(bw_mul(data->
3395 : stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3396 0 : if (ctx->dc->caps.max_slave_planes) {
3397 0 : calcs_output->stutter_exit_wm_ns[3].c_mark =
3398 0 : bw_fixed_to_int(bw_mul(data->
3399 : stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3400 0 : calcs_output->stutter_exit_wm_ns[4].c_mark =
3401 0 : bw_fixed_to_int(bw_mul(data->
3402 : stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3403 : } else {
3404 0 : calcs_output->stutter_exit_wm_ns[3].c_mark =
3405 0 : bw_fixed_to_int(bw_mul(data->
3406 : stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3407 0 : calcs_output->stutter_exit_wm_ns[4].c_mark =
3408 0 : bw_fixed_to_int(bw_mul(data->
3409 : stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3410 : }
3411 0 : calcs_output->stutter_exit_wm_ns[5].c_mark =
3412 0 : bw_fixed_to_int(bw_mul(data->
3413 : stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3414 0 : calcs_output->stutter_entry_wm_ns[0].c_mark =
3415 0 : bw_fixed_to_int(bw_mul(data->
3416 : stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3417 0 : calcs_output->stutter_entry_wm_ns[1].c_mark =
3418 0 : bw_fixed_to_int(bw_mul(data->
3419 : stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3420 0 : calcs_output->stutter_entry_wm_ns[2].c_mark =
3421 0 : bw_fixed_to_int(bw_mul(data->
3422 : stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3423 0 : if (ctx->dc->caps.max_slave_planes) {
3424 0 : calcs_output->stutter_entry_wm_ns[3].c_mark =
3425 0 : bw_fixed_to_int(bw_mul(data->stutter_entry_watermark[0],
3426 : bw_int_to_fixed(1000)));
3427 0 : calcs_output->stutter_entry_wm_ns[4].c_mark =
3428 0 : bw_fixed_to_int(bw_mul(data->stutter_entry_watermark[1],
3429 : bw_int_to_fixed(1000)));
3430 : } else {
3431 0 : calcs_output->stutter_entry_wm_ns[3].c_mark =
3432 0 : bw_fixed_to_int(bw_mul(data->stutter_entry_watermark[7],
3433 : bw_int_to_fixed(1000)));
3434 0 : calcs_output->stutter_entry_wm_ns[4].c_mark =
3435 0 : bw_fixed_to_int(bw_mul(data->stutter_entry_watermark[8],
3436 : bw_int_to_fixed(1000)));
3437 : }
3438 0 : calcs_output->stutter_entry_wm_ns[5].c_mark =
3439 0 : bw_fixed_to_int(bw_mul(data->
3440 : stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3441 0 : calcs_output->urgent_wm_ns[0].c_mark =
3442 0 : bw_fixed_to_int(bw_mul(data->
3443 : urgent_watermark[4], bw_int_to_fixed(1000)));
3444 0 : calcs_output->urgent_wm_ns[1].c_mark =
3445 0 : bw_fixed_to_int(bw_mul(data->
3446 : urgent_watermark[5], bw_int_to_fixed(1000)));
3447 0 : calcs_output->urgent_wm_ns[2].c_mark =
3448 0 : bw_fixed_to_int(bw_mul(data->
3449 : urgent_watermark[6], bw_int_to_fixed(1000)));
3450 0 : if (ctx->dc->caps.max_slave_planes) {
3451 0 : calcs_output->urgent_wm_ns[3].c_mark =
3452 0 : bw_fixed_to_int(bw_mul(data->
3453 : urgent_watermark[0], bw_int_to_fixed(1000)));
3454 0 : calcs_output->urgent_wm_ns[4].c_mark =
3455 0 : bw_fixed_to_int(bw_mul(data->
3456 : urgent_watermark[1], bw_int_to_fixed(1000)));
3457 : } else {
3458 0 : calcs_output->urgent_wm_ns[3].c_mark =
3459 0 : bw_fixed_to_int(bw_mul(data->
3460 : urgent_watermark[7], bw_int_to_fixed(1000)));
3461 0 : calcs_output->urgent_wm_ns[4].c_mark =
3462 0 : bw_fixed_to_int(bw_mul(data->
3463 : urgent_watermark[8], bw_int_to_fixed(1000)));
3464 : }
3465 0 : calcs_output->urgent_wm_ns[5].c_mark =
3466 0 : bw_fixed_to_int(bw_mul(data->
3467 : urgent_watermark[9], bw_int_to_fixed(1000)));
3468 : }
3469 :
3470 0 : if (dceip->version == BW_CALCS_VERSION_CARRIZO) {
3471 0 : ((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
3472 0 : ((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
3473 0 : ((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
3474 0 : ((struct bw_calcs_vbios *)vbios)->mid1_sclk = high_sclk;
3475 0 : ((struct bw_calcs_vbios *)vbios)->mid2_sclk = high_sclk;
3476 0 : ((struct bw_calcs_vbios *)vbios)->mid3_sclk = high_sclk;
3477 0 : ((struct bw_calcs_vbios *)vbios)->mid4_sclk = high_sclk;
3478 0 : ((struct bw_calcs_vbios *)vbios)->mid5_sclk = high_sclk;
3479 0 : ((struct bw_calcs_vbios *)vbios)->mid6_sclk = high_sclk;
3480 : } else {
3481 0 : ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3482 0 : ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3483 0 : ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3484 0 : ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3485 : }
3486 :
3487 0 : calculate_bandwidth(dceip, vbios, data);
3488 :
3489 0 : calcs_output->nbp_state_change_wm_ns[0].d_mark =
3490 0 : bw_fixed_to_int(bw_mul(data->
3491 : nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3492 0 : calcs_output->nbp_state_change_wm_ns[1].d_mark =
3493 0 : bw_fixed_to_int(bw_mul(data->
3494 : nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3495 0 : calcs_output->nbp_state_change_wm_ns[2].d_mark =
3496 0 : bw_fixed_to_int(bw_mul(data->
3497 : nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3498 0 : if (ctx->dc->caps.max_slave_planes) {
3499 0 : calcs_output->nbp_state_change_wm_ns[3].d_mark =
3500 0 : bw_fixed_to_int(bw_mul(data->
3501 : nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3502 0 : calcs_output->nbp_state_change_wm_ns[4].d_mark =
3503 0 : bw_fixed_to_int(bw_mul(data->
3504 : nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3505 : } else {
3506 0 : calcs_output->nbp_state_change_wm_ns[3].d_mark =
3507 0 : bw_fixed_to_int(bw_mul(data->
3508 : nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3509 0 : calcs_output->nbp_state_change_wm_ns[4].d_mark =
3510 0 : bw_fixed_to_int(bw_mul(data->
3511 : nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3512 : }
3513 0 : calcs_output->nbp_state_change_wm_ns[5].d_mark =
3514 0 : bw_fixed_to_int(bw_mul(data->
3515 : nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3516 :
3517 0 : calcs_output->stutter_exit_wm_ns[0].d_mark =
3518 0 : bw_fixed_to_int(bw_mul(data->
3519 : stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3520 0 : calcs_output->stutter_exit_wm_ns[1].d_mark =
3521 0 : bw_fixed_to_int(bw_mul(data->
3522 : stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3523 0 : calcs_output->stutter_exit_wm_ns[2].d_mark =
3524 0 : bw_fixed_to_int(bw_mul(data->
3525 : stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3526 0 : if (ctx->dc->caps.max_slave_planes) {
3527 0 : calcs_output->stutter_exit_wm_ns[3].d_mark =
3528 0 : bw_fixed_to_int(bw_mul(data->
3529 : stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3530 0 : calcs_output->stutter_exit_wm_ns[4].d_mark =
3531 0 : bw_fixed_to_int(bw_mul(data->
3532 : stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3533 : } else {
3534 0 : calcs_output->stutter_exit_wm_ns[3].d_mark =
3535 0 : bw_fixed_to_int(bw_mul(data->
3536 : stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3537 0 : calcs_output->stutter_exit_wm_ns[4].d_mark =
3538 0 : bw_fixed_to_int(bw_mul(data->
3539 : stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3540 : }
3541 0 : calcs_output->stutter_exit_wm_ns[5].d_mark =
3542 0 : bw_fixed_to_int(bw_mul(data->
3543 : stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3544 :
3545 0 : calcs_output->stutter_entry_wm_ns[0].d_mark =
3546 0 : bw_fixed_to_int(bw_mul(data->
3547 : stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3548 0 : calcs_output->stutter_entry_wm_ns[1].d_mark =
3549 0 : bw_fixed_to_int(bw_mul(data->
3550 : stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3551 0 : calcs_output->stutter_entry_wm_ns[2].d_mark =
3552 0 : bw_fixed_to_int(bw_mul(data->
3553 : stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3554 0 : if (ctx->dc->caps.max_slave_planes) {
3555 0 : calcs_output->stutter_entry_wm_ns[3].d_mark =
3556 0 : bw_fixed_to_int(bw_mul(data->
3557 : stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3558 0 : calcs_output->stutter_entry_wm_ns[4].d_mark =
3559 0 : bw_fixed_to_int(bw_mul(data->
3560 : stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3561 : } else {
3562 0 : calcs_output->stutter_entry_wm_ns[3].d_mark =
3563 0 : bw_fixed_to_int(bw_mul(data->
3564 : stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3565 0 : calcs_output->stutter_entry_wm_ns[4].d_mark =
3566 0 : bw_fixed_to_int(bw_mul(data->
3567 : stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3568 : }
3569 0 : calcs_output->stutter_entry_wm_ns[5].d_mark =
3570 0 : bw_fixed_to_int(bw_mul(data->
3571 : stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3572 :
3573 0 : calcs_output->urgent_wm_ns[0].d_mark =
3574 0 : bw_fixed_to_int(bw_mul(data->
3575 : urgent_watermark[4], bw_int_to_fixed(1000)));
3576 0 : calcs_output->urgent_wm_ns[1].d_mark =
3577 0 : bw_fixed_to_int(bw_mul(data->
3578 : urgent_watermark[5], bw_int_to_fixed(1000)));
3579 0 : calcs_output->urgent_wm_ns[2].d_mark =
3580 0 : bw_fixed_to_int(bw_mul(data->
3581 : urgent_watermark[6], bw_int_to_fixed(1000)));
3582 0 : if (ctx->dc->caps.max_slave_planes) {
3583 0 : calcs_output->urgent_wm_ns[3].d_mark =
3584 0 : bw_fixed_to_int(bw_mul(data->
3585 : urgent_watermark[0], bw_int_to_fixed(1000)));
3586 0 : calcs_output->urgent_wm_ns[4].d_mark =
3587 0 : bw_fixed_to_int(bw_mul(data->
3588 : urgent_watermark[1], bw_int_to_fixed(1000)));
3589 : } else {
3590 0 : calcs_output->urgent_wm_ns[3].d_mark =
3591 0 : bw_fixed_to_int(bw_mul(data->
3592 : urgent_watermark[7], bw_int_to_fixed(1000)));
3593 0 : calcs_output->urgent_wm_ns[4].d_mark =
3594 0 : bw_fixed_to_int(bw_mul(data->
3595 : urgent_watermark[8], bw_int_to_fixed(1000)));
3596 : }
3597 0 : calcs_output->urgent_wm_ns[5].d_mark =
3598 0 : bw_fixed_to_int(bw_mul(data->
3599 : urgent_watermark[9], bw_int_to_fixed(1000)));
3600 :
3601 0 : ((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
3602 0 : ((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
3603 0 : ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3604 0 : ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3605 0 : ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3606 0 : ((struct bw_calcs_vbios *)vbios)->mid3_sclk = mid3_sclk;
3607 0 : ((struct bw_calcs_vbios *)vbios)->mid4_sclk = mid4_sclk;
3608 0 : ((struct bw_calcs_vbios *)vbios)->mid5_sclk = mid5_sclk;
3609 0 : ((struct bw_calcs_vbios *)vbios)->mid6_sclk = mid6_sclk;
3610 0 : ((struct bw_calcs_vbios *)vbios)->high_sclk = high_sclk;
3611 : } else {
3612 0 : calcs_output->nbp_state_change_enable = true;
3613 0 : calcs_output->cpuc_state_change_enable = true;
3614 0 : calcs_output->cpup_state_change_enable = true;
3615 0 : calcs_output->stutter_mode_enable = true;
3616 0 : calcs_output->dispclk_khz = 0;
3617 0 : calcs_output->sclk_khz = 0;
3618 : }
3619 :
3620 0 : kfree(data);
3621 :
3622 0 : return is_display_configuration_supported(vbios, calcs_output);
3623 : }
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