Line data Source code
1 : /*
2 : * Copyright 2017 Advanced Micro Devices, Inc.
3 : * Copyright 2019 Raptor Engineering, LLC
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: AMD
24 : *
25 : */
26 :
27 : #include "dm_services.h"
28 : #include "dc.h"
29 : #include "dcn_calcs.h"
30 : #include "dcn_calc_auto.h"
31 : #include "dal_asic_id.h"
32 : #include "resource.h"
33 : #include "dcn10/dcn10_resource.h"
34 : #include "dcn10/dcn10_hubbub.h"
35 : #include "dml/dml1_display_rq_dlg_calc.h"
36 :
37 : #include "dcn_calc_math.h"
38 :
39 : #define DC_LOGGER \
40 : dc->ctx->logger
41 :
42 : #define WM_SET_COUNT 4
43 : #define WM_A 0
44 : #define WM_B 1
45 : #define WM_C 2
46 : #define WM_D 3
47 :
48 : /*
49 : * NOTE:
50 : * This file is gcc-parseable HW gospel, coming straight from HW engineers.
51 : *
52 : * It doesn't adhere to Linux kernel style and sometimes will do things in odd
53 : * ways. Unless there is something clearly wrong with it the code should
54 : * remain as-is as it provides us with a guarantee from HW that it is correct.
55 : */
56 :
57 : /* Defaults from spreadsheet rev#247.
58 : * RV2 delta: dram_clock_change_latency, max_num_dpp
59 : */
60 : const struct dcn_soc_bounding_box dcn10_soc_defaults = {
61 : /* latencies */
62 : .sr_exit_time = 17, /*us*/
63 : .sr_enter_plus_exit_time = 19, /*us*/
64 : .urgent_latency = 4, /*us*/
65 : .dram_clock_change_latency = 17, /*us*/
66 : .write_back_latency = 12, /*us*/
67 : .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
68 :
69 : /* below default clocks derived from STA target base on
70 : * slow-slow corner + 10% margin with voltages aligned to FCLK.
71 : *
72 : * Use these value if fused value doesn't make sense as earlier
73 : * part don't have correct value fused */
74 : /* default DCF CLK DPM on RV*/
75 : .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
76 : .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
77 : .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
78 : .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
79 :
80 : /* default DISP CLK voltage state on RV */
81 : .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
82 : .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
83 : .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
84 : .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
85 :
86 : /* default DPP CLK voltage state on RV */
87 : .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
88 : .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
89 : .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
90 : .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
91 :
92 : /* default PHY CLK voltage state on RV */
93 : .phyclkv_max0p9 = 900, /*MHz*/
94 : .phyclkv_nom0p8 = 847, /*MHz*/
95 : .phyclkv_mid0p72 = 800, /*MHz*/
96 : .phyclkv_min0p65 = 600, /*MHz*/
97 :
98 : /* BW depend on FCLK, MCLK, # of channels */
99 : /* dual channel BW */
100 : .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
101 : .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
102 : .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
103 : .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
104 : /* single channel BW
105 : .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
106 : .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
107 : .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
108 : .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
109 : */
110 :
111 : .number_of_channels = 2,
112 :
113 : .socclk = 208, /*MHz*/
114 : .downspreading = 0.5f, /*%*/
115 : .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
116 : .urgent_out_of_order_return_per_channel = 256, /*bytes*/
117 : .vmm_page_size = 4096, /*bytes*/
118 : .return_bus_width = 64, /*bytes*/
119 : .max_request_size = 256, /*bytes*/
120 :
121 : /* Depends on user class (client vs embedded, workstation, etc) */
122 : .percent_disp_bw_limit = 0.3f /*%*/
123 : };
124 :
125 : const struct dcn_ip_params dcn10_ip_defaults = {
126 : .rob_buffer_size_in_kbyte = 64,
127 : .det_buffer_size_in_kbyte = 164,
128 : .dpp_output_buffer_pixels = 2560,
129 : .opp_output_buffer_lines = 1,
130 : .pixel_chunk_size_in_kbyte = 8,
131 : .pte_enable = dcn_bw_yes,
132 : .pte_chunk_size = 2, /*kbytes*/
133 : .meta_chunk_size = 2, /*kbytes*/
134 : .writeback_chunk_size = 2, /*kbytes*/
135 : .odm_capability = dcn_bw_no,
136 : .dsc_capability = dcn_bw_no,
137 : .line_buffer_size = 589824, /*bit*/
138 : .max_line_buffer_lines = 12,
139 : .is_line_buffer_bpp_fixed = dcn_bw_no,
140 : .line_buffer_fixed_bpp = dcn_bw_na,
141 : .writeback_luma_buffer_size = 12, /*kbytes*/
142 : .writeback_chroma_buffer_size = 8, /*kbytes*/
143 : .max_num_dpp = 4,
144 : .max_num_writeback = 2,
145 : .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
146 : .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
147 : .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
148 : .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
149 : .max_hscl_ratio = 4,
150 : .max_vscl_ratio = 4,
151 : .max_hscl_taps = 8,
152 : .max_vscl_taps = 8,
153 : .pte_buffer_size_in_requests = 42,
154 : .dispclk_ramping_margin = 1, /*%*/
155 : .under_scan_factor = 1.11f,
156 : .max_inter_dcn_tile_repeaters = 8,
157 : .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
158 : .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
159 : .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
160 : };
161 :
162 0 : static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
163 : {
164 0 : switch (sw_mode) {
165 : case DC_SW_LINEAR:
166 : return dcn_bw_sw_linear;
167 : case DC_SW_4KB_S:
168 0 : return dcn_bw_sw_4_kb_s;
169 : case DC_SW_4KB_D:
170 0 : return dcn_bw_sw_4_kb_d;
171 : case DC_SW_64KB_S:
172 0 : return dcn_bw_sw_64_kb_s;
173 : case DC_SW_64KB_D:
174 0 : return dcn_bw_sw_64_kb_d;
175 : case DC_SW_VAR_S:
176 0 : return dcn_bw_sw_var_s;
177 : case DC_SW_VAR_D:
178 0 : return dcn_bw_sw_var_d;
179 : case DC_SW_64KB_S_T:
180 0 : return dcn_bw_sw_64_kb_s_t;
181 : case DC_SW_64KB_D_T:
182 0 : return dcn_bw_sw_64_kb_d_t;
183 : case DC_SW_4KB_S_X:
184 0 : return dcn_bw_sw_4_kb_s_x;
185 : case DC_SW_4KB_D_X:
186 0 : return dcn_bw_sw_4_kb_d_x;
187 : case DC_SW_64KB_S_X:
188 0 : return dcn_bw_sw_64_kb_s_x;
189 : case DC_SW_64KB_D_X:
190 0 : return dcn_bw_sw_64_kb_d_x;
191 : case DC_SW_VAR_S_X:
192 0 : return dcn_bw_sw_var_s_x;
193 : case DC_SW_VAR_D_X:
194 0 : return dcn_bw_sw_var_d_x;
195 : case DC_SW_256B_S:
196 : case DC_SW_256_D:
197 : case DC_SW_256_R:
198 : case DC_SW_4KB_R:
199 : case DC_SW_64KB_R:
200 : case DC_SW_VAR_R:
201 : case DC_SW_4KB_R_X:
202 : case DC_SW_64KB_R_X:
203 : case DC_SW_VAR_R_X:
204 : default:
205 0 : BREAK_TO_DEBUGGER(); /*not in formula*/
206 0 : return dcn_bw_sw_4_kb_s;
207 : }
208 : }
209 :
210 : static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
211 : {
212 : switch (depth) {
213 : case LB_PIXEL_DEPTH_18BPP:
214 : return 18;
215 : case LB_PIXEL_DEPTH_24BPP:
216 : return 24;
217 : case LB_PIXEL_DEPTH_30BPP:
218 : return 30;
219 : case LB_PIXEL_DEPTH_36BPP:
220 : return 36;
221 : default:
222 : return 30;
223 : }
224 : }
225 :
226 : static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
227 : {
228 : switch (format) {
229 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
230 : case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
231 : return dcn_bw_rgb_sub_16;
232 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
233 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
234 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
235 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
236 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
237 : return dcn_bw_rgb_sub_32;
238 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
239 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
240 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
241 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
242 : return dcn_bw_rgb_sub_64;
243 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
244 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
245 : return dcn_bw_yuv420_sub_8;
246 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
247 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
248 : return dcn_bw_yuv420_sub_10;
249 : default:
250 : return dcn_bw_rgb_sub_32;
251 : }
252 : }
253 :
254 0 : enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
255 : {
256 0 : switch (sw_mode) {
257 : /* for 4/8/16 high tiles */
258 : case DC_SW_LINEAR:
259 : return dm_4k_tile;
260 : case DC_SW_4KB_S:
261 : case DC_SW_4KB_S_X:
262 : return dm_4k_tile;
263 : case DC_SW_64KB_S:
264 : case DC_SW_64KB_S_X:
265 : case DC_SW_64KB_S_T:
266 0 : return dm_64k_tile;
267 : case DC_SW_VAR_S:
268 : case DC_SW_VAR_S_X:
269 0 : return dm_256k_tile;
270 :
271 : /* For 64bpp 2 high tiles */
272 : case DC_SW_4KB_D:
273 : case DC_SW_4KB_D_X:
274 : return dm_4k_tile;
275 : case DC_SW_64KB_D:
276 : case DC_SW_64KB_D_X:
277 : case DC_SW_64KB_D_T:
278 0 : return dm_64k_tile;
279 : case DC_SW_VAR_D:
280 : case DC_SW_VAR_D_X:
281 0 : return dm_256k_tile;
282 :
283 : case DC_SW_4KB_R:
284 : case DC_SW_4KB_R_X:
285 : return dm_4k_tile;
286 : case DC_SW_64KB_R:
287 : case DC_SW_64KB_R_X:
288 0 : return dm_64k_tile;
289 : case DC_SW_VAR_R:
290 : case DC_SW_VAR_R_X:
291 0 : return dm_256k_tile;
292 :
293 : /* Unsupported swizzle modes for dcn */
294 : case DC_SW_256B_S:
295 : default:
296 0 : ASSERT(0); /* Not supported */
297 : return 0;
298 : }
299 : }
300 :
301 0 : static void pipe_ctx_to_e2e_pipe_params (
302 : const struct pipe_ctx *pipe,
303 : struct _vcs_dpi_display_pipe_params_st *input)
304 : {
305 0 : input->src.is_hsplit = false;
306 :
307 : /* stereo can never be split */
308 0 : if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
309 : pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
310 : /* reset the split group if it was already considered split. */
311 0 : input->src.hsplit_grp = pipe->pipe_idx;
312 0 : } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {
313 0 : input->src.is_hsplit = true;
314 0 : } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {
315 0 : input->src.is_hsplit = true;
316 : }
317 :
318 0 : if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
319 : /*
320 : * this method requires us to always re-calculate watermark when dcc change
321 : * between flip.
322 : */
323 0 : input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
324 : } else {
325 : /*
326 : * allow us to disable dcc on the fly without re-calculating WM
327 : *
328 : * extra overhead for DCC is quite small. for 1080p WM without
329 : * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
330 : */
331 : unsigned int bpe;
332 :
333 0 : input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
334 0 : dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
335 : }
336 0 : input->src.dcc_rate = 1;
337 0 : input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
338 0 : input->src.source_scan = dm_horz;
339 0 : input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
340 :
341 0 : input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
342 0 : input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
343 0 : input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
344 0 : input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
345 0 : input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
346 0 : input->src.cur0_bpp = 32;
347 :
348 0 : input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
349 :
350 0 : switch (pipe->plane_state->rotation) {
351 : case ROTATION_ANGLE_0:
352 : case ROTATION_ANGLE_180:
353 0 : input->src.source_scan = dm_horz;
354 0 : break;
355 : case ROTATION_ANGLE_90:
356 : case ROTATION_ANGLE_270:
357 0 : input->src.source_scan = dm_vert;
358 0 : break;
359 : default:
360 0 : ASSERT(0); /* Not supported */
361 : break;
362 : }
363 :
364 : /* TODO: Fix pixel format mappings */
365 0 : switch (pipe->plane_state->format) {
366 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
367 : case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
368 0 : input->src.source_format = dm_420_8;
369 0 : input->src.viewport_width_c = input->src.viewport_width / 2;
370 0 : input->src.viewport_height_c = input->src.viewport_height / 2;
371 0 : break;
372 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
373 : case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
374 0 : input->src.source_format = dm_420_10;
375 0 : input->src.viewport_width_c = input->src.viewport_width / 2;
376 0 : input->src.viewport_height_c = input->src.viewport_height / 2;
377 0 : break;
378 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
379 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
380 : case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
381 : case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
382 0 : input->src.source_format = dm_444_64;
383 0 : input->src.viewport_width_c = input->src.viewport_width;
384 0 : input->src.viewport_height_c = input->src.viewport_height;
385 0 : break;
386 : case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
387 0 : input->src.source_format = dm_rgbe_alpha;
388 0 : input->src.viewport_width_c = input->src.viewport_width;
389 0 : input->src.viewport_height_c = input->src.viewport_height;
390 0 : break;
391 : default:
392 0 : input->src.source_format = dm_444_32;
393 0 : input->src.viewport_width_c = input->src.viewport_width;
394 0 : input->src.viewport_height_c = input->src.viewport_height;
395 0 : break;
396 : }
397 :
398 0 : input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
399 0 : input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
400 0 : input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
401 0 : input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
402 0 : if (input->scale_ratio_depth.vinit < 1.0)
403 0 : input->scale_ratio_depth.vinit = 1;
404 0 : input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
405 0 : input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
406 0 : input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
407 0 : input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
408 0 : input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
409 0 : input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
410 0 : if (input->scale_ratio_depth.vinit_c < 1.0)
411 0 : input->scale_ratio_depth.vinit_c = 1;
412 0 : switch (pipe->plane_res.scl_data.lb_params.depth) {
413 : case LB_PIXEL_DEPTH_30BPP:
414 0 : input->scale_ratio_depth.lb_depth = 30; break;
415 : case LB_PIXEL_DEPTH_36BPP:
416 0 : input->scale_ratio_depth.lb_depth = 36; break;
417 : default:
418 0 : input->scale_ratio_depth.lb_depth = 24; break;
419 : }
420 :
421 :
422 0 : input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
423 0 : + pipe->stream->timing.v_border_bottom;
424 :
425 0 : input->dest.recout_width = pipe->plane_res.scl_data.recout.width;
426 0 : input->dest.recout_height = pipe->plane_res.scl_data.recout.height;
427 :
428 0 : input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;
429 0 : input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;
430 :
431 0 : input->dest.htotal = pipe->stream->timing.h_total;
432 0 : input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
433 0 : input->dest.hblank_end = input->dest.hblank_start
434 0 : - pipe->stream->timing.h_addressable
435 0 : - pipe->stream->timing.h_border_left
436 0 : - pipe->stream->timing.h_border_right;
437 :
438 0 : input->dest.vtotal = pipe->stream->timing.v_total;
439 0 : input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
440 0 : input->dest.vblank_end = input->dest.vblank_start
441 0 : - pipe->stream->timing.v_addressable
442 0 : - pipe->stream->timing.v_border_bottom
443 0 : - pipe->stream->timing.v_border_top;
444 0 : input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
445 0 : input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
446 0 : input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
447 0 : input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
448 0 : input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
449 :
450 0 : }
451 :
452 0 : static void dcn_bw_calc_rq_dlg_ttu(
453 : const struct dc *dc,
454 : const struct dcn_bw_internal_vars *v,
455 : struct pipe_ctx *pipe,
456 : int in_idx)
457 : {
458 0 : struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
459 0 : struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
460 0 : struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
461 0 : struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
462 0 : struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;
463 0 : struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;
464 0 : struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;
465 0 : float total_active_bw = 0;
466 0 : float total_prefetch_bw = 0;
467 0 : int total_flip_bytes = 0;
468 : int i;
469 :
470 0 : memset(dlg_regs, 0, sizeof(*dlg_regs));
471 0 : memset(ttu_regs, 0, sizeof(*ttu_regs));
472 0 : memset(rq_regs, 0, sizeof(*rq_regs));
473 0 : memset(rq_param, 0, sizeof(*rq_param));
474 0 : memset(dlg_sys_param, 0, sizeof(*dlg_sys_param));
475 0 : memset(input, 0, sizeof(*input));
476 :
477 0 : for (i = 0; i < number_of_planes; i++) {
478 0 : total_active_bw += v->read_bandwidth[i];
479 0 : total_prefetch_bw += v->prefetch_bandwidth[i];
480 0 : total_flip_bytes += v->total_immediate_flip_bytes[i];
481 : }
482 0 : dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
483 0 : if (dlg_sys_param->total_flip_bw < 0.0)
484 0 : dlg_sys_param->total_flip_bw = 0;
485 :
486 0 : dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark;
487 0 : dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
488 0 : dlg_sys_param->t_urg_wm_us = v->urgent_watermark;
489 0 : dlg_sys_param->t_extra_us = v->urgent_extra_latency;
490 0 : dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
491 0 : dlg_sys_param->total_flip_bytes = total_flip_bytes;
492 :
493 0 : pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);
494 0 : input->clks_cfg.dcfclk_mhz = v->dcfclk;
495 0 : input->clks_cfg.dispclk_mhz = v->dispclk;
496 0 : input->clks_cfg.dppclk_mhz = v->dppclk;
497 0 : input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
498 0 : input->clks_cfg.socclk_mhz = v->socclk;
499 0 : input->clks_cfg.voltage = v->voltage_level;
500 : // dc->dml.logger = pool->base.logger;
501 0 : input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
502 0 : input->dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
503 : //input[in_idx].dout.output_standard;
504 :
505 : /*todo: soc->sr_enter_plus_exit_time??*/
506 :
507 0 : dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);
508 0 : dml1_extract_rq_regs(dml, rq_regs, rq_param);
509 0 : dml1_rq_dlg_get_dlg_params(
510 : dml,
511 : dlg_regs,
512 : ttu_regs,
513 0 : &rq_param->dlg,
514 : dlg_sys_param,
515 : input,
516 : true,
517 : true,
518 0 : v->pte_enable == dcn_bw_yes,
519 0 : pipe->plane_state->flip_immediate);
520 0 : }
521 :
522 0 : static void split_stream_across_pipes(
523 : struct resource_context *res_ctx,
524 : const struct resource_pool *pool,
525 : struct pipe_ctx *primary_pipe,
526 : struct pipe_ctx *secondary_pipe)
527 : {
528 0 : int pipe_idx = secondary_pipe->pipe_idx;
529 :
530 0 : if (!primary_pipe->plane_state)
531 : return;
532 :
533 0 : *secondary_pipe = *primary_pipe;
534 :
535 0 : secondary_pipe->pipe_idx = pipe_idx;
536 0 : secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
537 0 : secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
538 0 : secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
539 0 : secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
540 0 : secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
541 0 : secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
542 0 : if (primary_pipe->bottom_pipe) {
543 0 : ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
544 0 : secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
545 0 : secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
546 : }
547 0 : primary_pipe->bottom_pipe = secondary_pipe;
548 0 : secondary_pipe->top_pipe = primary_pipe;
549 :
550 0 : resource_build_scaling_params(primary_pipe);
551 0 : resource_build_scaling_params(secondary_pipe);
552 : }
553 :
554 : #if 0
555 : static void calc_wm_sets_and_perf_params(
556 : struct dc_state *context,
557 : struct dcn_bw_internal_vars *v)
558 : {
559 : /* Calculate set A last to keep internal var state consistent for required config */
560 : if (v->voltage_level < 2) {
561 : v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
562 : v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
563 : v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
564 : dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
565 :
566 : context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
567 : v->stutter_exit_watermark * 1000;
568 : context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
569 : v->stutter_enter_plus_exit_watermark * 1000;
570 : context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
571 : v->dram_clock_change_watermark * 1000;
572 : context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 : context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
574 :
575 : v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
576 : v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
577 : v->dcfclk = v->dcfclkv_nom0p8;
578 : dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
579 :
580 : context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
581 : v->stutter_exit_watermark * 1000;
582 : context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
583 : v->stutter_enter_plus_exit_watermark * 1000;
584 : context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
585 : v->dram_clock_change_watermark * 1000;
586 : context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 : context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
588 : }
589 :
590 : if (v->voltage_level < 3) {
591 : v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
592 : v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
593 : v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
594 : v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
595 : v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
596 : v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
597 : v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
598 : v->dcfclk = v->dcfclkv_max0p9;
599 : dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
600 :
601 : context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
602 : v->stutter_exit_watermark * 1000;
603 : context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
604 : v->stutter_enter_plus_exit_watermark * 1000;
605 : context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
606 : v->dram_clock_change_watermark * 1000;
607 : context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
608 : context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
609 : }
610 :
611 : v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
612 : v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
613 : v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
614 : v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
615 : v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
616 : v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
617 : v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
618 : v->dcfclk = v->dcfclk_per_state[v->voltage_level];
619 : dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
620 :
621 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
622 : v->stutter_exit_watermark * 1000;
623 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
624 : v->stutter_enter_plus_exit_watermark * 1000;
625 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
626 : v->dram_clock_change_watermark * 1000;
627 : context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
628 : context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
629 : if (v->voltage_level >= 2) {
630 : context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
631 : context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
632 : }
633 : if (v->voltage_level >= 3)
634 : context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
635 : }
636 : #endif
637 :
638 0 : static bool dcn_bw_apply_registry_override(struct dc *dc)
639 : {
640 0 : bool updated = false;
641 :
642 0 : if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
643 0 : && dc->debug.sr_exit_time_ns) {
644 0 : updated = true;
645 0 : dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
646 : }
647 :
648 0 : if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
649 0 : != dc->debug.sr_enter_plus_exit_time_ns
650 0 : && dc->debug.sr_enter_plus_exit_time_ns) {
651 0 : updated = true;
652 0 : dc->dcn_soc->sr_enter_plus_exit_time =
653 0 : dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
654 : }
655 :
656 0 : if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
657 0 : && dc->debug.urgent_latency_ns) {
658 0 : updated = true;
659 0 : dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
660 : }
661 :
662 0 : if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
663 0 : != dc->debug.percent_of_ideal_drambw
664 0 : && dc->debug.percent_of_ideal_drambw) {
665 0 : updated = true;
666 0 : dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
667 : dc->debug.percent_of_ideal_drambw;
668 : }
669 :
670 0 : if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
671 0 : != dc->debug.dram_clock_change_latency_ns
672 0 : && dc->debug.dram_clock_change_latency_ns) {
673 0 : updated = true;
674 0 : dc->dcn_soc->dram_clock_change_latency =
675 0 : dc->debug.dram_clock_change_latency_ns / 1000.0;
676 : }
677 :
678 0 : return updated;
679 : }
680 :
681 : static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
682 : {
683 : /*
684 : * disable optional pipe split by lower dispclk bounding box
685 : * at DPM0
686 : */
687 0 : v->max_dispclk[0] = v->max_dppclk_vmin0p65;
688 : }
689 :
690 : static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
691 : unsigned int pixel_rate_100hz)
692 : {
693 0 : float pixel_rate_mhz = pixel_rate_100hz / 10000;
694 :
695 : /*
696 : * force enabling pipe split by lower dpp clock for DPM0 to just
697 : * below the specify pixel_rate, so bw calc would split pipe.
698 : */
699 0 : if (pixel_rate_mhz < v->max_dppclk[0])
700 0 : v->max_dppclk[0] = pixel_rate_mhz;
701 : }
702 :
703 0 : static void hack_bounding_box(struct dcn_bw_internal_vars *v,
704 : struct dc_debug_options *dbg,
705 : struct dc_state *context)
706 : {
707 : int i;
708 :
709 0 : for (i = 0; i < MAX_PIPES; i++) {
710 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
711 :
712 : /**
713 : * Workaround for avoiding pipe-split in cases where we'd split
714 : * planes that are too small, resulting in splits that aren't
715 : * valid for the scaler.
716 : */
717 0 : if (pipe->plane_state &&
718 0 : (pipe->plane_state->dst_rect.width <= 16 ||
719 0 : pipe->plane_state->dst_rect.height <= 16 ||
720 0 : pipe->plane_state->src_rect.width <= 16 ||
721 0 : pipe->plane_state->src_rect.height <= 16)) {
722 0 : hack_disable_optional_pipe_split(v);
723 : return;
724 : }
725 : }
726 :
727 0 : if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
728 0 : hack_disable_optional_pipe_split(v);
729 :
730 0 : if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
731 0 : context->stream_count >= 2)
732 0 : hack_disable_optional_pipe_split(v);
733 :
734 0 : if (context->stream_count == 1 &&
735 0 : dbg->force_single_disp_pipe_split)
736 0 : hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
737 : }
738 :
739 : static unsigned int get_highest_allowed_voltage_level(bool is_vmin_only_asic)
740 : {
741 : /* for low power RV2 variants, the highest voltage level we want is 0 */
742 0 : if (is_vmin_only_asic)
743 : return 0;
744 : else /* we are ok with all levels */
745 : return 4;
746 : }
747 :
748 0 : bool dcn_validate_bandwidth(
749 : struct dc *dc,
750 : struct dc_state *context,
751 : bool fast_validate)
752 : {
753 : /*
754 : * we want a breakdown of the various stages of validation, which the
755 : * perf_trace macro doesn't support
756 : */
757 0 : BW_VAL_TRACE_SETUP();
758 :
759 0 : const struct resource_pool *pool = dc->res_pool;
760 0 : struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
761 : int i, input_idx, k;
762 : int vesa_sync_start, asic_blank_end, asic_blank_start;
763 : bool bw_limit_pass;
764 : float bw_limit;
765 :
766 0 : PERFORMANCE_TRACE_START();
767 :
768 0 : BW_VAL_TRACE_COUNT();
769 :
770 0 : if (dcn_bw_apply_registry_override(dc))
771 0 : dcn_bw_sync_calcs_and_dml(dc);
772 :
773 0 : memset(v, 0, sizeof(*v));
774 :
775 0 : v->sr_exit_time = dc->dcn_soc->sr_exit_time;
776 0 : v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
777 0 : v->urgent_latency = dc->dcn_soc->urgent_latency;
778 0 : v->write_back_latency = dc->dcn_soc->write_back_latency;
779 0 : v->percent_of_ideal_drambw_received_after_urg_latency =
780 0 : dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
781 :
782 0 : v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
783 0 : v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
784 0 : v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
785 0 : v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
786 :
787 0 : v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
788 0 : v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
789 0 : v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
790 0 : v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
791 :
792 0 : v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
793 0 : v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
794 0 : v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
795 0 : v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
796 :
797 0 : v->socclk = dc->dcn_soc->socclk;
798 :
799 0 : v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
800 0 : v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
801 0 : v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
802 0 : v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
803 :
804 0 : v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
805 0 : v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
806 0 : v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
807 0 : v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
808 :
809 0 : v->downspreading = dc->dcn_soc->downspreading;
810 0 : v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
811 0 : v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
812 0 : v->number_of_channels = dc->dcn_soc->number_of_channels;
813 0 : v->vmm_page_size = dc->dcn_soc->vmm_page_size;
814 0 : v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
815 0 : v->return_bus_width = dc->dcn_soc->return_bus_width;
816 :
817 0 : v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
818 0 : v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
819 0 : v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
820 0 : v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
821 0 : v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
822 0 : v->pte_enable = dc->dcn_ip->pte_enable;
823 0 : v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
824 0 : v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
825 0 : v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
826 0 : v->odm_capability = dc->dcn_ip->odm_capability;
827 0 : v->dsc_capability = dc->dcn_ip->dsc_capability;
828 0 : v->line_buffer_size = dc->dcn_ip->line_buffer_size;
829 0 : v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
830 0 : v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
831 0 : v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
832 0 : v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
833 0 : v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
834 0 : v->max_num_dpp = dc->dcn_ip->max_num_dpp;
835 0 : v->max_num_writeback = dc->dcn_ip->max_num_writeback;
836 0 : v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
837 0 : v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
838 0 : v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
839 0 : v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
840 0 : v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
841 0 : v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
842 0 : v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
843 0 : v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
844 0 : v->under_scan_factor = dc->dcn_ip->under_scan_factor;
845 0 : v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
846 0 : v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
847 0 : v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
848 0 : v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
849 0 : dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
850 0 : v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
851 0 : dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
852 :
853 0 : v->voltage[5] = dcn_bw_no_support;
854 0 : v->voltage[4] = dcn_bw_v_max0p9;
855 0 : v->voltage[3] = dcn_bw_v_max0p9;
856 0 : v->voltage[2] = dcn_bw_v_nom0p8;
857 0 : v->voltage[1] = dcn_bw_v_mid0p72;
858 0 : v->voltage[0] = dcn_bw_v_min0p65;
859 0 : v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
860 0 : v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
861 0 : v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
862 0 : v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
863 0 : v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
864 0 : v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
865 0 : v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
866 0 : v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
867 0 : v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
868 0 : v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
869 0 : v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
870 0 : v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
871 0 : v->max_dispclk[5] = v->max_dispclk_vmax0p9;
872 0 : v->max_dispclk[4] = v->max_dispclk_vmax0p9;
873 0 : v->max_dispclk[3] = v->max_dispclk_vmax0p9;
874 0 : v->max_dispclk[2] = v->max_dispclk_vnom0p8;
875 0 : v->max_dispclk[1] = v->max_dispclk_vmid0p72;
876 0 : v->max_dispclk[0] = v->max_dispclk_vmin0p65;
877 0 : v->max_dppclk[5] = v->max_dppclk_vmax0p9;
878 0 : v->max_dppclk[4] = v->max_dppclk_vmax0p9;
879 0 : v->max_dppclk[3] = v->max_dppclk_vmax0p9;
880 0 : v->max_dppclk[2] = v->max_dppclk_vnom0p8;
881 0 : v->max_dppclk[1] = v->max_dppclk_vmid0p72;
882 0 : v->max_dppclk[0] = v->max_dppclk_vmin0p65;
883 0 : v->phyclk_per_state[5] = v->phyclkv_max0p9;
884 0 : v->phyclk_per_state[4] = v->phyclkv_max0p9;
885 0 : v->phyclk_per_state[3] = v->phyclkv_max0p9;
886 0 : v->phyclk_per_state[2] = v->phyclkv_nom0p8;
887 0 : v->phyclk_per_state[1] = v->phyclkv_mid0p72;
888 0 : v->phyclk_per_state[0] = v->phyclkv_min0p65;
889 0 : v->synchronized_vblank = dcn_bw_no;
890 0 : v->ta_pscalculation = dcn_bw_override;
891 0 : v->allow_different_hratio_vratio = dcn_bw_yes;
892 :
893 0 : for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
894 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
895 :
896 0 : if (!pipe->stream)
897 0 : continue;
898 : /* skip all but first of split pipes */
899 0 : if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
900 0 : continue;
901 :
902 0 : v->underscan_output[input_idx] = false; /* taken care of in recout already*/
903 0 : v->interlace_output[input_idx] = false;
904 :
905 0 : v->htotal[input_idx] = pipe->stream->timing.h_total;
906 0 : v->vtotal[input_idx] = pipe->stream->timing.v_total;
907 0 : v->vactive[input_idx] = pipe->stream->timing.v_addressable +
908 0 : pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
909 0 : v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
910 0 : - v->vactive[input_idx]
911 0 : - pipe->stream->timing.v_front_porch;
912 0 : v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
913 0 : if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
914 0 : v->pixel_clock[input_idx] *= 2;
915 0 : if (!pipe->plane_state) {
916 0 : v->dcc_enable[input_idx] = dcn_bw_yes;
917 0 : v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
918 0 : v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
919 0 : v->lb_bit_per_pixel[input_idx] = 30;
920 0 : v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
921 0 : v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
922 : /*
923 : * for cases where we have no plane, we want to validate up to 1080p
924 : * source size because here we are only interested in if the output
925 : * timing is supported or not. if we cannot support native resolution
926 : * of the high res display, we still want to support lower res up scale
927 : * to native
928 : */
929 0 : if (v->viewport_width[input_idx] > 1920)
930 0 : v->viewport_width[input_idx] = 1920;
931 0 : if (v->viewport_height[input_idx] > 1080)
932 0 : v->viewport_height[input_idx] = 1080;
933 0 : v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
934 0 : v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
935 0 : v->override_hta_ps[input_idx] = 1;
936 0 : v->override_vta_ps[input_idx] = 1;
937 0 : v->override_hta_pschroma[input_idx] = 1;
938 0 : v->override_vta_pschroma[input_idx] = 1;
939 0 : v->source_scan[input_idx] = dcn_bw_hor;
940 :
941 : } else {
942 0 : v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;
943 0 : v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
944 0 : v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
945 0 : v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
946 0 : if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
947 0 : if (pipe->plane_state->rotation % 2 == 0) {
948 0 : int viewport_end = pipe->plane_res.scl_data.viewport.width
949 0 : + pipe->plane_res.scl_data.viewport.x;
950 0 : int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
951 0 : + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
952 :
953 0 : if (viewport_end > viewport_b_end)
954 0 : v->viewport_width[input_idx] = viewport_end
955 0 : - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
956 : else
957 0 : v->viewport_width[input_idx] = viewport_b_end
958 0 : - pipe->plane_res.scl_data.viewport.x;
959 : } else {
960 0 : int viewport_end = pipe->plane_res.scl_data.viewport.height
961 0 : + pipe->plane_res.scl_data.viewport.y;
962 0 : int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
963 0 : + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
964 :
965 0 : if (viewport_end > viewport_b_end)
966 0 : v->viewport_height[input_idx] = viewport_end
967 0 : - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
968 : else
969 0 : v->viewport_height[input_idx] = viewport_b_end
970 0 : - pipe->plane_res.scl_data.viewport.y;
971 : }
972 0 : v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
973 0 : + pipe->bottom_pipe->plane_res.scl_data.recout.width;
974 : }
975 :
976 0 : if (pipe->plane_state->rotation % 2 == 0) {
977 0 : ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
978 : || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
979 0 : ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
980 : || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
981 : } else {
982 0 : ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
983 : || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
984 0 : ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
985 : || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
986 : }
987 :
988 0 : if (dc->debug.optimized_watermark) {
989 : /*
990 : * this method requires us to always re-calculate watermark when dcc change
991 : * between flip.
992 : */
993 0 : v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
994 : } else {
995 : /*
996 : * allow us to disable dcc on the fly without re-calculating WM
997 : *
998 : * extra overhead for DCC is quite small. for 1080p WM without
999 : * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
1000 : */
1001 : unsigned int bpe;
1002 :
1003 0 : v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
1004 0 : pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
1005 : }
1006 :
1007 0 : v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
1008 0 : pipe->plane_state->format);
1009 0 : v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
1010 : pipe->plane_state->tiling_info.gfx9.swizzle);
1011 0 : v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
1012 0 : v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
1013 0 : v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
1014 0 : v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
1015 0 : v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
1016 : /*
1017 : * Spreadsheet doesn't handle taps_c is one properly,
1018 : * need to force Chroma to always be scaled to pass
1019 : * bandwidth validation.
1020 : */
1021 0 : if (v->override_hta_pschroma[input_idx] == 1)
1022 0 : v->override_hta_pschroma[input_idx] = 2;
1023 0 : if (v->override_vta_pschroma[input_idx] == 1)
1024 0 : v->override_vta_pschroma[input_idx] = 2;
1025 0 : v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
1026 : }
1027 0 : if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
1028 0 : v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
1029 0 : v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
1030 0 : v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
1031 0 : PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
1032 0 : v->output[input_idx] = pipe->stream->signal ==
1033 0 : SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
1034 0 : v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
1035 0 : if (v->output[input_idx] == dcn_bw_hdmi) {
1036 0 : switch (pipe->stream->timing.display_color_depth) {
1037 : case COLOR_DEPTH_101010:
1038 0 : v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
1039 0 : break;
1040 : case COLOR_DEPTH_121212:
1041 0 : v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc;
1042 0 : break;
1043 : case COLOR_DEPTH_161616:
1044 0 : v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc;
1045 0 : break;
1046 : default:
1047 : break;
1048 : }
1049 : }
1050 :
1051 0 : input_idx++;
1052 : }
1053 0 : v->number_of_active_planes = input_idx;
1054 :
1055 0 : scaler_settings_calculation(v);
1056 :
1057 0 : hack_bounding_box(v, &dc->debug, context);
1058 :
1059 0 : mode_support_and_system_configuration(v);
1060 :
1061 : /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1062 0 : if (v->voltage_level != 0
1063 0 : && context->stream_count == 1
1064 0 : && dc->debug.force_single_disp_pipe_split) {
1065 0 : v->max_dppclk[0] = v->max_dppclk_vmin0p65;
1066 0 : mode_support_and_system_configuration(v);
1067 : }
1068 :
1069 0 : if (v->voltage_level == 0 &&
1070 : (dc->debug.sr_exit_time_dpm0_ns
1071 0 : || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1072 :
1073 0 : if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1074 0 : v->sr_enter_plus_exit_time =
1075 0 : dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1076 0 : if (dc->debug.sr_exit_time_dpm0_ns)
1077 0 : v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1078 0 : context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1079 0 : context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1080 0 : mode_support_and_system_configuration(v);
1081 : }
1082 :
1083 0 : display_pipe_configuration(v);
1084 :
1085 0 : for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1086 0 : if (v->source_scan[k] == dcn_bw_hor)
1087 0 : v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1088 : else
1089 0 : v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1090 : }
1091 0 : for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1092 0 : if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1093 0 : v->byte_per_pixel_dety[k] = 8.0;
1094 0 : v->byte_per_pixel_detc[k] = 0.0;
1095 0 : } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1096 0 : v->byte_per_pixel_dety[k] = 4.0;
1097 0 : v->byte_per_pixel_detc[k] = 0.0;
1098 0 : } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1099 0 : v->byte_per_pixel_dety[k] = 2.0;
1100 0 : v->byte_per_pixel_detc[k] = 0.0;
1101 0 : } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1102 0 : v->byte_per_pixel_dety[k] = 1.0;
1103 0 : v->byte_per_pixel_detc[k] = 2.0;
1104 : } else {
1105 0 : v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1106 0 : v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1107 : }
1108 : }
1109 :
1110 0 : v->total_data_read_bandwidth = 0.0;
1111 0 : for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1112 0 : v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1113 0 : dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1114 0 : v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1115 0 : dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1116 0 : v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1117 0 : v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1118 : }
1119 :
1120 0 : BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1121 :
1122 0 : if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1123 0 : float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1124 :
1125 0 : if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1126 : bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1127 0 : else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1128 : bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1129 0 : else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1130 : bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1131 : else
1132 0 : bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1133 :
1134 0 : if (bw_consumed < v->fabric_and_dram_bandwidth)
1135 0 : if (dc->debug.voltage_align_fclk)
1136 0 : bw_consumed = v->fabric_and_dram_bandwidth;
1137 :
1138 0 : display_pipe_configuration(v);
1139 : /*calc_wm_sets_and_perf_params(context, v);*/
1140 : /* Only 1 set is used by dcn since no noticeable
1141 : * performance improvement was measured and due to hw bug DEGVIDCN10-254
1142 : */
1143 0 : dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1144 :
1145 0 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1146 0 : v->stutter_exit_watermark * 1000;
1147 0 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1148 0 : v->stutter_enter_plus_exit_watermark * 1000;
1149 0 : context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1150 0 : v->dram_clock_change_watermark * 1000;
1151 0 : context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1152 0 : context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1153 0 : context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1154 0 : context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1155 0 : context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1156 :
1157 0 : context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1158 0 : (ddr4_dram_factor_single_Channel * v->number_of_channels));
1159 0 : if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1160 0 : context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1161 :
1162 0 : context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1163 0 : context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1164 :
1165 0 : context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1166 0 : if (dc->debug.max_disp_clk == true)
1167 0 : context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1168 :
1169 0 : if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1170 0 : dc->debug.min_disp_clk_khz) {
1171 0 : context->bw_ctx.bw.dcn.clk.dispclk_khz =
1172 0 : dc->debug.min_disp_clk_khz;
1173 : }
1174 :
1175 0 : context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1176 0 : v->dispclk_dppclk_ratio;
1177 0 : context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1178 0 : switch (v->voltage_level) {
1179 : case 0:
1180 0 : context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1181 0 : (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1182 0 : break;
1183 : case 1:
1184 0 : context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1185 0 : (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1186 0 : break;
1187 : case 2:
1188 0 : context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1189 0 : (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1190 0 : break;
1191 : default:
1192 0 : context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1193 0 : (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1194 0 : break;
1195 : }
1196 :
1197 0 : BW_VAL_TRACE_END_WATERMARKS();
1198 :
1199 0 : for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1200 0 : struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1201 :
1202 : /* skip inactive pipe */
1203 0 : if (!pipe->stream)
1204 0 : continue;
1205 : /* skip all but first of split pipes */
1206 0 : if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1207 0 : continue;
1208 :
1209 0 : pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1210 0 : pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1211 0 : pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1212 0 : pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1213 :
1214 0 : pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1215 0 : pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1216 0 : vesa_sync_start = pipe->stream->timing.v_addressable +
1217 0 : pipe->stream->timing.v_border_bottom +
1218 0 : pipe->stream->timing.v_front_porch;
1219 :
1220 0 : asic_blank_end = (pipe->stream->timing.v_total -
1221 0 : vesa_sync_start -
1222 0 : pipe->stream->timing.v_border_top)
1223 0 : * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1224 :
1225 0 : asic_blank_start = asic_blank_end +
1226 0 : (pipe->stream->timing.v_border_top +
1227 0 : pipe->stream->timing.v_addressable +
1228 : pipe->stream->timing.v_border_bottom)
1229 0 : * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1230 :
1231 0 : pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1232 0 : pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1233 :
1234 0 : if (pipe->plane_state) {
1235 0 : struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1236 :
1237 0 : pipe->plane_state->update_flags.bits.full_update = 1;
1238 :
1239 0 : if (v->dpp_per_plane[input_idx] == 2 ||
1240 0 : ((pipe->stream->view_format ==
1241 0 : VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1242 : pipe->stream->view_format ==
1243 0 : VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1244 0 : (pipe->stream->timing.timing_3d_format ==
1245 0 : TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1246 : pipe->stream->timing.timing_3d_format ==
1247 : TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1248 0 : if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1249 : /* update previously split pipe */
1250 0 : hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1251 0 : hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1252 0 : hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1253 0 : hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1254 :
1255 0 : hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1256 0 : hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1257 0 : hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1258 0 : hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1259 : } else {
1260 : /* pipe not split previously needs split */
1261 0 : hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1262 0 : ASSERT(hsplit_pipe);
1263 0 : split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1264 : }
1265 :
1266 0 : dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1267 0 : } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1268 : /* merge previously split pipe */
1269 0 : pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1270 0 : if (hsplit_pipe->bottom_pipe)
1271 0 : hsplit_pipe->bottom_pipe->top_pipe = pipe;
1272 0 : hsplit_pipe->plane_state = NULL;
1273 0 : hsplit_pipe->stream = NULL;
1274 0 : hsplit_pipe->top_pipe = NULL;
1275 0 : hsplit_pipe->bottom_pipe = NULL;
1276 : /* Clear plane_res and stream_res */
1277 0 : memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1278 0 : memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1279 0 : resource_build_scaling_params(pipe);
1280 : }
1281 : /* for now important to do this after pipe split for building e2e params */
1282 0 : dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1283 : }
1284 :
1285 0 : input_idx++;
1286 : }
1287 0 : } else if (v->voltage_level == number_of_states_plus_one) {
1288 0 : BW_VAL_TRACE_SKIP(fail);
1289 0 : } else if (fast_validate) {
1290 0 : BW_VAL_TRACE_SKIP(fast);
1291 : }
1292 :
1293 0 : if (v->voltage_level == 0) {
1294 0 : context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1295 0 : dc->dcn_soc->sr_enter_plus_exit_time;
1296 0 : context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1297 : }
1298 :
1299 : /*
1300 : * BW limit is set to prevent display from impacting other system functions
1301 : */
1302 :
1303 0 : bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1304 0 : bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1305 :
1306 0 : PERFORMANCE_TRACE_END();
1307 0 : BW_VAL_TRACE_FINISH();
1308 :
1309 0 : if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
1310 : return true;
1311 : else
1312 : return false;
1313 : }
1314 :
1315 0 : static unsigned int dcn_find_normalized_clock_vdd_Level(
1316 : const struct dc *dc,
1317 : enum dm_pp_clock_type clocks_type,
1318 : int clocks_in_khz)
1319 : {
1320 0 : int vdd_level = dcn_bw_v_min0p65;
1321 :
1322 0 : if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1323 : return vdd_level;
1324 :
1325 0 : switch (clocks_type) {
1326 : case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1327 0 : if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1328 0 : vdd_level = dcn_bw_v_max0p91;
1329 0 : BREAK_TO_DEBUGGER();
1330 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1331 : vdd_level = dcn_bw_v_max0p9;
1332 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1333 : vdd_level = dcn_bw_v_nom0p8;
1334 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1335 : vdd_level = dcn_bw_v_mid0p72;
1336 : } else
1337 0 : vdd_level = dcn_bw_v_min0p65;
1338 : break;
1339 : case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1340 0 : if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1341 0 : vdd_level = dcn_bw_v_max0p91;
1342 0 : BREAK_TO_DEBUGGER();
1343 0 : } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1344 : vdd_level = dcn_bw_v_max0p9;
1345 0 : } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1346 : vdd_level = dcn_bw_v_nom0p8;
1347 0 : } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1348 : vdd_level = dcn_bw_v_mid0p72;
1349 : } else
1350 0 : vdd_level = dcn_bw_v_min0p65;
1351 : break;
1352 :
1353 : case DM_PP_CLOCK_TYPE_DPPCLK:
1354 0 : if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1355 0 : vdd_level = dcn_bw_v_max0p91;
1356 0 : BREAK_TO_DEBUGGER();
1357 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1358 : vdd_level = dcn_bw_v_max0p9;
1359 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1360 : vdd_level = dcn_bw_v_nom0p8;
1361 0 : } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1362 : vdd_level = dcn_bw_v_mid0p72;
1363 : } else
1364 0 : vdd_level = dcn_bw_v_min0p65;
1365 : break;
1366 :
1367 : case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1368 : {
1369 0 : unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1370 :
1371 0 : if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1372 0 : vdd_level = dcn_bw_v_max0p91;
1373 0 : BREAK_TO_DEBUGGER();
1374 0 : } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1375 : vdd_level = dcn_bw_v_max0p9;
1376 0 : } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1377 : vdd_level = dcn_bw_v_nom0p8;
1378 0 : } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1379 : vdd_level = dcn_bw_v_mid0p72;
1380 : } else
1381 0 : vdd_level = dcn_bw_v_min0p65;
1382 : }
1383 : break;
1384 :
1385 : case DM_PP_CLOCK_TYPE_DCFCLK:
1386 0 : if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1387 0 : vdd_level = dcn_bw_v_max0p91;
1388 0 : BREAK_TO_DEBUGGER();
1389 0 : } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1390 : vdd_level = dcn_bw_v_max0p9;
1391 0 : } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1392 : vdd_level = dcn_bw_v_nom0p8;
1393 0 : } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1394 : vdd_level = dcn_bw_v_mid0p72;
1395 : } else
1396 0 : vdd_level = dcn_bw_v_min0p65;
1397 : break;
1398 :
1399 : default:
1400 : break;
1401 : }
1402 0 : return vdd_level;
1403 : }
1404 :
1405 0 : unsigned int dcn_find_dcfclk_suits_all(
1406 : const struct dc *dc,
1407 : struct dc_clocks *clocks)
1408 : {
1409 : unsigned vdd_level, vdd_level_temp;
1410 : unsigned dcf_clk;
1411 :
1412 : /*find a common supported voltage level*/
1413 0 : vdd_level = dcn_find_normalized_clock_vdd_Level(
1414 : dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1415 0 : vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1416 : dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1417 :
1418 0 : vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1419 0 : vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1420 : dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1421 0 : vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1422 :
1423 0 : vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1424 : dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1425 0 : vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1426 0 : vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1427 : dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1428 :
1429 : /*find that level conresponding dcfclk*/
1430 0 : vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1431 0 : if (vdd_level == dcn_bw_v_max0p91) {
1432 0 : BREAK_TO_DEBUGGER();
1433 0 : dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1434 0 : } else if (vdd_level == dcn_bw_v_max0p9)
1435 0 : dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1436 0 : else if (vdd_level == dcn_bw_v_nom0p8)
1437 0 : dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000;
1438 0 : else if (vdd_level == dcn_bw_v_mid0p72)
1439 0 : dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000;
1440 : else
1441 0 : dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;
1442 :
1443 : DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1444 0 : return dcf_clk;
1445 : }
1446 :
1447 : static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1448 : {
1449 : int i;
1450 :
1451 0 : if (clks->num_levels == 0)
1452 : return false;
1453 :
1454 0 : for (i = 0; i < clks->num_levels; i++)
1455 : /* Ensure that the result is sane */
1456 0 : if (clks->data[i].clocks_in_khz == 0)
1457 : return false;
1458 :
1459 : return true;
1460 : }
1461 :
1462 0 : void dcn_bw_update_from_pplib(struct dc *dc)
1463 : {
1464 0 : struct dc_context *ctx = dc->ctx;
1465 0 : struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1466 : bool res;
1467 : unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx;
1468 :
1469 : /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1470 0 : res = dm_pp_get_clock_levels_by_type_with_voltage(
1471 : ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1472 :
1473 0 : if (res)
1474 : res = verify_clock_values(&fclks);
1475 :
1476 0 : if (res) {
1477 0 : ASSERT(fclks.num_levels);
1478 :
1479 0 : vmin0p65_idx = 0;
1480 0 : vmid0p72_idx = fclks.num_levels -
1481 0 : (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
1482 0 : vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
1483 0 : vmax0p9_idx = fclks.num_levels - 1;
1484 :
1485 0 : dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
1486 0 : 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
1487 0 : dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
1488 0 : dc->dcn_soc->number_of_channels *
1489 0 : (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
1490 0 : * ddr4_dram_factor_single_Channel / 1000.0;
1491 0 : dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
1492 0 : dc->dcn_soc->number_of_channels *
1493 0 : (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
1494 0 : * ddr4_dram_factor_single_Channel / 1000.0;
1495 0 : dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
1496 0 : dc->dcn_soc->number_of_channels *
1497 0 : (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
1498 0 : * ddr4_dram_factor_single_Channel / 1000.0;
1499 : } else
1500 0 : BREAK_TO_DEBUGGER();
1501 :
1502 0 : res = dm_pp_get_clock_levels_by_type_with_voltage(
1503 : ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1504 :
1505 0 : if (res)
1506 : res = verify_clock_values(&dcfclks);
1507 :
1508 0 : if (res && dcfclks.num_levels >= 3) {
1509 0 : dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1510 0 : dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1511 0 : dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1512 0 : dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1513 : } else
1514 0 : BREAK_TO_DEBUGGER();
1515 0 : }
1516 :
1517 0 : void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1518 : {
1519 0 : struct pp_smu_funcs_rv *pp = NULL;
1520 0 : struct pp_smu_wm_range_sets ranges = {0};
1521 : int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1522 0 : const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1523 :
1524 0 : if (dc->res_pool->pp_smu)
1525 0 : pp = &dc->res_pool->pp_smu->rv_funcs;
1526 0 : if (!pp || !pp->set_wm_ranges)
1527 0 : return;
1528 :
1529 0 : min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1530 0 : min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1531 0 : socclk_khz = dc->dcn_soc->socclk * 1000;
1532 :
1533 : /* Now notify PPLib/SMU about which Watermarks sets they should select
1534 : * depending on DPM state they are in. And update BW MGR GFX Engine and
1535 : * Memory clock member variables for Watermarks calculations for each
1536 : * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1537 : */
1538 : /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1539 : * care what the value is, hence min to overdrive level
1540 : */
1541 0 : ranges.num_reader_wm_sets = WM_SET_COUNT;
1542 0 : ranges.num_writer_wm_sets = WM_SET_COUNT;
1543 : ranges.reader_wm_sets[0].wm_inst = WM_A;
1544 0 : ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1545 0 : ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1546 0 : ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1547 0 : ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1548 : ranges.writer_wm_sets[0].wm_inst = WM_A;
1549 0 : ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1550 0 : ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1551 0 : ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1552 0 : ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1553 :
1554 0 : if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1555 : ranges.reader_wm_sets[0].wm_inst = WM_A;
1556 0 : ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1557 : ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1558 0 : ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1559 : ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1560 : ranges.writer_wm_sets[0].wm_inst = WM_A;
1561 0 : ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1562 : ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1563 0 : ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1564 : ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1565 : }
1566 :
1567 0 : ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1568 0 : ranges.reader_wm_sets[1].wm_inst = WM_B;
1569 :
1570 0 : ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1571 0 : ranges.reader_wm_sets[2].wm_inst = WM_C;
1572 :
1573 0 : ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1574 0 : ranges.reader_wm_sets[3].wm_inst = WM_D;
1575 :
1576 : /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1577 0 : pp->set_wm_ranges(&pp->pp_smu, &ranges);
1578 : }
1579 :
1580 0 : void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1581 : {
1582 : DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1583 : "sr_enter_plus_exit_time: %f ns\n"
1584 : "urgent_latency: %f ns\n"
1585 : "write_back_latency: %f ns\n"
1586 : "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1587 : "max_request_size: %d bytes\n"
1588 : "dcfclkv_max0p9: %f kHz\n"
1589 : "dcfclkv_nom0p8: %f kHz\n"
1590 : "dcfclkv_mid0p72: %f kHz\n"
1591 : "dcfclkv_min0p65: %f kHz\n"
1592 : "max_dispclk_vmax0p9: %f kHz\n"
1593 : "max_dispclk_vnom0p8: %f kHz\n"
1594 : "max_dispclk_vmid0p72: %f kHz\n"
1595 : "max_dispclk_vmin0p65: %f kHz\n"
1596 : "max_dppclk_vmax0p9: %f kHz\n"
1597 : "max_dppclk_vnom0p8: %f kHz\n"
1598 : "max_dppclk_vmid0p72: %f kHz\n"
1599 : "max_dppclk_vmin0p65: %f kHz\n"
1600 : "socclk: %f kHz\n"
1601 : "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1602 : "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1603 : "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1604 : "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1605 : "phyclkv_max0p9: %f kHz\n"
1606 : "phyclkv_nom0p8: %f kHz\n"
1607 : "phyclkv_mid0p72: %f kHz\n"
1608 : "phyclkv_min0p65: %f kHz\n"
1609 : "downspreading: %f %%\n"
1610 : "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1611 : "urgent_out_of_order_return_per_channel: %d Bytes\n"
1612 : "number_of_channels: %d\n"
1613 : "vmm_page_size: %d Bytes\n"
1614 : "dram_clock_change_latency: %f ns\n"
1615 : "return_bus_width: %d Bytes\n",
1616 : dc->dcn_soc->sr_exit_time * 1000,
1617 : dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1618 : dc->dcn_soc->urgent_latency * 1000,
1619 : dc->dcn_soc->write_back_latency * 1000,
1620 : dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1621 : dc->dcn_soc->max_request_size,
1622 : dc->dcn_soc->dcfclkv_max0p9 * 1000,
1623 : dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1624 : dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1625 : dc->dcn_soc->dcfclkv_min0p65 * 1000,
1626 : dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1627 : dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1628 : dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1629 : dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1630 : dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1631 : dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1632 : dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1633 : dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1634 : dc->dcn_soc->socclk * 1000,
1635 : dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1636 : dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1637 : dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1638 : dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1639 : dc->dcn_soc->phyclkv_max0p9 * 1000,
1640 : dc->dcn_soc->phyclkv_nom0p8 * 1000,
1641 : dc->dcn_soc->phyclkv_mid0p72 * 1000,
1642 : dc->dcn_soc->phyclkv_min0p65 * 1000,
1643 : dc->dcn_soc->downspreading * 100,
1644 : dc->dcn_soc->round_trip_ping_latency_cycles,
1645 : dc->dcn_soc->urgent_out_of_order_return_per_channel,
1646 : dc->dcn_soc->number_of_channels,
1647 : dc->dcn_soc->vmm_page_size,
1648 : dc->dcn_soc->dram_clock_change_latency * 1000,
1649 : dc->dcn_soc->return_bus_width);
1650 : DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1651 : "det_buffer_size_in_kbyte: %f\n"
1652 : "dpp_output_buffer_pixels: %f\n"
1653 : "opp_output_buffer_lines: %f\n"
1654 : "pixel_chunk_size_in_kbyte: %f\n"
1655 : "pte_enable: %d\n"
1656 : "pte_chunk_size: %d kbytes\n"
1657 : "meta_chunk_size: %d kbytes\n"
1658 : "writeback_chunk_size: %d kbytes\n"
1659 : "odm_capability: %d\n"
1660 : "dsc_capability: %d\n"
1661 : "line_buffer_size: %d bits\n"
1662 : "max_line_buffer_lines: %d\n"
1663 : "is_line_buffer_bpp_fixed: %d\n"
1664 : "line_buffer_fixed_bpp: %d\n"
1665 : "writeback_luma_buffer_size: %d kbytes\n"
1666 : "writeback_chroma_buffer_size: %d kbytes\n"
1667 : "max_num_dpp: %d\n"
1668 : "max_num_writeback: %d\n"
1669 : "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1670 : "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1671 : "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1672 : "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1673 : "max_hscl_ratio: %f\n"
1674 : "max_vscl_ratio: %f\n"
1675 : "max_hscl_taps: %d\n"
1676 : "max_vscl_taps: %d\n"
1677 : "pte_buffer_size_in_requests: %d\n"
1678 : "dispclk_ramping_margin: %f %%\n"
1679 : "under_scan_factor: %f %%\n"
1680 : "max_inter_dcn_tile_repeaters: %d\n"
1681 : "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1682 : "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1683 : "dcfclk_cstate_latency: %d\n",
1684 : dc->dcn_ip->rob_buffer_size_in_kbyte,
1685 : dc->dcn_ip->det_buffer_size_in_kbyte,
1686 : dc->dcn_ip->dpp_output_buffer_pixels,
1687 : dc->dcn_ip->opp_output_buffer_lines,
1688 : dc->dcn_ip->pixel_chunk_size_in_kbyte,
1689 : dc->dcn_ip->pte_enable,
1690 : dc->dcn_ip->pte_chunk_size,
1691 : dc->dcn_ip->meta_chunk_size,
1692 : dc->dcn_ip->writeback_chunk_size,
1693 : dc->dcn_ip->odm_capability,
1694 : dc->dcn_ip->dsc_capability,
1695 : dc->dcn_ip->line_buffer_size,
1696 : dc->dcn_ip->max_line_buffer_lines,
1697 : dc->dcn_ip->is_line_buffer_bpp_fixed,
1698 : dc->dcn_ip->line_buffer_fixed_bpp,
1699 : dc->dcn_ip->writeback_luma_buffer_size,
1700 : dc->dcn_ip->writeback_chroma_buffer_size,
1701 : dc->dcn_ip->max_num_dpp,
1702 : dc->dcn_ip->max_num_writeback,
1703 : dc->dcn_ip->max_dchub_topscl_throughput,
1704 : dc->dcn_ip->max_pscl_tolb_throughput,
1705 : dc->dcn_ip->max_lb_tovscl_throughput,
1706 : dc->dcn_ip->max_vscl_tohscl_throughput,
1707 : dc->dcn_ip->max_hscl_ratio,
1708 : dc->dcn_ip->max_vscl_ratio,
1709 : dc->dcn_ip->max_hscl_taps,
1710 : dc->dcn_ip->max_vscl_taps,
1711 : dc->dcn_ip->pte_buffer_size_in_requests,
1712 : dc->dcn_ip->dispclk_ramping_margin,
1713 : dc->dcn_ip->under_scan_factor * 100,
1714 : dc->dcn_ip->max_inter_dcn_tile_repeaters,
1715 : dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1716 : dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1717 : dc->dcn_ip->dcfclk_cstate_latency);
1718 :
1719 0 : dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1720 0 : dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1721 0 : dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1722 0 : dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1723 0 : dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1724 0 : dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1725 0 : dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1726 0 : dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1727 0 : dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1728 0 : dc->dcn_soc->round_trip_ping_latency_cycles;
1729 0 : dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1730 0 : dc->dcn_soc->urgent_out_of_order_return_per_channel;
1731 0 : dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1732 0 : dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1733 0 : dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1734 0 : dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1735 :
1736 0 : dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1737 0 : dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1738 0 : dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1739 0 : dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1740 0 : dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1741 0 : dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1742 0 : dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1743 0 : dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1744 0 : dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1745 0 : dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1746 0 : dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1747 0 : dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1748 0 : dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1749 0 : dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1750 0 : dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1751 0 : dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1752 0 : dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1753 0 : dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1754 0 : dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1755 0 : dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1756 0 : dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1757 0 : dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1758 0 : dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1759 0 : dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1760 0 : dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1761 : /*pte_buffer_size_in_requests missing in dml*/
1762 0 : dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1763 0 : dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1764 0 : dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1765 0 : dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1766 0 : dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1767 0 : dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1768 0 : dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1769 0 : dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1770 0 : }
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